User Manual
Table Of Contents
- Safety information
- Chapter 1: Product Introduction
- Chapter 2: Hardware Information
- 2.1 Chassis cover
- 2.2 Air ducts
- 2.3 Central Processing Unit (CPU)
- 2.4 System memory
- 2.5 Storage devices
- 2.6 Expansion slot
- 2.6.1 Installing an expansion card to the left PCIe riser card bracket
- 2.6.2 Installing an expansion card to the right PCIe riser card bracket
- 2.6.3 Installing a ASUS PIKE II card to the right PCIe riser card bracket
- 2.6.4 Installing an OCP 3.0 card to the OCP 3.0 slot
- 2.6.5 Installing an M.2 (NGFF) card
- 2.6.6 (optional) Installing the PFR module
- 2.6.7 Configuring an expansion card
- 2.7 Cable connections
- 2.8 Backplane cabling
- 2.9 Storage device configuration and cabling
- 2.10 Removable/optional components
- Chapter 3: Installation Options
- Chapter 4: Motherboard Information
- Chapter 5: BIOS Setup
- 5.1 Managing and updating your BIOS
- 5.2 BIOS setup program
- 5.3 Main menu
- 5.4 Performance Tuning menu
- 5.5 Advanced menu
- 5.5.1 Trusted Computing
- 5.5.2 PSP Firmware Versions
- 5.5.3 Redfish Host Interface Settings
- 5.5.4 APM Configuration
- 5.5.5 Onboard LAN Configuration
- 5.5.6 Serial Port Console Redirection
- 5.5.7 CPU Configuration
- 5.5.8 PCI Subsystem Settings
- 5.5.9 USB Configuration
- 5.5.10 Network Stack Configuration
- 5.5.11 CSM Configuration
- 5.5.12 NVMe Configuration
- 5.5.13 SATA Configuration
- 5.5.14 AMD Mem Configuration Status
- 5.6 Chipset menu
- 5.7 Security menu
- 5.8 Boot menu
- 5.9 Tool menu
- 5.10 Save & Exit menu
- 5.11 AMD CBS menu
- 5.12 Event Logs menu
- 5.13 Server Mgmt menu
- Chapter 6: Driver Installation
- Appendix
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ASUS RS520A-E11-RS12U
Core Watchdog
Core Watchdog Timer Enable [Auto]
Allows you to enable or disable CPU Watchdog Timer.
Configuration options: [Disable] [Enable] [Auto]
The following items are only available when Core Watchdog Timer Enable is set to
[Enabled].
Core Watchdog Timer Interval [Auto]
Configuration options: [21.461s] [10.730s] [5.364s] [2.681s] [1.340s] [669.41ms]
[334.05ms] [166.37ms] [82.53ms] [40.61ms] [20.970ms] [10.484ms] [5.241ms]
[2.620ms] [1.309ms] [654.08us] [326.4us] [162.56us] [80.64us] [39.68us] [Auto]
Core Watchdog Timer Severity [Auto]
Allows you to specify the CPU watch dog timer severity.
Configuration options: [No Error] [Transparent] [Corrected] [Deferred] [Uncorrected]
[Fatal] [Auto]
RedirectForReturnDis [Auto]
This option is from a workaround for GCC/C000005 issue for XV Core on CZ A0, setting
MSRC001_1029 Decode Configuration (DE_CFG) bit 14 [DecfgNoRdrctForReturns] to 1.
Configuration options: [Auto] [1] [0]
Platform First Error Handling [Auto]
This option is from a workaround for GCC/C000005 issue for XV Core on CZ A0, setting
MSRC001_1029 Decode Configuration (DE_CFG) bit 14 [DecfgNoRdrctForReturns] to 1.
Configuration options: [Auto] [1] [0]
Core Performance Boost [Auto]
This option allows you to enable or disable CPB.
Configuration options: [Disabled] [Auto]
Global C-state Control [Auto]
This option allows you to control IO based C-state generation and DF C-states.
Configuration options: [Disabled] [Enabled] [Auto]
Power Supply Idle Control [Auto]
Configuration options: [Low Current Idle] [Typical Current Idle] [Auto]
SEV ASID Count [Auto]
This field specifies the maximum valid ASID, which affects the maximum system physical
address space. 16TB of physical address space is available for systems that support 253
ASIDs, while 8TB of physical address space is available for systems that support 509 ASIDs.
Configuration options: [253 ASIDs] [509 ASIDs] [Auto]
SEV-ES ASID Space Limit Control [Auto]
Configuration options: [Auto] [Manual]