User Manual

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Chapter 5: BIOS Setup
TrdrdDd [Auto]
Specifies the Read to Read turnaround timing in a different DIMM.
Configuration options: [Auto] [1 Clk] [2 Clk] [3 Clk] [4 Clk] [5 Clk] [6 Clk] [7
Clk] [8 Clk] [9 Clk] [0Ah Clk] [0Bh Clk] [0Ch Clk] [0Dh Clk] [0Eh Clk] [0Fh
Clk]
ProcODT [Auto]
Specifies the Processor ODT.
Configuration options: [Auto] [High Impedance] [480 ohm] [240 ohm] [160
ohm] [120 ohm] [96 ohm] [80 ohm] [68.6 ohm] [60 ohm] [53.3 ohm] [48
ohm] [43.6 ohm] [40 ohm] [36.9 ohm] [34.3 ohm] [32 ohm] [30 ohm] [28.2
ohm]
DRAM Controller Configuration
DRAM Power Options
Power Down Enable [Auto]
Allows you to enable or disable power down mode.
Configuration options: [Disabled] [Enabled] [Auto]
Power Down Entry Delay [BB8]
Allows you to specify value at UMC::CH::DramTiming17 [19:8]
PwrDownDly.
SubUrgRefLowerBound [4]
Specifies the stored refresh limit required to enter sub-urgent refresh mode.
Constraint: SubUrgRefLowerBound <= UrgRefLimit. Valid value: 6~1
UrgRefLimit [6]
Specifies the stored refresh limit required to enter urgent refresh mode.
Constraint: SubUrgRefLowerBound <= UrgRefLimit. Valid value: 6~1
DRAM Maximum Activate Count [Auto]
Override DIMM SPD Byte 7 [3:0]. Maximum Activate Count (MAC). When
set to [Auto] it will be based on SPD setting.
Configuration options: [Untested MAC] [700 K] [600 K] [500 K] [400 K] [300
K] [200 K] [Unlimited MAC] [Auto]
DRAM Refresh Rate [7.8 usec]
Configuration options: [7.8 usec] [3.9 usec]
Self-Refresh Exit Staggering [Disabled]
Tcksrx += (Trfc/n * (UMC_Number % 4)), here n = 3 or 4.
Configuration options: [Disabled] [Trfc / 3] [Trfc / 4]
Does not apply the extra addition if set to [Disabled].
Cmd2T
Select between 1T and 2T mode on ADDR/CMD.
Configuration options: [Auto] [1T] [2T]
Gear Down Mode
Configuration options: [Auto] [Disabled] [Enabled]
CAD Bus Configuration
CAD Bus Timing User Controls [Auto]
Allows you to set the CAD bus signals to Auto or Manual.
Configuration options: [Auto] [Manual]