User Manual

Chapter 5: BIOS Setup
5-44
Hide Port? [No]
User can force to hide this root port from OS.
Conguration options: [No] [Yes]
MCTP [Yes]
Allows you to enable or disable MCTP.
Conguration options: [No] [Yes]
Port 1C/2B/2C/2D
Settings related to PCI Express Ports (0/1A/1B/1C/1D/2A/2B/2C/2D/3A/3B/3C/3D/4A4
B/4C/4D/5A/5B/5C/5D)
PCI-E Port [Auto]
Allows you to enable or disable the port and expose/hide its CFG space.
In auto mode, the BIOS will remove the EXP port if there is no device or
errors on that device and that device is not HP capable.
Conguration options: [Auto] [Disable] [Enable]
The following items appear only when
PCI-E Port
is set to
[Auto]
or
[Enable]
.
PCI-E Port Link Disable [No]
This option disabled the link so that the no training occurs but the CFG
space is still active.
Conguration options: [No] [Yes]
Link Speed [Auto]
Choose the Link Speed for this PCIe port.
Conguration options: [Auto] [Gen 1 (2.5 GT/s)] [Gen 2 (5 GT/s)] [Gen 3 (8
GT/s)]
Override Max Link Width [Auto]
Override the max link width that was set by bifurcation.
Conguration options: [Auto] [x1] [x2] [x4] [x8] [x16]
The following item appears only when
Link Speed
is set to
[Auto]
,
[Gen 2 (5 GT/s)]
, or
[Gen
3 (8 GT/s)]
.
PCI-E Port DeEmphasis [-3.5 dB]
De-Emphasis control (LNKCON2 [6]) for this PCIe port.
Conguration options: [-6.0 dB] [-3.5 dB]
PCI-E Port Clocking [Common]
Congure port clocking via LNKCON [6]. This refers to this component and
the down stream component.
Conguration options: [Distinct] [Common]
PCI-E Port Clock Gating [Enable]
Allows you to enable or disable Clock Gating for this PCIe port.
Conguration options: [Disable] [Enable]
Data Link Feature Exchange [Enable]
Allows you to enable or disable data link feature negotiation in the Data
Link Feature Capabilities (DLFCAP) register.
Conguration options: [Disable] [Enable]
PCI-E Port MPSS [Auto]
Congure Max Payload Size Supported in PCIe Device Capabilities
register.
Conguration options: [128B] [256B] [512B] [Auto]