Owner manual

5-205-20
5-205-20
5-20
Chapter 5: BIOS setupChapter 5: BIOS setup
Chapter 5: BIOS setupChapter 5: BIOS setup
Chapter 5: BIOS setup
5.4.35.4.3
5.4.35.4.3
5.4.3
ChipsetChipset
ChipsetChipset
Chipset
The Chipset menu allows you to change the advanced chipset settings.
Select an item then press <Enter> to display the sub-menu.
Advanced Chipset Settings
Configure DRAM Timing by SPD [Enabled]
Booting Graphic Adapter Priority [PCI Express/Int-VGA]
Internal Graphics Mode Select [Enabled, 8M]
Graphics Memory Type [Auto]
PCI-EX Ports Configuration
VC1 for Azalia & Root Ports [Disabled]
Microcode Updation [Enabled]Microcode Updation [Enabled]
Microcode Updation [Enabled]Microcode Updation [Enabled]
Microcode Updation [Enabled]
Enables or disables microcode updation.
Configuration options: [Disabled] [Enabled]
Max CPUID Value Limit [Disabled]Max CPUID Value Limit [Disabled]
Max CPUID Value Limit [Disabled]Max CPUID Value Limit [Disabled]
Max CPUID Value Limit [Disabled]
Enable this item to boot legacy operating systems that cannot support
CPUs with extended CPUID functions. Configuration options: [Disabled]
[Enabled]
Enhanced C1 Control [Auto]Enhanced C1 Control [Auto]
Enhanced C1 Control [Auto]Enhanced C1 Control [Auto]
Enhanced C1 Control [Auto]
When set to [Auto], the BIOS will automatically check the CPU’s capability
to enable the C1E support. In C1E mode, the CPU power consumption is
lower when idle. Configuration options: [Auto] [Disabled]
CPU Internal Thermal Control [Auto]CPU Internal Thermal Control [Auto]
CPU Internal Thermal Control [Auto]CPU Internal Thermal Control [Auto]
CPU Internal Thermal Control [Auto]
Disables or sets the CPU internal thermal control.
Configuration options: [Auto] [Disabled]
Hyper Threading Technology [Enabled]Hyper Threading Technology [Enabled]
Hyper Threading Technology [Enabled]Hyper Threading Technology [Enabled]
Hyper Threading Technology [Enabled]
Enables or disables the processor Hyper-Threading technology.
Configuration options: [Disabled] [Enabled]
Enable or disable
DRAM timing.