User's Manual

Platform Design Guidelines
Intel
®
Wireless-AC 9560 (Jefferson Peak)
April 2017 External Product Specification (EPS)
Document Number: 567240–1.0 Intel Confidential 49
Shared M.2 socket pins
The following M.2 pins are shared between different functions:
V3P3A, GND
This is the M.2 card power supply (3.3V) and Ground pins, respectively. Both have multiple pins on
the connector. These pins have the same purpose in either discrete or CNVi implementations, and
therefore are not affected by the Hybrid Key E scheme.
PCIe-1/CNVio
These are six pins that are assigned to the PCIe-1 bus in the M.2 standard pinout. This bus has three
differential pairs, two for the PCIe data lanes (one per direction) and one for the PCIe clock. In the
Hybrid Key E scheme, these signals are used for the CNVio interface from Pulsar to the companion RF
chip. Due to this sharing, the Hybrid Key E scheme does not support PCIe-1.
SDIO/CNVio
These are eight pins that are assigned to the SDIO bus in the M.2 standard pinout. This bus has eight
signals, four bi-directional for the SDIO data, one bi-directional command signal, one clock (SoC to
M.2) and two control (Reset SoC to M.2, Wake M.2 to SoC). In the Hybrid Key E scheme these signals
are used for CNVio interface the RF companion chip to Pulsar (siz for CNVio and two for ground). Due
to this sharing, the Hybrid Key E scheme does not support SDIO.
PCM/ClockReq and Reset
The standard M.2 defines four pins for a dedicated PCM audio serial bus. In the Hybrid Key E scheme,
two of these signals are used for CNVi Clock (from RF companion to SoC) and Reset (For SoC to RF
companion). Since the PCM serial bus is connected to PCH GPIO pins, and the CNVi clock request and
reset pins are also connected to PCH GPIO pins, it is possible to have support for both PCM bus and
CNVi signals by changing the PCH GPIO muxing function select. Due to this sharing, the Hybrid Key E
scheme can still support PCM (for discrete connectivity with PCM support).
UART (BT) / BRI and RGI
The standard M.2 defines four pins for a dedicated UART serial bus for Bluetooth. In the Hybrid Key E
scheme, all these signals are used for CNVi BRI (Bluetooth radio interface) and RGI (radio generic
interface), each comprised of two signals (one per direction). Since the UART serial bus is connected
to PCH GPIO pins, and the CNVi BRI and RGI are also connected to PCH GPIO pins, it is possible to
have support for both the UART bus and CNVi signals by changing the PCH GPIO muxing function. Due
to this sharing, the Hybrid Key E scheme can still support BT UART (for discrete connectivity with BT-
UART support).
SUSCLK/P_32K
These signals are both functionally similar. In the M.2 standard, this pin is optionally connected to a
32kHz RTC clock. In the Hybrid Key E scheme for CNVi, it should be connected to a 32kHz clock, which
is not optional, and must be driven by a valid 32kHz clock any time the RF companion module is
powered on. The 32kHz clock can come from a PCH pin or from a different source on the platform,
depending on the platform used. For CNL, this signal comes from the PCH. In Gemini Lake it is
connected to the SoC.
GND/LNA_EN
This signal is used for different purposes in CNVi and discrete, but in both cases should be connected
to ground; therefore, it does not affect functionality.