User's Manual
Table Of Contents
- 1 Introduction
- NOTE:
- NOTE:
- 2 Product Architecture
- 3 Electrical Specifications
- 4 Mechanical Specifications
- 5 Performance
- 1. BT in SW RF-KILL in all the tests
- 2. HB values refer to internal FE SKU
- 3. OS: Win10
- 1. Wi-Fi in SW RF-KILL in all the tests
- 2. OS: Win10
- 3. WsP is Master device
- 1. The TX power per MCS relate to IEEE, mask compliance and limited by regulatory TX power limits.
- 2. The values relate to internal FE SKU
- 3. The values are for typical device and typical conditions
- 1. Measured at ANT port
- 2. Typical means Nominal corner, AVG over non BE CHs. AVG over freq segment and chains
- 3. Max means over PVT
- NOTE: The throughput values relate to Intel® Skylake Platform and CPU, Single User.
- 6 Thermal Specifications
- 7 Regulatory
- 8 Dynamic Regulatory Solution
- 9 Platform Design Guidelines
- 9.1 Socket 1 key options for 2230 cards
- 9.1.1 Socket 1 Hybrid Key E scheme
- 9.1.2 Connectorized Hybrid Key E (2230) pin-out
- 9.1.3 Special considerations for the Hybrid Key E scheme
- 9.1.4 Soldered-down (1216) pin-out
- 9.1.5 Breakout example for JfP soldered-down module
- 9.1.6 Signal connection pitfalls
- 9.1.7 Pullups and pulldowns
- 9.1.8 IO connection scenarios and best practices
- 9.1.9 I/F specific guidelines
- 9.1.10 Connectivity module power control
- 9.1.11 Power supply de-coupling
- 9.1.12 Wi-Fi wireless disable and HW RF-KILL
- 9.1.13 M.2 Bluetooth HW RF-KILL
- 9.1.14 BIOS
- 9.1 Socket 1 key options for 2230 cards
Platform Design Guidelines
Intel
®
Wireless-AC 9560 (Jefferson Peak)
April 2017 External Product Specification (EPS)
Document Number: 567240–1.0 Intel Confidential 51
Table 9–1 Hybrid Key E interface mapping for different connectivity cards
M.2 Interface CNVi Discrete
PCIe-1 M.2 pins are not connected to the CRF.
Wi-Fi uses internal IOSF to interface the
host.
Used for Wi-Fi host interface
PCIe-2 Not functional
Pins are connected to CRF and Pulsar
CNVio and can’t be used as PCIe.
Not functional
Pins are connected to Pulsar CNVio and
can’t be used as PCIe.
Wi-Fi SDIO Not functional
Pins are connected to CRF and Pulsar
CNVio and can’t be used as SDIO.
Not functional
Pins are connected to Pulsar CNVio and
can’t be used as SDIO.
Wi-Fi CLINK M.2 pins are not connected to the CRF.
Wi-Fi uses internal CLINK to interface the
ME.
Used for Wi-Fi CSME interface
Wi-Fi RF-KILL Used (optional) Used (optional)
BT USB M.2 pins are not connected to the CRF.
BT uses internal U2U to interface the
host.
Used for BT USB interface
BT UART M.2 pins are not connected to the CRF.
BT uses internal UART to interface the
host.
Used for BT UART interface
BT I2S (Audio) M.2 pins are not connected to the CRF.
BT uses internal I2S to interface the host.
Used for BT I2S interface
BT wake M.2 pin is not connected to the CRF. BT
uses internal vGPIO.
Used for BT wake signal
BT RF-KILL Used (optional) Used (optional)
NFC Not functional
Pins are connected to A4WP bus and to
Refclock (38.4M system clock) and can’t
be used for NFC.
Not functional
Pins are connected to A4WP bus and to
Refclock (38.4M system clock) and can’t
be used for NFC.
I2C bus to A4WP Used for A4WP support to connect to
platform WPR module.
Used for A4WP support to connect to
platform WPR module.
3.3V Power supply
pins
Used per M.2 standard Used per M.2 standard
GND Used per M.2 standard Used per M.2 standard
9.1.4 Soldered-down (1216) pin-out
The RF Companion SD-1216 module has the same mechanical outline as the standard M.2 connectivity
type 1216-S3. The standard M.2 land pattern is modified to accommodate the proprietary the RF
companion module signals. Instead, it has an additional set of solder pads which don’t overlap with
the standard solder pads. This allows having a single motherboard design that can accommodate