User's Manual
Table Of Contents
- 1 Introduction
- NOTE:
- NOTE:
- 2 Product Architecture
- 3 Electrical Specifications
- 4 Mechanical Specifications
- 5 Performance
- 1. BT in SW RF-KILL in all the tests
- 2. HB values refer to internal FE SKU
- 3. OS: Win10
- 1. Wi-Fi in SW RF-KILL in all the tests
- 2. OS: Win10
- 3. WsP is Master device
- 1. The TX power per MCS relate to IEEE, mask compliance and limited by regulatory TX power limits.
- 2. The values relate to internal FE SKU
- 3. The values are for typical device and typical conditions
- 1. Measured at ANT port
- 2. Typical means Nominal corner, AVG over non BE CHs. AVG over freq segment and chains
- 3. Max means over PVT
- NOTE: The throughput values relate to Intel® Skylake Platform and CPU, Single User.
- 6 Thermal Specifications
- 7 Regulatory
- 8 Dynamic Regulatory Solution
- 9 Platform Design Guidelines
- 9.1 Socket 1 key options for 2230 cards
- 9.1.1 Socket 1 Hybrid Key E scheme
- 9.1.2 Connectorized Hybrid Key E (2230) pin-out
- 9.1.3 Special considerations for the Hybrid Key E scheme
- 9.1.4 Soldered-down (1216) pin-out
- 9.1.5 Breakout example for JfP soldered-down module
- 9.1.6 Signal connection pitfalls
- 9.1.7 Pullups and pulldowns
- 9.1.8 IO connection scenarios and best practices
- 9.1.9 I/F specific guidelines
- 9.1.10 Connectivity module power control
- 9.1.11 Power supply de-coupling
- 9.1.12 Wi-Fi wireless disable and HW RF-KILL
- 9.1.13 M.2 Bluetooth HW RF-KILL
- 9.1.14 BIOS
- 9.1 Socket 1 key options for 2230 cards
Platform Design Guidelines
Intel
®
Wireless-AC 9560 (Jefferson Peak)
April 2017 External Product Specification (EPS)
Document Number: 567240–1.0 Intel Confidential 55
Figure 9–6 Board layout example showing breakout from JfP 1216 pads (dual design for
CNVi and discrete)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
25
G2
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
G3
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
51
50
49
52
G1 G4
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A24
A23
A7
A25
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A33
A34
A50
A32
A26 A27 A28 A29 A30 A31
G ND
NC
NC
NC
NC
NC
NC
NC
G ND
NC
NC
NC
WT_CLK+
WT_CLK-
WT_D0+
WT_D0-
WT_D1+
WT_D1-
G ND NC NC NC NC G ND
C_P32K W GR _CL K+
W GR _CL K-
W GR _D0+
W GR _D0-
W GR _D1+
W GR _D1-
BRI _DT
BRI _RSP
RG I_DT
RG I_RSP
RF_RESET_B
CL KREQ0
REFCL K0
NC
NC
NC
+3.3V
+3.3V
G ND
CO EX_TXD
CO EX_RXD
CO EX3
SUSCLK
W_DI S A BLE 1#
G ND G ND
G ND
PEW AKW#
CL KREQ#
RERST#
G ND
REFCL K0-
REFCL K0+
G ND
PER0-
PER0+
G ND
PET0-
PET0+
G ND
C L INK _CL K
C L INK _DA T
C L INK _RST
U ART_W AKE#
U ART_RTS
U ART_RXD
U ART_TXD
U ART_CTS
PCM_S Y NC
PCM_O UT
PCM_IN
PCM_CL K
W_DI S A BLE 2#
G ND
LED2#
LED1#
G ND
U SB _D-
U SB _D+
G ND
3.3V
3.3V
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
Coex sig na ls
W i Fi P CI e
BT US B
I2S
UA RT
GP IO
C N V i o RX
W iFi LE D
R E FC LK 38.4M hz
C NV i o TX
C LIN K
BT RF_K ILL
W iFi R F_K ILL
32Kh z clo ck
RGI BRI
C LK R EQ
RF_RESET_B
BT LED
3.3V
3.3V
P o we r
P o we r
9.1.6 Signal connection pitfalls
The OEM should make sure to follow the M.2 definitions of signal names and directions (I/O TX/Rx
etc.) and avoid confusion between platform side and device side.
Note that some lines are bidirectional, such as PCIe CLKREQ, PEWAKE.
9.1.7 Pullups and pulldowns
The OEM should apply pullups and pulldowns in the platform side according to Table 9–2.
Table 9–2 Socket 1 pullups and pulldowns
I/F Signals PU/PD Guideline Rationale
BRI/RGI
BT UART
BRI_DT / RTS None Intel SoC with CNVi support have
internal PU/PD as needed.
RGI_RSP / CTS PU Intel SoC with CNVi support have
internal PU/PD as needed.