User's Manual
Table Of Contents
- 1 Introduction
- NOTE:
- NOTE:
- 2 Product Architecture
- 3 Electrical Specifications
- 4 Mechanical Specifications
- 5 Performance
- 1. BT in SW RF-KILL in all the tests
- 2. HB values refer to internal FE SKU
- 3. OS: Win10
- 1. Wi-Fi in SW RF-KILL in all the tests
- 2. OS: Win10
- 3. WsP is Master device
- 1. The TX power per MCS relate to IEEE, mask compliance and limited by regulatory TX power limits.
- 2. The values relate to internal FE SKU
- 3. The values are for typical device and typical conditions
- 1. Measured at ANT port
- 2. Typical means Nominal corner, AVG over non BE CHs. AVG over freq segment and chains
- 3. Max means over PVT
- NOTE: The throughput values relate to Intel® Skylake Platform and CPU, Single User.
- 6 Thermal Specifications
- 7 Regulatory
- 8 Dynamic Regulatory Solution
- 9 Platform Design Guidelines
- 9.1 Socket 1 key options for 2230 cards
- 9.1.1 Socket 1 Hybrid Key E scheme
- 9.1.2 Connectorized Hybrid Key E (2230) pin-out
- 9.1.3 Special considerations for the Hybrid Key E scheme
- 9.1.4 Soldered-down (1216) pin-out
- 9.1.5 Breakout example for JfP soldered-down module
- 9.1.6 Signal connection pitfalls
- 9.1.7 Pullups and pulldowns
- 9.1.8 IO connection scenarios and best practices
- 9.1.9 I/F specific guidelines
- 9.1.10 Connectivity module power control
- 9.1.11 Power supply de-coupling
- 9.1.12 Wi-Fi wireless disable and HW RF-KILL
- 9.1.13 M.2 Bluetooth HW RF-KILL
- 9.1.14 BIOS
- 9.1 Socket 1 key options for 2230 cards
Platform Design Guidelines
Intel
®
Wireless-AC 9560 (Jefferson Peak)
External Product Specification (EPS) April 2017
58 Intel Confidential Document Number: 567240–1.0
Wi-Fi/BT/LTE coexistence signals
In order to allow a Hybrid Key E scheme supporting both connectivity and a cellular modem, there is a
need to connect the modem coexistence bus in a configuration that will allow the modem to connect to
the connectivity coexistence control logic. In Intel connectivity modules, this logic may reside in the
M.2 module or in the SoC, depending on whether the CNVi or discrete solutions are used:
• For CNVi, the logic that is connected to the coexistence bus resides in Pulsar, which is part of
the SoC.
• For discrete M.2 cards, this logic resides in the module.
As a result, when a motherboard design contains a modem, and it is desired that it be able to support
CNVi and discrete on the same M.2 socket, there is a need to have a 3-way connection of the board,
as shown in Figure 9–7. In this diagram, the red lines represent lines that are unused in each
connection scenario. One can simplify the routing by adding a jumper resistor to select between the
two configurations; however, this will result in losing the option to swap between CNVi and Discrete on
the board. Any such swapping will then require a board hardware change for changing the jumper
resistor position.
Note that when doing this 3-way connection between SoC, M.2 and the modem, there will always be
an unused signal that is not optimally terminated for that connection. This signal is shown in red in the
connection diagram. The effect of this signal is similar to a stub that adds undesired impedance
change to the trace. The effect of this stub on the UART bus depends on several system parameters:
distance between the different UART pins, UART bus speed, and electrical characteristics of the UART
drivers and receivers (referenced to the signal pins). This effect must be considered and analyzed
through design practices or simulations to ensure that signal integrity is not compromised. For this
analysis, the UART baud rate shall be assumed to not be higher than 4Mbaud.
Figure 9–7 Coexistence UART for connectivity/modem 3-way configuration
SOC
Pulsar
Coex
UART
M.2- CN Vi
Cellular Modem
Coex
UART
SOC
Pulsar
Coex
UART
M.2- discret e
Cellular Modem
Coex
UART
Coex
UART
COEX3 COEX3
COEX3
9.1.10 Connectivity module power control
The connectivity module power supply pins shall be connected directly to the rail DSW.
To ensure proper operation of the integrated connectivity module, the use of a power switch to control
the M.2 module power shall be avoided. The Jefferson Peak module is not compatible with the
SLP_WLAN control signal. Note that the Jefferson Peak module was designed with low-leakage power,
and therefore does not require any external power control to be used during normal operation.