User's Manual

Atmel AVR2080
13
8479A-AVR-01/12
Each ground pin should be connected to the bottom plane with at least one via. Move
the vias as close to the IC as possible. It is always desired to integrate the single-pin
ground connections into polygon structures after a short distance. Top, bottom, and,
on multilayer boards, the inner ground planes, should be tied together with a grid of
vias. When ground loops are smaller than one tenth of the wavelength, it is safe to
consider this as a solid piece of metal.
The soldering technology used allows the placement of small vias (0.15mm drill)
within the ground paddle underneath the chip. During reflow soldering, the vias get
filled with solder, having a positive effect on the connection cross section. The small
drill size keeps solder losses within an acceptable limit. During the soldering process
vias should be open on the bottom side to allow enclosed air to expand.
5.4 PCB – digital GND routing
Digital ground pins (12, 16, 18, and 21) are not directly connected to the paddle.
Digital ground pins may carry digital noise from I/O pad cells or other digital
processing units within the chip.
In case of a direct paddle connection, impedances of the paddle ground vias could
cause a small voltage drop for this noise and may result in an increased noise level
transferred to the analog domain.
5.5 PCB – GND plane
Besides the function to provide supply ground to the individual parts, the ground
plane has to be considered as a counterpart for the antenna. Such an antenna base
plate is considered a continuous metal plane.
For that reason, any unused surface should be filled with a copper plane and
connected to the other ground side using sufficient through holes. Larger copper
areas should also be connected to the other side layer with a grid of vias. This way,
for an external electromagnetic field the board will behave like a coherent piece of
metal.
When a trace is cutting the plane on one side, the design should contain vias along
this trace to bridge the interrupted ground on the other side. Place vias especially
close to corners and necks to connect lose polygon ends.
5.6 Ceramic antenna design and tuning
The antenna section follows an already existing similar implementation as described
in Atmel AVR2043 REB231ED – Hardware User Manual [10] applicatio
n note. The
application note provides detailed information about a design study, design-in and
tuning.