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Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014

Features

 Integrated Temperature Sensor + Nonvolatile Registers + Serial EEPROM

 2-Wire I

C and SMBus

™

compatible serial interface

 Supports SMBus Timeout

 Supports SMBus Alert and Alert Response Address (ARA)

 Selectable addressing allows up to eight devices on the same bus

 Single 1.7V to 5.5V supply

 400kHz and 1MHz compatibility

 Industry standard green (Pb/Halide-free/RoHS compliant) package options

 8-lead SOIC (150-mil)

 8-lead MSOP (3.0 x 3.0mm)

 8-pad Ultra Thin DFN (UDFN — 2.0 x 3.0 x 0.6mm)

Digital Temperature Sensor Features

 Measures temperature from -55C to +125C

 Highly accurate temperature measurements requiring no external components

 ±0.5°C accuracy (typical) over the 0C to +85C range

 ±1.0°C accuracy (typical) over the -25C to +105C range

 ±2.0°C accuracy (typical) over the -40C to +125C range

 Pin and software compatible to industry-standard LM75-type devices

 User-configurable resolution

 9 to 12 bits (0.5C to 0.0625C)

 User-configurable high and low temperature limits

 Nonvolatile registers to retain user-configured or pre-defined power-up defaults

 Register locking to prevent erroneous misconfiguration

 Register lockdown for permanent, non-changeable device configuration

 One-Shot mode for single temperature measurement while in Shutdown mode

 ALERT output pin for indicating temperature alarms

 Low power dissipation

 75μA active current (typical) during temperature measurements

 Shutdown mode to minimize power consumption

 1μA active current (typical)

AT30TSE752A, AT30TSE754A, AT30TSE758A

9- to 12-bit Selectable, ±0.5°C Accurate

Digital Temperature Sensor with Nonvolatile Registers

and Serial EEPROM

DATASHEET

Summary of content (57 pages)

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AT30TSE752A, AT30TSE754A, AT30TSE758A 9- to 12-bit Selectable, ±0.5°C Accurate Digital Temperature Sensor with Nonvolatile Registers and Serial EEPROM DATASHEET Features  Integrated Temperature Sensor + Nonvolatile Registers + Serial EEPROM  2-Wire I2C and SMBus™ compatible serial interface Supports SMBus Timeout Supports SMBus Alert and Alert Response Address (ARA)  Selectable addressing allows up to eight devices on the same bus    Single 1.7V to 5.
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Serial EEPROM Features  Atmel® AT30TSE752A Integrates 2Kb of EEPROM  Atmel AT30TSE754A Integrates 4Kb of EEPROM  Atmel AT30TSE758A Integrates 8Kb of EEPROM  Reversible software Write protection for full array  Supports byte and Page Write operations  Self-timed write cycle (5ms maximum)  High-reliability   2 Endurance: 1,000,000 write cycles Data retention: 100 years AT30TSE752A/754A/758A [DATASHEET] Atmel-8854G-DTS-AT30TSE752A-754A-758A-Datasheet_102014
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T ab le of Cont ent s 1. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Pin Descriptions and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. Device Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 4.2 4.3 4.
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10. Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 10.2 10.3 10.4 10.5 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Byte Write . . . . . . . . . . . .
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1. Description The Atmel® AT30TSE752A/754A/758A are a complete, precise temperature monitoring device designed for use in a variety of applications that require the measuring of local temperatures as an integral part of the system's function and/or reliability. The AT30TSE752A/754A/758A devices combine a high-precision digital temperature sensor, programmable high and low temperature alarms, and a 2-wire I2C and SMBus (System Management Bus) compatible serial interface into a single, compact package.
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2. Pin Descriptions and Pinouts Table 1. Pin Description Symbol Name and Function SCL Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command and input data present on the SDA pin is always latched in on the rising edge of SCL, while output data on the SDA pin is always clocked out on the falling edge of SCL.
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Figure 1. Pin Configurations SDA 8-SOIC 8-MSOP 8-UDFN (Top View) (Top View) (Top View) 1 8 VCC SDA SCL SCL 3. 2 7 A0 ALERT 3 6 A1 GND 4 5 A2 ALERT GND 8 1 7 2 6 3 5 4 VCC SDA 1 8 VCC A0 SCL 2 7 A0 A1 ALERT 3 6 A1 A2 GND 4 5 A2 Block Diagram Figure 3-1.
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4. Device Communication The AT30TSE752A/754A/758A operates as a slave device and utilizes a simple 2-wire I2C and SMBus compatible digital serial interface to communicate with a host controller, commonly referred to as the bus Master. The Master initiates and controls all Read and Write operations to the slave devices on the serial bus, and both the Master and the slave devices can transmit and receive data on the bus.
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4.4 No-Acknowledge (NACK) When the AT30TSE752A/754A/758A are transmitting data to the Master, the Master can indicate that it is done receiving data and wants to end the operation by sending a NACK response to the AT30TSE752A/754A/758A instead of an ACK response. This is accomplished by the Master outputting a Logic 1 during the ACK/NACK clock cycle, at which point the AT30TSE752A/754A/758A will release the SDA line so that the Master can then generate a Stop condition.
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5. Device Operation Commands used to configure and control the operation of the AT30TSE752A/754A/758A are sent to the device from the Master via the serial interface. Likewise, the Master can read the temperature data from the AT30TSE752A/754A/758A via the serial interface; however, since multiple slave devices can reside on the serial bus, each slave device must have its own unique 7-bit address so that the Master can access each device independently.
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5.2 Temperature Alarm After the measured temperature value has been stored into the Temperature Register, the data will be compared with both the high and low temperature limits defined by the values stored in the THIGH Limit Register and TLOW Limit Register. If the comparison results in a valid fault condition (see Section 5.2.1, “Fault Tolerance Limits” on page 11), then the device will activate the ALERT output pin.
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5.2.2 Comparator Mode When the device operates in the Comparator mode, then the ALERT pin goes active if the measured temperature meets or exceeds the high temperature limit set by the THIGH Limit Register and a valid fault condition exists (the consecutive number of temperature faults has been reached). The ALERT pin will return to the inactive state after the measured temperature drops below the TLOW Limit Register value the appropriate number of times to create a subsequent valid fault condition.
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5.2.3 Interrupt Mode Similar to the Comparator mode, when the device operates in the Interrupt mode, the ALERT pin will go active if the measured temperature meets or exceeds the high temperature limit set by the THIGH Limit Register and a valid fault condition exists (the consecutive number of temperature faults has been reached).
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Figure 5-4. Interrupt Mode (Fault Tolerance Queue = 2) Delay Before Reading Register THIGH Limit Temperature TLOW Limit ALERT (Active High, POL = 1) Read Register Read Register ALERT (Active Low, POL = 0) Temperature Measurements/Conversions 5.3 Shutdown Mode To reduce current consumption and save power, the device features a Shutdown mode that disables all internal device circuitry except for the serial interface and POR circuits.
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6. Registers The AT30TSE752A/754A/758A contains eight registers (a Pointer Register and seven data registers) that are used to control the operational mode and performance of the temperature sensor, store the user-defined high and low temperature limits, and store the digitized temperature measurements. All accesses to the device are performed using these eight registers.
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For Write operations to the AT30TSE752A/754A/758A, the Pointer Register value must be refreshed each time a Write to the device is to be performed, even if the same data register is going to be written to a second time in a row. Example: If the Pointer Register is set to point to the Configuration Register, once the subsequent Write operation to the Configuration Register has completed, the user cannot write again into the Configuration Register without first setting the Pointer Register value again.
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6.2 Temperature Register The Temperature Register is a 16-bit Read-only Register that stores the digitized value of the most recent temperature measurement. The temperature data value is represented in the twos complement format, and, depending on the resolution selected, up to 12 bits of data will be available for output with the remaining LSBs being fixed in the Logic 0 state.
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After each temperature measurement and digital conversion is complete, the new temperature data is loaded into the Temperature Register if the register is not currently being read. If a Read is in progress, then the previous temperature data will be output. Accessing the Temperature Register continuously without waiting the maximum conversion time (tCONV) for the selected resolution may prevent the device from properly updating the Temperature Register with new temperature data.
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6.3 Configuration Register The Configuration Register is used to control key operational modes and settings of the device such as the One-Shot mode, the temperature conversion resolution, the fault tolerance queue, the ALERT pin polarity, the Alarm Thermostat mode, and the Shutdown mode.
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To set the value of the Configuration Register, the Master must first initiate a Start condition followed by the AT30TSE752A/754A/758A device address byte (1001AAA0 where “AAA” corresponds to the hard-wired A2-0 address pins). After the AT30TSE752A/754A/758A has received the proper address byte, the device will send an ACK to the Master. The Master must then send the appropriate Pointer Register byte of 01h to select the Configuration Register.
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6.3.3 FT1:FT0 Bits The FT1 and FT0 bits are used to set the fault tolerance queue value which defines how many consecutive faults must occur before the ALERT pin will be activated (see Section 5.2.1, “Fault Tolerance Limits” on page 11). The FT1 and FT0 bit settings provide four different fault values as detailed in Table 6-7.
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6.3.7 NVRBSY The Ready/Busy status of the Nonvolatile Configuration Register, Nonvolatile TLOW Limit Register, and Nonvolatile THIGH Limit Register can be determined by reading the NVRBSY bit. When the NVRBSY bit is in the Logic 0 state, then the Nonvolatile Configuration and Limit Registers are available to be read from or written to. When the NVRBSY bit is in the Logic 1 state, the Nonvolatile Registers are busy and cannot be accessed for reading, writing, or copying.
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6.4 Nonvolatile Configuration Register The Nonvolatile Configuration Register is a 16-bit wide Read/Write Register used to manage key power-up/reset device settings and operational modes including the locking of the AT30TSE752A/754A/758A's various registers. The Nonvolatile Configuration Register is used in conjunction with the Configuration Register to control how the device operates.
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To set the value of the Nonvolatile Configuration Register, the Master must first initiate a Start condition followed by the AT30TSE752A/754A/758A device address byte (1001AAA0 where “AAA” corresponds to the hard-wired A2-0 address pins). After the AT30TSE752A/754A/758A has received the proper address byte, the device will send an ACK to the Master. The Master must then send the appropriate Pointer Register byte of 11h to select the Nonvolatile Configuration Register.
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6.4.2 NVFT1:NVFT0 Bits The nonvolatile NVFT1 and NVFT0 bits are used to set the power-up/reset default Fault Tolerance Queue value which defines how many consecutive faults must occur before the ALERT pin will be activated (see Section 5.2.1, “Fault Tolerance Limits” on page 11). The NVFT1 and NVFT0 bit settings provide four different fault values as detailed in Table 6-10. Both the NVFT1 and NVFT0 bits are factory-set to default to the Logic 0 state. Table 6-10. Fault Tolerance Queue 6.4.
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6.4.7 RLCK The nonvolatile RLCK bit controls the reversible locking of both the Volatile and Nonvolatile Configuration and Limit Registers. When the RLCK bit is set to the Logic 0 state, the Configuration Register, TLOW Limit Register, THIGH Limit Register, Nonvolatile Configuration Register, Nonvolatile TLOW Limit Register, and Nonvolatile THIGH Limit Register will be unlocked and can be modified.
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6.5 TLOW and THIGH Limit Registers The 16-bit TLOW and THIGH Limit Registers store the user-programmable lower and upper temperature limits for the temperature alarm. Like the Temperature Register, the temperature data values of the TLOW and THIGH Limit Registers are stored in the twos complement format with the MSB (bit 15) of the registers containing the sign bit (zero indicates a positive number and a one indicates a negative number).
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ready for the lower byte of data. The AT30TSE752A/754A/758A will then clock out the lower byte of the register, after which the Master must send a NACK to end the operation. When the AT30TSE752A/754A/758A receives the NACK, it will release the SDA line so that the Master can send a Stop or repeated Start condition.
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6.6 Nonvolatile TLOW and THIGH Limit Registers The 16-bit Nonvolatile TLOW and THIGH Limit Registers store the power-up/reset default values for the volatile versions of the TLOW and THIGH Limit Registers. Like their volatile counterparts, the temperature data values of the Nonvolatile TLOW and THIGH Limit Registers are stored in the twos complement format with the MSB (bit 15) of the registers containing the sign bit (zero indicates a positive number and a one indicates a negative number).
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this time, the NVRBSY bit of the Configuration Register will indicate that the device is busy. If the Master issues a repeated Start condition instead of a Stop condition, the AT30TSE752A/754A/758A will abort the operation and the contents of the Nonvolatile TLOW or THIGH Limit Register will not be changed.
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Figure 6-11.
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7. Register Locking All Volatile and Nonvolatile Configuration and Limit Registers (the Configuration Register, TLOW Limit Register, THIGH Limit Register, Nonvolatile Configuration Register, Nonvolatile TLOW Limit Register, and Nonvolatile THIGH Limit Register) can be locked from data changes by utilizing the RLCK bit in the Nonvolatile Configuration Register.
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8. Operations Allowed During Nonvolatile Busy Status While the AT30TSE752A/754A/758A is busy performing nonvolatile operations such as programming the Nonvolatile Configuration Register or the Serial EEPROM, certain other operations can still be executed. Table 8-1 details which commands are allowed or not allowed during a Nonvolatile Busy operation. For those commands that are not allowed during a Nonvolatile Busy operation, the device will respond with a NACK where it would normally respond with an ACK.
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9. Other Commands The AT30TSE752A/754A/758A incorporates additional commands for other device functions. The command opcode consists of a single byte of data that is sent from the Master to the AT30TSE752A/754A/758A in place of the Pointer Register byte; therefore, the device must first be addressed by the Master and then given the subsequent command opcode. Sending any of the command opcodes to the AT30TSE752A/754A/758A will not change the contents of the Pointer Register byte. Table 9-1.
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Figure 9-2. Copy Nonvolatile Registers to Volatile Registers 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 0 0 SCL Address Byte SDA 1 0 0 1 A Command Byte A A 0 0 MSB Start by Master 9.
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10. Serial EEPROM The AT30TSE752A/754A/758A contains an integrated 2Kb, 4Kb, or 8Kb Serial EEPROM that is a drop in functional replacement for a stand alone 2-wire Serial EEPROM device enabling the added benefit of saving board space and component cost. The Serial EEPROM can be used to permanently store system configuration, application specific, and or user preference data. 10.1 Memory Organization The Serial EEPROM in the AT30TSE752A/754A/758A is internally organized into pages or rows of data bytes.
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10.3 Write Operations The Serial EEPROM within the AT30TSE752A/754A/758A supports single byte writes up to a full 16 bytes per page. The only difference between a Byte Write and a Page Write protocol sequence is the amount of data bytes loaded. Regardless of whether a Byte Write or Page Write operation is performed, it will take the same amount of time to write the data to the addressed memory location(s). The internal write cycle will complete in the minimum tWR specification. 10.3.
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Figure 10-2.
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Figure 10-3. Current Address Read from Serial EEPROM 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D2 D1 D0 1 SCL Device Address Byte SDA 1 0 1 0 A Data Byte (n) A/P1 A/P0 1 0 D7 MSB D6 D5 D4 D3 MSB Start by Master ACK from Slave NACK from Master Stop by Master 10.4.2 Random Read Random Read operations allow the Master to access any memory location in a random manner and requires a “dummy write” sequence to preload the byte address of the data byte to be read.
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10.4.3 Sequential Read Sequential Read operations are initiated in the same way as a Random Read, except that after the AT30TSE752A/754A/758A transmits the first data byte, the Master issues a ACK instead of a NACK and Stop condition in a Random Read operation. This directs the AT30TSE752A/754A/758A to increment the internal address pointer by one and transmit the next sequentially addressed data byte.
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The Write Protection status can be checked to see if the memory array is in full protection or not by sending a Start condition followed by 01100011 (63h), if the AT30TSE752A/754A/758A responds with a NACK, this indicates the memory array is in full write protect. Likewise, if the AT30TSE752A/754A/758A responds with an ACK, this indicates the memory array is not protected. Table 10-3.
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11. SMBus Features and I2C General Call 11.1 SMBus Alert The AT30TSE752A/754A/758A utilizes the ALERT pin to support the SMBus Alert function when the Alarm Thermostat mode is set to the Interrupt mode (the CMP/INT bit of the Configuration Register is set to one) and the ALERT pin polarity is set to active low (the POL bit of the Configuration Register is set to zero).
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11.2 SMBus Timeout The AT30TSE752A/754A/758A supports the SMBus Timeout feature in which the AT30TSE752A/754A/758A will reset its serial interface and release the SMBus (stop driving the bus and let SDA float high) if the SCL pin is held low for more than the minimum tTIMEOUT specification. The AT30TSE752A/754A/758A will be ready to accept a new Start condition before tTIMEOUT maximum has elapsed. Figure 11-2.
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12. Electrical Specifications 12.1 Absolute Maximum Ratings* Temperature under Bias . . . . . . . -40°C to +125°C Storage Temperature . . . . . . . . . -65°C to +150°C Supply voltage with respect to ground . . . . . . . . . . . -0.5V to +7.0V ALERT Pin . . . . . . . . . . . . . . . -0.5V to VCC + 0.3V All input voltages with respect to ground . . . . . . . -0.5V to VCC + 0.5V All other output voltages with respect to ground . . . . . . . -0.5V to VCC + 0.5V 12.
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12.3 DC Characteristics Symbol Parameter ICC1 Active Current, Bus Inactive Typ(1) Max 60 75 65 95 85 125 120 160 150 225 225 325 0.15 0.20 0.23 0.35 0.48 0.63 0.70 1.50 2.00 3.40 2.50 4.40 1.7V ≤ VCC ≤ 2.0V 0.40 2.50 2.7V ≤ VCC ≤ 3.6V 0.60 3.50 4.5V ≤ VCC ≤ 5.5V 1.20 5.50 1.7V ≤ VCC ≤ 2.0V 110 140 130 180 180 270 VCC Range Condition Min 1.7V ≤ VCC ≤ 2.0V 2.7V ≤ VCC ≤ 3.6V Active Temperature Conversions 4.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC ≤ 2.
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12.4 Temperature Sensor Accuracy and Conversion Characteristics Symbol TACC Sensor Accuracy TRES Conversion Resolution tCONV Conversion Time Notes: 1. 2. 12.5 Parameter Typ(1) Max TA = 0°C to +85°C ±0.5 ±1.0 TA = -25°C to +105°C ±1.0 ±2.0 TA = -40°C to +125°C ±2.0 ±3.0 TA = -55°C to +125°C(2) ±3.0 Condition Selectable 9 to 12 bits Min 0.5 (9 bits) 0.0625 (12 bits) 9-bit Resolution 25 37.
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Figure 12-1. SMBus/I2C Timing Diagram tSCKH tR tSCKL tF SCL tOH tSUDAT tSUSTO tSUSTA tBUF tV SDA IN IN OUT OUT IN Start Condition 12.6 Stop Condition IN Start Condition Repeated Start Condition Nonvolatile Register and Serial EEPROM Characteristics Typ(1) Max Units Nonvolatile Register Program Time 1.0 5.0 ms tWR Serial EEPROM Write Cycle Time 3.0 5.0 ms tCOPYW Volatile to Nonvolatile Register Copy Time 1.0 5.
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12.8 Pin Capacitance Symbol Parameter CI/O(1) (1) CIN Note: 12.9 1. Min Max Units Input/Output Capacitance (SDA and ALERT pins) VI/O = 0V 8 pF Input Capacitance (A2-0 and SCL pins) VIN= 0V 6 pF Not 100% tested (value guaranteed by design and characterization). Input Test Waveforms and Measurement Levels AC Input Levels 0.9VCC VCC 2 0.1VCC tR, tF < 5ns (10% to 90%) 12.
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13. Ordering Information 13.1 Atmel Ordering Code Detail AT 3 0 T S E 7 5 2 A - S S 8 M - B Atmel Designator Product Family 30TSE = Digital Temperature Sensor with Integrated EEPROM Device Type EEPROM Density 2 = 2-kilobit 4 = 4-kilobit 8 = 8-kilobit Shipping Carrier Option B = Bulk (tubes) Y = Bulk (trays) T = Tape and Reel Voltage Option M = 1.7V to 5.
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13.2 Green Package Options (Pb/Halide-free/RoHS Compliant) Atmel Ordering Code AT30TSE752A-SS8M-B AT30TSE752A-SS8M-T AT30TSE752A-XM8M-B AT30TSE752A-XM8M-T AT30TSE752A-MA8M-T AT30TSE754A-SS8M-B AT30TSE754A-SS8M-T AT30TSE754A-XM8M-B AT30TSE754A-XM8M-T AT30TSE754A-MA8M-T AT30TSE758A-SS8M-B AT30TSE758A-SS8M-T AT30TSE758A-XM8M-B AT30TSE758A-XM8M-T AT30TSE758A-MA8M-T Note: Package Lead (Pad) Finish Operating Voltage Max. Freq. (kHz) NiPdAu 1.7V to 5.
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14. Part Marking Detail AT30TSE752A, AT30TSE754A & AT30TSE758A: Package Marking Information 8-lead SOIC 8-lead UDFN 8-lead MSOP 2.0 x 3.
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15. Packaging Information 15.1 8S1 — 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. SYMBOL MIN A 1.35 NOM MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.
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8XM — 8-lead MSOP Pin 1 3 2 1 E 0.20 C B A 1 -B- E1 CL N TOP VIEW 3 N b A2 3 2X (N/2 TIPS) 2 1 0.05 S 15.2 SEE DETAIL "A" BOTTOM VIEW END VIEW e 0.25 BSC A 0.07 R. MIN 2 PLACES SEATING PLANE 0.10 C A1 -HD 1 4 C OC SEATING PLANE -C- DETAIL 'A' -A- COMMON DIMENSIONS (Unit of Measure = mm) SIDE VIEW SYMBOL NOTES: 1. DIMENSIONS "D" & "E1" DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, AND ARE MEASURED AT DATUM PLANE -H- , MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.
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15.3 8MA2 — 8-pad UDFN E 1 8 Pin 1 ID 2 7 3 6 4 5 D C TOP VIEW A2 SIDE VIEW A A1 E2 b (8x) 8 1 7 D2 6 3 5 4 e (6x) K L (8x) BOTTOM VIEW Notes: COMMON DIMENSIONS (Unit of Measure = mm) 2 Pin#1 ID 1. This drawing is for general information only. Refer to Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. The Pin #1 ID is a laser-marked feature on Top View. 3. Dimensions b applies to metallized terminal and is measured between 0.15 mm and 0.
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16. Errata 16.
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17. Revision History Doc. Rev. Date Comments 8854G 10/2014 8854F 05/2014 Update DC Characteristics for ICC4 values and 8MA2 package drawing. 8854E 04/2014 Update the DC Characteristics table, Power-Up Conditions Condition table, and TACC Sensor Accuracy parameter condition. 8854D 09/2013 8854C 07/2013 Increase the ICC1 4.5V  VCC  5.5V typical from 75 to 85 and maximum from 100 to 125. Update ths UDFN, 8MA2 package outline drawing. Update the Absolute Maximum Ratings.
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