Features • Number of keys: up to 16 keys, and one slider (constructed from 2 to 8 keys) • Number of I/O lines: 11 (3 dedicated - configurable for input or output, 8 shared output only), PWM control for LED driving • Technology: patented spread-spectrum charge-transfer (transverse mode) • Key outline sizes: 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and shapes possible • Key spacings: 8 mm or wider, center to center (panel thickness dependent) • Slider design: 2 to 8 keys pla
. Pinout and Pin Listing Description 2.1 Pinout Description I2CA1 SDA SCL RST Y0A 1 28 27 26 25 24 23 22 21 GPIO3 2 20 Y1B VDD 3 19 Y0B VSS 4 18 VSS X6 5 17 VDD X7 6 16 VDD CHANGE 7 QT2160 8 9 15 10 11 12 13 14 I2CA0 X5 X4 X3 X2 X1 X0 SMP VRef 2.2 Y1A GPIO1 GPIO2 Pin Listing Description Table 2-1.Pin Listing 2 Comments If Unused, Connect To...
AT42QT2160 Table 2-1.Pin Listing (continued) Comments If Unused, Connect To...
Figure 3-1. Field Flow Between X and Y Elements overlying panel X element 3.1 Y elem ent Keys and Slider The QT2160 is capable of a maximum of 16 keys. These can be located anywhere within an electrical grid of 8X and 2Y scan lines. A lesser number of enabled keys will cause any unused acquisition burst timeslots to be pared from the sampling sequence, to optimize acquire speed and lessen power consumption. Thus, if only 8 keys are actually enabled, only 8 timeslots are used for scanning.
AT42QT2160 4.2 Burst Paring Keys that are disabled by setting their burst length to zero have their bursts removed from the scan sequence to save scan time and thus power. The QT2160 operates on a fixed 16 ms cycle and will go to sleep after all acquisitions and processing is done till the next 16ms cycle starts. As a consequence, the fewer keys, the less power is consumed. 4.3 Cs Sample Capacitor Operation Cs capacitors (Cs0...
Unlike other QT circuits, the Cs capacitor values on QT2160 devices have no effect on conversion gain. However, they do affect conversion time. Unused Y lines should be left open. Figure 4-1. VCs – Nonlinear During Burst (Burst too long, or Cs too small, or X-Y transcapacitance too large) X Drive YnB Figure 4-2. VCs – Poor Gain, Nonlinear During Burst (Excess capacitance from Y line to Gnd) X Drive YnB Figure 4-3.
AT42QT2160 Figure 4-4. Drive Pulse Roll-off and Dwell Time X drive Lost charge due to inadequate settling before end of dwell time Dwell time Y gate Note: 4.5 The Dwell time is a minimum of ~250ns - see Section 4.7 Sample Resistors The sample resistors (Rs0...Rs1) are used to perform single-slope ADC conversion of the acquired charge on each Cs capacitor. These resistors directly control acquisition gain; larger values of Rs will proportionately increase signal gain.
Dwell time is the duration in which charge coupled from X to Y is captured (Figure 4-4 on page 7). Increasing Rx values will cause the leading edge of the X pulses to increasingly roll off, causing the loss of captured charge (and hence loss of signal strength) from the keys. The dwell time is a minimum of 250 ns.
AT42QT2160 For better surface moisture suppression, the outer perimeter of X should be as wide as possible, and there should be no ground planes near the keys. The variable “T" in this drawing represents the total thickness of all materials that the keys must penetrate. Figure 4-6. Recommended Key Structure Y0 X0 Y1 Note: 4.9 4.9.1 “T" should ideally be similar to the complete thickness the fields need to penetrate to the touch surface.
Key sizes should be in the 5-7mm range when used in the slider to get the best linearity. The slider should be made up of however many of these elements are required to fit their dimensions. The slider will be treated as an object in the Adjacent Key Suppression (AKS) groupings. The keys in the slider would normally be set to the same burst length and threshold, although adjustments can be made in these at the expense of linearity. 4.9.
AT42QT2160 LED terminals which are multiplexed or switched into a floating state and which are within or physically very near a key structure (even if on another nearby PCB) should be bypassed to either Vss or Vdd with at least a 10nF capacitor to suppress capacitive coupling effects which can induce false signal shifts. The bypass capacitor does not need to be next to the LED, in fact it can be quite distant. The bypass capacitor is noncritical and can be of any type.
Caution: A regulator IC shared with other logic devices can result in erratic operation and is not advised. A regulator can be shared among two or more QT devices on one board. Refer to page 15 for suggested regulator manufacturers. A single ceramic 0.1uF bypass capacitor, with short traces, should be placed very close to supply pins 3 and 4 of the IC. Failure to do so can result in device oscillation, high current consumption, erratic operation etc.
AT42QT2160 4.15 Spread Spectrum Acquisitions QT2160 uses spread-spectrum burst modulation. This has the effect of drastically reducing the possibility of EMI effects on the sensor keys, while simultaneously spreading RF emissions. This feature is hard-wired into the device and cannot be disabled or modified. Spread spectrum is configured as a frequency chirp over a wide range of frequencies for robust operation. 4.16 Detection Integrator See also Section 4.2 on page 5.
4.18 General Purpose Inputs/Outputs There are three dedicated GPIOs (GPIO1...3) and eight GPOs shared with X lines (X0...7). Shared GPOs are always outputs, whereas dedicated GPIOs can be set to be outputs or inputs. GPIOs set to input can be used for reading dome switches or logic signals. Outputs can be used to drive LEDs, or other devices.
AT42QT2160 4.19 Wiring Figure 4-8. Wiring Diagram Vunreg follow regulator manufacturers recommended values for input and output bypass capacitors. VDD VREG tightly wire a 100nF bypass capacitor between Vdd and Vss (pins 3 and 4).
Figure 4-9.
AT42QT2160 5. I2C-compatible Bus Operation 5.1 Interface Bus More detailed information about the I 2 C -compatible bus protocol is available from www.i2C-bus.org. Devices are connected onto the I2C-compatible bus as shown in Figure 5-1. Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all I2C-compatible devices must be open-drain type. This implements a wired-AND function which allows any and all devices to drive the bus, one at a time.
Figure 5-2. Data Transfer SDA SCL Data Stable Data Stable Data Change 5.3 START and STOP Conditions The host initiates and terminates a data transmission. The transmission is initiated when the host issues a START condition on the bus, and is terminated when the host issues a STOP condition. Between START and STOP conditions, the bus is considered busy. As shown below, START and STOP conditions are signaled by changing the level of the SDA line when the SCL line is high. Figure 5-3.
AT42QT2160 Figure 5-4. Address Packet Format Addr MSB Addr LSB R/W ACK 7 8 9 SDA SCL 1 2 START 5.5 Data Packet Format All data packets are 9 bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the host generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by the Receiver pulling the SDA line low during the ninth SCL cycle.
Figure 5-6 shows a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W and the STOP. Figure 5-5. Data Packet Format Data MSB Data LSB ACK Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 2 7 Data Byte SLA+R/W Figure 5-6.
AT42QT2160 6. Interfaces 6.1 I2C-compatible Protocol The I2C-compatible protocol is based around access to an address table and supports multibyte reads and writes. Note: Each write or read cycle must end with a stop condition. The QT2160 may not respond correctly if a cycle is terminated by a new start condition. 6.2 I2C-compatible Addresses Four preset I2C-compatible addresses are selectable through pin I2CA0 and I2CA1 (Table 6-1). I2C-compatible Addresses Table 6-1. 6.3 6.3.
If the host sends more than one data byte, they will be written to consecutive memory addresses. The device automatically increments the target memory address after writing each data byte. After writing the last data byte, the host should send the STOP condition. The host should not try to write beyond address 255 because the device will not increment the internal memory address beyond this. 6.3.2 Reading Data From the Device The sequence of events required to read data from the device is shown next.
AT42QT2160 7. Communications Protocol 7.1 Introduction The device is address mapped. All communications consist of writes to, and reads from, locations in an 8-bit address map. Table 7-1 shows the address map of QT2160. Table 7-1. Memory Map Address Use Access 0 Chip ID Read 1 Major/minor code version Read 2 General Status Read 3 Key Status 1 Read 4 Key Status 2 Read 5 Slider Touch Position Read 6 GPIO Read Read 7 Sub-revision - Reserved - 0x00 - 8...
Table 7-1. Memory Map (continued) Address Use Access 71 GPIO/GPO Drive 2 Read/Write 72 Reserved - 0x00 Read/Write 73 GPIO Direction 2 Read/Write 74 GPIO/GPO PWM 1 Read/Write 75 GPIO/GPO PWM 2 Read/Write 76 PWM Level Read/Write 77 GPIO Wake Read/Write 78 Common change Keys 1 Read/Write 79 Common change Keys 2 Read/Write 80...99 Reserved - 0x00 - 100...131 Key 0 - 15 Signals Read 132...
AT42QT2160 7.4 Address 2: General Status Table 7-4. General Status Address b7 b6 b5 b4 b3 b2 b1 b0 2 RESET CYCLE OVER RUN 0 0 0 0 CC SDET These bits indicate the general status of the device. A change in this byte will cause the CHANGE line to trigger. RESET: this bit is set after a reset. This bit is clear after this byte is read back by the host. CYCLE OVERRUN: this bit is set if the cycle time is more than 16ms. It will be cleared when the cycle time is less than 16ms.
7.6 Address 5: Slider Touch Position Table 7-6. Address Slider Touch Position b7 b6 b5 b4 5 b3 b2 b1 b0 Position Position: Last position of the touch on the slider A change in this byte will cause the CHANGE line to trigger. 7.7 Address 6: GPIO Read Table 7-7. GPIO Read Address b7 b6 b5 b4 b3 b2 b1 b0 6 0 0 0 GPIO3 GPIO2 GPIO1 0 0 GPIO1...3: If GPIO1...3 are set as inputs, returns the logic level on the respective pin.
AT42QT2160 7.10 Address 11: Reset Table 7-10. Reset Address b7 b6 b5 b4 11 b3 b2 b1 b0 RESET Any nonzero value will trigger the device to reset. After a reset, the device will revert to default settings. After receiving a reset command the QT2160 will start not acknowledging I 2 C -compatible communications and make CHANGE inactive within 16ms. The chip will reset after another ~16ms. 7.11 Address 12: LP Mode Table 7-11.
7.13 Address 15...16: Neg/Pos Drift Compensation Table 7-13. Neg/Pos Drift Compensation Address b7 b6 b5 b4 b3 15 0 NDRIFT 16 0 PDRIFT b2 b1 b0 Signals can drift because of changes in Cx and Cs over time and temperature. It is crucial that such drift be compensated, else false detections and sensitivity shifts can occur. Drift compensation (see Figure 7-1) is performed by making the reference level track the raw signal at a slow rate, but only while there is no detection in effect.
AT42QT2160 However, an obstruction over the sense pad, for which the sensor has already made full allowance, could suddenly be removed leaving the sensor with an artificially suppressed reference level and thus become insensitive to touch. In this latter case, the sensor should compensate for the object's removal by raising the reference level relatively quickly (PDRIFT). Drift compensation and the detection time-outs work together to provide for robust, adaptive sensing.
The Negative Recal Delay timer monitors such detections; if a detection event exceeds the timer's setting, the key will be automatically recalibrated. After a recalibration has taken place, the affected key will once again function normally even if it is still being contacted by the foreign object. This feature is set globally. NRD can be disabled by setting it to zero (infinite timeout) in which case the key will never autorecalibrate during a continuous detection (but the host could still command it).
AT42QT2160 7.17 Address 20: Slider Control Table 7-17. Slider Control Address b7 b6 20 b5 b4 b3 HYST b2 b1 b0 NUM_KEYS HSYT: Set the hysteresis value for the slider’s reported position. Hysteresis is the number of positions the user has to move back, before the new touch position is reported when the direction of scrolling is changed and during first scroll after touch down. At lower resolutions, where skipping of reported positions will be noticed, hysteresis can be set to 0 (1 position).
7.19 Address 22...37: Key Control Table 7-20. Key Control Address b7 b6 b5 b4 b3 b2 22...37 0 0 0 0 0 0 b1 b0 AKS GROUP AKS GROUP: these bits configure which AKS group a key is within (0 - AKS disabled, 1, 2 or 3). Keys in the same group cannot both be in detect at the same time, unless they both form part of the slider (see Section 4.9.2 on page 10). Default: 0 (AKS disabled) 7.20 Address 38...53: Negative Threshold Table 7-21. Address Negative Threshold b7 b6 b5 38...
AT42QT2160 The burst length is the number of times the charge-transfer (QT) process is performed on a given key. Each QT process is simply the pulsing of an X line once, with a corresponding Y line enabled to capture the resulting charge passed through the key’s capacitance Cx. Increasing burst length directly affects key sensitivity. This occurs because the accumulation of charge in the charge integrator is directly linked to the burst length.
Shared X line GPOs are always outputs. By default, the dedicated GPIOs are set as inputs. Make sure to drive (set to outputs) these GPIOs if not used, as floating pins may consume unnecessary current. Default: 0 (All inputs) 7.24 Address 74...75: GPIO/GPO PWM Table 7-25. GPIO/GPO PWM Address b7 b6 b5 b4 b3 b2 b1 b0 74 X7 X6 X5 X4 X3 X2 X1 X0 75 0 0 0 GPIO3 GPIO2 GPIO1 0 0 Setting the corresponding GPIO PWM bit to 1 will enable PWM on the respective pin.
AT42QT2160 7.26 Address 77: GPIO Wake Table 7-27. GPIO Wake Address b7 b6 b5 b4 b3 b2 b1 b0 77 0 0 0 GPIO3 GPIO2 GPIO1 0 0 If the corresponding bit is set to 1, dedicated GPIO pins set to inputs will still be read during SLEEP mode (no capacitive sensing carried out). When a change in the state of the inputs is detected, the CHANGE line will be triggered and the QT2160 will go back to SLEEP. Default: 0 (Wake disabled) 7.27 Address 78...79: Common Change Keys Table 7-28.
8. Setups Block Setups data is sent from the host to the QT2160 using the I2C-compatible interface. The setups block is memory mapped onto this interface. Thus each setup can be accessed by reading/writing the appropriate address. Setups can be accessed individually or as a block. Table 8-1. Address Bytes Parameter 12 1 LP Mode 13 1 15 Symbol Valid Range Bits Key Scope Default Value Description Page 0: SLEEP mode (no capacitive sensing) LP_MODE 0 - 255 8 16 1 Burst Repetition BREP 1.
AT42QT2160 Table 8-1. Address Setups Table (continued) Bytes 70 71 73 1 1 1 Parameter Symbol Valid Range Bits Key Scope Default Value X7 0...1 1 - 0 X6 0...1 1 - 0 X5 0...1 1 - 0 X4 0...1 1 - 0 X3 0...1 1 - 0 X2 0...1 1 - 0 X1 0...1 1 - 0 X0 0...1 1 - 0 - - 1 - 0 - - 1 - 0 - - 1 - 0 GPIO3 0...1 1 - 0 GPIO2 0...1 1 - 0 GPIO1 0...1 1 - 0 - - 1 - 0 - - 1 - 0 - - 1 - 0 - - 1 - 0 - - 1 - 0 GPIO3 0...
Table 8-1. Address 74 75 Setups Table (continued) Bytes 1 1 Parameter Symbol Valid Range Bits Key Scope Default Value X7 0...1 1 - 0 X6 0...1 1 - 0 X5 0...1 1 - 0 X4 0...1 1 - 0 X3 0...1 1 - 0 X2 0...1 1 - 0 X1 0...1 1 - 0 X0 0...1 1 - 0 - - 1 - 0 - - 1 - 0 - - 1 - 0 GPIO3 0...1 1 - 0 GPIO2 0...1 1 - 0 GPIO1 0...
AT42QT2160 9. Getting Started With the QT2160 9.1 Using the I2C-compatible Bus The QT2160 is an address-mapped part. All commands and data transfers consist of reads from, and writes to, memory locations. 9.2 Establishing Contact To establish that the device is present and running, write a zero to it (see Section 9.3). Now read a single byte (see Section 9.4). This byte should be the ID of the device (0x11). If this is the case the device is present and running. 9.
A change in burst length should be followed by a calibration command (set the calibration byte to a nonzero value) to ensure reliable operation. It is also possible to adjust the sensitivity using the negative threshold for that key. Note that thresholds below 6 counts may cause sensitivity to noise and thresholds above 12 counts will require longer burst lengths than strictly necessary. All unused keys should be switched off by setting their burst lengths to zero.
AT42QT2160 9.8 GPIOs By default, the dedicated GPIOs (GPIO1...GPIO3) are set as inputs. Make sure to drive (set to outputs) these GPIOs if not used, as floating pins may consume unnecessary current. By default, shared GPOs are push-pull outputs driven low when not measuring. Table 9-1 shows a summary of the GPIO options, and the precedence of each setting. 9.
Figure 9-1. Typical Initialization and Usage Reset/Power Up CHANGE pin active (low)? No Yes Send setup parameters to set up QT2160 Send Calibrate command Read all status bytes (Address 2...6) to restore CHANGE pin to inactive (high) CHANGE pin active (low)? No Yes Read required Status bytes and other status bytes that changed, to restore CHANGE pin to inactive (high).
AT42QT2160 10. Specifications 10.1 Absolute Maximum Specifications Vdd -0.5 to +6V Max continuous pin current, any control or drive pin ±10 mA Short circuit duration to ground, any pin infinite Short circuit duration to Vdd, any pin infinite Voltage forced onto any pin -0.6V to (Vdd + 0.6) Volts CAUTION: Stresses beyond those listed under “Absolute Maximum Specifications" may cause permanent damage to the device.
10.3 DC Specifications Vdd = 5.0V, Cs = 4.7nF, Rs = 1MΩ, Ta = recommended range, unless otherwise noted Parameter Min Typ Max Units Notes Iddr Average supply current, running (LP16ms) 476 955 1127 µA Vdd = 1.8V Vdd = 3.3V Vdd = 5.0V Idds Average supply current, sleeping (SLEEP) <1.5 <2 <3 µA Vdd = 1.8V Vdd = 3.3V Vdd = 5.0V V 1.8V
AT42QT2160 10.5 Power Consumption Table 10-1. Average Current Consumption Test condition: 16 keys enabled, BL = 16 (4 x 16 = 64 actual pulses), BREP = 1 Idd (µA) at Vdd = LP Mode 1.8V 3.3V 5V SLEEP <1.
10.6 Mechanical Dimensions Figure 10-1. Mechanical Dimensions D C 1 2 Pin 1 ID 3 E SIDE VIEW A1 TOP VIEW A y K D2 1 0.45 2 R 0.20 3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 C L e BOTTOM VIEW Note: The terminal #1 ID is a Laser-marked Feature. NOTE 0.20 REF D 3.95 4.00 4.05 D2 2.35 2.40 2.45 E 3.95 4.00 4.05 E2 2.35 2.40 2.45 e 0.45 L 0.35 0.40 0.45 y 0.00 – 0.
AT42QT2160 10.7 Marking Either part marking can be supplied. 28 Pin 1 ID 1 Chip Assembly Lotcode (for traceability) AT42 QT2160 -MMU LTCODE Part number; AT42QT2160-MMU 28 Pin 1 ID 1 Abbreviation of Part number; AT42QT 2160 LTCODE Chip Assembly Lotcode (for traceability) 2160 AT Program week code number 1-52 where: A = 1, B = 2...Z = 26 then using the underscore A = 27...Z = 52 10.8 10.
10.10 Revision History 48 Revision No.
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