Features • Programmable Audio Output for Interfacing with Common Audio DAC • • • • • • • • • • • • • • • • • • • – PCM Format Compatible – I2S Format Compatible 8-bit MCU C51 Core-based (FMAX = 20 MHz) 2304 Bytes of Internal RAM 64K Bytes of Code Memory – AT89C5132: Flash (100K Write/Erase Cycles) 4K Bytes of Boot Flash Memory (AT89C5132) – ISP: Download from USB or UART to any External Memory Cards USB Rev 1.
Block Diagram Figure 1.
AT89C5132 Figure 2. AT89C5132 80-pin TQFP Package 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TQFP80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 Figure 3. AT89C5132 84-pin PLCC (1) 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PLCC84 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.
AT89C5132 Signals All the AT89C5132 signals are detailed by functionality in Table 1 to Table 15. Table 1. Ports Signal Description Signal Name Type Description Alternate Function P0.7:0 I/O Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. P1.
Table 3. Timer 0 and Timer 1 Signal Description Signal Name Type Alternate Function Description Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0 I External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is set by a low level on INT0#. P3.
AT89C5132 Table 7. MutiMediaCard Interface Signal Description Signal Name Type MCLK O MMC Clock output Data or command clock transfer. - MCMD I/O MMC Command line Bidirectional command channel used for card initialization and data transfer commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to VDD or VSS. - MDAT I/O MMC Data line Bidirectional data channel. To avoid any parasitic current consumption, unused MDAT input must be polarized to VDD or VSS.
Table 11. A/D Converter Signal Description Signal Name Type Alternate Function AIN1:0 I A/D Converter Analog Inputs - AREFP I Analog Positive Voltage Reference Input - AREFN I Analog Negative Voltage Reference Input This pin is internally connected to AVSS. - Description Table 12. Keypad Interface Signal Description Signal Name Type KIN3:0 I Alternate Function Description Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. P1.
AT89C5132 Table 14. System Signal Description Signal Name Type Description RST I Reset Input Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD.
Internal Pin Structure Table 16. Detailed Internal Pin Structure Circuit(1) Type Pins Input TST Input/Output RST Input/Output P1(2) P2(3) P3 P4 P53:0 RTST VDD VDD P RRST Watchdog Output VSS 2 osc periods Latch Output VDD VDD VDD P1 P2 P3 N VSS VDD P Input/Output P0 MCMD MDAT ISP N PSEN VSS ALE SCLK DCLK VDD P Output N DOUT DSEL MCLK VSS D+ Input/Output D+ D- D- Notes: 12 1.
AT89C5132 Address Spaces Code Memory The AT8xC5132 derivatives implement four different address spaces: • Program/Code Memory • Boot Memory • Data Memory • Special Function Registers (SFRs) The AT89C5132 implements 64K Bytes of on-chip program/code memory in Flash technology. The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and programming.
AT89C5132 Clock Controller The AT89C5132 clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this controller. Oscillator The AT89C5132 X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 4) that can be configured with off-chip components such as a Pierce oscillator (see Figure 5).
Figure 6. Mode Switching Waveforms X1 X1 ÷ 2 X2 Bit Clock STD Mode Note: X2 Mode(1) STD Mode In order to prevent any incorrect operation while operating in X2 mode, the user must be aware that all peripherals using clock frequency as time reference (timers…) will have their time reference divided by two. For example, a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms.
AT89C5132 Figure 7. PLL Block Diagram and Symbol PFILT PLLCON.1 PLLEN N divider OSC CLOCK Up N6:0 PFLD CHP Vref VCO Down PLOCK PLL Clock R divider PLLCON.0 R9:0 PLL CLOCK OSCclk × ( R + 1 ) PLLclk = ----------------------------------------------N+1 PLL Clock Symbol Figure 8. PLL Filter Connection PFILT R C2 C1 VSS PLL Programming VSS The PLL is programmed using the flow shown in Figure 9.
Registers Table 1. CKCON Register CKCON (S:8Fh) – Clock Control Register 7 6 5 4 3 2 1 0 - WDX2 - - - T1X2 T0X2 X2 Bit Number 7 Bit Mnemonic Description - Reserved The values read from this bit is indeterminate. Do not set this bit. Watchdog Clock Control Bit Set to select the oscillator clock divided by two as watchdog clock input (X2 independent). Clear to select the peripheral clock as watchdog clock input (X2 dependent).
AT89C5132 Table 3. PLLCON Register PLLCON (S:E9h) – PLL Control Register 7 6 5 4 3 2 1 0 R1 R0 - - PLLRES - PLLEN PLOCK Bit Number Bit Mnemonic Description PLL Least Significant Bits R Divider 2 LSB of the 10-bit R divider. 7-6 R1:0 5-4 - 3 PLLRES 2 - 1 PLLEN PLL Enable Bit Set to enable the PLL. Clear to disable the PLL. 0 PLOCK PLL Lock Indicator Set by hardware when PLL is locked. Clear by hardware when PLL is unlocked.
Program/Code Memory The AT89C5132 implements 64K Bytes of on-chip program/code memory. Figure 10 shows the split of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. The high voltage needed for programming or erasing Flash cells is generated on-chip using the standard V DD voltage, made possible by the internal charge pump.
AT89C5132 User Space This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128 Bytes. It contains the user’s application code. This space can be read or written by both software and hardware modes. Boot Space This space is composed of a 4K Bytes Flash memory. It contains the bootloader for InSystem Programming and the routines for In-System Application Programming. This space can only be read or written by hardware mode using a parallel programming tool.
Boot Memory Execution As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented to allow boot memory to be mapped in the code space for execution at addresses from F000h to FFFFh. The boot memory is enabled by setting the ENBOOT bit in AUXR1 (see Table 6). The three ways to set this bit are detailed in the following sections. Software Boot Mapping The software way to set ENBOOT consists in writing to AUXR1 from the user’s software.
AT89C5132 Registers Table 6. AUXR1 Register AUXR1 (S:A2h) – Auxiliary Register 1 7 6 5 4 3 2 1 0 - - ENBOOT - GF3 0 - DPS Bit Number Bit Mnemonic Description 7-6 - Reserved The values read from these Bits are indeterminate. Do not set these Bits. Enable Boot Flash Set this bit to map the boot Flash in the code space between at addresses F000h to FFFFh. Clear this bit to disable boot Flash.
Hardware Bytes Table 7. HSB Byte – Hardware Security Byte 7 6 5 4 3 2 1 0 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description X2B(1) 7 (2) 6 BLJB 5-4 - 3 - 2-0 LB2:0 X2 Bit Program this bit to start in X2 mode. Unprogram (erase) this bit to start in standard mode. Boot Loader Jump Bit Program this bit to execute the boot loader at address F000h on next reset. Unprogram (erase) this bit to execute user’s application at address 0000h on next reset.
AT89C5132 Data Memory The AT89C5132 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: – The lower 128 Bytes RAM segment – The upper 128 Bytes RAM segment – The expanded 2048 Bytes RAM segment 2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode.
Figure 14. Lower 128 Bytes Internal RAM Organization 7Fh 30h 2Fh 20h 18h 10h 08h 00h Bit-Addressable Space (Bit Addresses 0 - 7Fh) 1Fh 17h 0Fh 4 Banks of 8 Registers R0 - R7 07h Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. Expanded RAM The on-chip 2K Bytes of expanded RAM (ERAM) are accessible from address 0000h to 07FFh using indirect addressing mode through MOVX instructions.
AT89C5132 External Space Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD, WR, and ALE). Figure 15 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 12 describes the external memory interface signals. Figure 15.
External Bus Cycles This section describes the bus cycles that AT89C5132 executes to read (see Figure 16), and write data (see Figure 17) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode, refer to the section “X2 Feature”, page 11. Slow peripherals can be accessed by stretching the read and write cycles.
AT89C5132 Dual Data Pointer Description The AT89C5132 implement a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Table 15) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 18). Figure 18.
Registers Table 13. PSW Register PSW (S:8Eh) – Program Status Word Register 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7 CY Carry Flag Carry out from bit 1 of ALU operands. 6 AC Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5 F0 User Definable Flag 0. 4-3 RS1:0 Register Bank Select Bits Refer to Table 10 for Bits description. 2 OV Overflow Flag Overflow set by arithmetic operations.
AT89C5132 Table 14. AUXR Register AUXR (S:8Eh) – Auxiliary Control Register 7 6 5 4 3 2 1 0 - EXT16 M0 DPHDIS XRS1 XRS0 EXTRAM AO Bit Number Bit Mnemonic Description Reserved The values read from this bit is indeterminate. Do not set this bit. 7 - 6 EXT16 5 M0 External Memory Access Stretch Bit Set to stretch RD or WR signals duration to 15 CPU clock periods. Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.
Special Function Registers The Special Function Registers (SFRs) of the AT89C5132 derivatives fall into the categories detailed in Table 15 to Table 30. The relative addresses of these SFRs are provided together with their reset values in Table 31. In this table, the bit-addressable registers are identified by Note 1. Table 15.
AT89C5132 Table 19. Port SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 P0 80h 8-bit Port 0 – – – – – – – – P1 90h 8-bit Port 1 – – – – – – – – P2 A0h 8-bit Port 2 – – – – – – – – P3 B0h 8-bit Port 3 – – – – – – – – P4 C0h 8-bit Port 4 – – – – – – – – P5 D8h 4-bit Port 5 – – – – – – – – 7 6 5 4 3 2 1 0 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY 7 6 5 4 3 2 1 0 Table 20.
Table 23.
AT89C5132 Table 26. Serial I/O Port SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI SCON 98h Serial Control SBUF 99h Serial Data Buffer – – – – – – – – SADEN B9h Slave Address Mask – – – – – – – – SADDR A9h Slave Address – – – – – – – – BDRCON 92h Baud Rate Control – – – BRR TBCK RBCK SPD SRC BRL 91h Baud Rate Reload – – – – – – – – 7 6 5 4 3 2 1 0 Table 27.
Table 31.
AT89C5132 Interrupt System The AT89C5132, like other control-oriented computer architectures, employ a program interrupt method. This operation branches to a subroutine and performs some service in response to the interrupt. When the subroutine terminates, execution resumes at the point where the interrupt occurred. Interrupts may occur as a result of internal AT89C5132 activity (e.g., timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g., keyboard).
Table 33. Priority Levels IPHxx IPLxx Priority Level 0 0 0 Lowest 0 1 1 1 0 2 1 1 3 Highest A low-priority interrupt is always interrupted by a higher priority interrupt but not by another interrupt of lower or equal priority. Higher priority interrupts are serviced before lower priority interrupts. The response to simultaneous occurrence of equal priority interrupts is determined by an internal hardware polling sequence detailed in Table 34.
AT89C5132 Figure 19. Interrupt Control System INT0# 00 01 10 11 External Interrupt 0 Highest Priority Interrupts EX0 00 01 10 11 IEN0.0 Timer 0 ET0 INT1# External Interrupt 1 00 01 10 11 IEN0.1 EX1 00 01 10 11 IEN0.2 Timer 1 ET1 TXD RXD Serial Port 00 01 10 11 IEN0.3 ES IEN0.4 00 01 10 11 Audio Interface EAUD MCLK MDAT MCMD MMC Controller 00 01 10 11 IEN0.6 EMMC SCL SDA Two-wire Controller 00 01 10 11 IEN1.0 EI2C SCK SI SO SPI Controller 00 01 10 11 IEN1.
External Interrupts INT1:0 Inputs External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to be level-triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in TCON register as shown in Figure 20. If ITn = 0, INTn is triggered by a low level at the pin. If ITn = 1, INTn is negative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXn, n = 0 or 1) in IEN0. Events on INTn set the interrupt request flag IEn in TCON register.
AT89C5132 Registers Table 35. IEN0 Register IEN0 (S:A8h) – Interrupt Enable Register 0 7 6 5 4 3 2 1 0 EA EAUD – ES ET1 EX1 ET0 EX0 Bit Number 7 Bit Mnemonic Description EA Enable All Interrupt Bit Set to enable all interrupts. Clear to disable all interrupts. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. Audio Interface Interrupt Enable Bit Set to enable audio interface interrupt.
Table 36. IEN1 Register IEN1 (S:B1h) – Interrupt Enable Register 1 7 6 5 4 3 2 1 0 - EUSB – EKB EADC ESPI EI2C EMMC Bit Number Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. 7 - 6 EUSB 5 - 4 EKB 3 EADC A to D Converter Interrupt Enable Bit Set to enable ADC interrupt. Clear to disable ADC interrupt. 2 ESPI SPI Controller Interrupt Enable Bit Set to enable SPI interrupt. Clear to disable SPI interrupt.
AT89C5132 Table 37. IPH0 Register IPH0 (S:B7h) – Interrupt Priority High Register 0 7 6 5 4 3 2 1 0 - IPHAUD – IPHS IPHT1 IPHX1 IPHT0 IPHX0 Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 IPHAUD Audio Interface Interrupt Priority Level MSB Refer to Table 33 for priority level description. 5 IPHMP3 MP3 Decoder Interrupt Priority Level MSB Refer to Table 33 for priority level description.
Table 38. IPH1 Register IPH1 (S:B3h) – Interrupt Priority High Register 1 7 6 5 4 3 2 1 0 - IPHUSB – IPHKB IPHADC IPHSPI IPHI2C IPHMMC Bit Number Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. 7 - 6 IPHUSB 5 - 4 IPHKB 3 IPHADC A to D Converter Interrupt Priority Level MSB Refer to Table 33 for priority level description. 2 IPHSPI SPI Interrupt Priority Level MSB Refer to Table 33 for priority level description.
AT89C5132 Table 39. IPL0 Register IPL0 (S:B8h) – Interrupt Priority Low Register 0 7 6 5 4 3 2 1 0 - IPLAUD – IPLS IPLT1 IPLX1 IPLT0 IPLX0 Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 IPLAUD Audio Interface Interrupt Priority Level LSB Refer to Table 33 for priority level description. 5 IPLMP3 MP3 Decoder Interrupt Priority Level LSB Refer to Table 33 for priority level description.
Table 40. IPL1 Register IPL1 (S:B2h) – Interrupt Priority Low Register 1 7 6 5 4 3 2 1 0 - IPLUSB - IPLKB IPLADC IPLSPI IPLI2C IPLMMC Bit Number Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. 7 - 6 IPLUSB 5 - 4 IPLKB 3 IPLADC A to D Converter Interrupt Priority Level LSB Refer to Table 33 for priority level description. 2 IPLSPI SPI Interrupt Priority Level LSB Refer to Table 33 for priority level description.
AT89C5132 Power Management 2 power reduction modes are implemented in the AT89C5132: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “X2 Feature”, page 12. Reset In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an high level has to be applied on the RST pin.
Table 17. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1) VDD Rise Time Oscillator Start-Up Time 1 ms 10 ms 100 ms 5 ms 820 nF 1.2 µF 12 µF 20 ms 2.7 µF 3.9 µF 12 µF Note: 1. These values assume VDD starts from 0V to the nominal value. If the time between 2 on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged, leading to a bad reset sequence.
AT89C5132 Entering Idle Mode To enter Idle mode, the user must set the IDL bit in PCON register (see Table 18). The AT89C5132 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. Note: Exiting Idle Mode If IDL bit and PD bit are set simultaneously, the AT89C5132 enter Power-down mode. Then it does not go in Idle mode when exiting Power-down mode. There are 2 ways to exit Idle mode: 1. Generate an enabled interrupt.
resumes when the input is released (see Figure 24) while using KINx input, execution resumes after counting 1024 clock ensuring the oscillator is restarted properly (see Figure 25). This behavior is necessary for decoding the key while it is still pressed. In both cases, execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-down mode. Note: 1.
AT89C5132 Registers Table 18. PCON Register PCON (S:87h) – Power Configuration Register 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - - GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial Port Mode Bit 1 Set to select double baud rate in mode 1,2 or 3. 6 SMOD0 Serial Port Mode Bit 0 Set to select FE bit in SCON register. Clear to select SM0 bit in SCON register.
Timers/Counters The AT89C5132 implement two general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin.
AT89C5132 Figure 26. Timer 0 and Timer 1 Clock Controller and Symbols PER CLOCK 0 Timer 0 Clock PER CLOCK 0 Timer 1 Clock 1 OSC CLOCK 1 OSC CLOCK ÷2 T0X2 T1X2 CKCON.1 CKCON.2 TIM0 CLOCK TIM1 CLOCK Timer 0 Clock Symbol Timer 0 ÷2 Timer 1 Clock Symbol Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 27 through Figure 33 show the logical configuration of each mode.
Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 29). The selected input increments TL0 register. Figure 30 gives the overflow period calculation formula when in timer mode. Figure 29. Timer/Counter x (x = 0 or 1) in Mode 1 TIMx CLOCK ÷6 0 THx (8 Bits) 1 TLx (8 Bits) Overflow TFx TCON Reg Tx Timer x Interrupt Request C/Tx# TMOD Reg INTx GATEx TRx TMOD Reg TCON Reg Figure 30.
AT89C5132 3. Figure 32 gives the autoreload period calculation formulas for both TF0 and TF1 flags. Figure 33. Timer/Counter 0 in Mode 3: Two 8-bit Counters TIM0 CLOCK ÷6 0 1 TL0 (8 Bits) Overflow TH0 (8 Bits) Overflow TF0 TCON.5 T0 Timer 0 Interrupt Request C/T0# TMOD.2 INT0 GATE0 TR0 TMOD.3 TIM0 CLOCK TCON.4 ÷6 TF1 TCON.7 Timer 1 Interrupt Request TR1 TCON.6 Figure 34.
Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo-32 prescaler implemented with the lower 5 Bits of the TL1 register (see Figure 27). The upper 3 Bits of TL1 register are ignored. Prescaler overflow increments TH1 register. Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 29). The selected input increments TL1 register.
AT89C5132 Registers Table 41. TCON Register TCON (S:88h) – Timer/Counter Control Register 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7 TF1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6 TR1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1.
Table 42. TMOD Register TMOD (89:h) - Timer/Counter 0 and 1 Modes 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Bit Number Mnemonic Description 7 GATE1 Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set. 6 C/T1# Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock.
AT89C5132 Table 44. TL0 Register TL0 (S:8Ah) – Timer 0 Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7:0 Low Byte of Timer 0 Reset Value = 0000 0000b Table 45. TH1 Register TH1 (S:8Dh) – Timer 1 High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7:0 High Byte of Timer 1 Reset Value = 0000 0000b Table 46.
Watchdog Timer The AT89C5132 implement a hardware Watchdog Timer (WDT) that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. Description The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in Figure 36, the 14-bit prescaler is fed by the WDT clock detailed in section "Watchdog Clock Controller", page 56.
AT89C5132 Watchdog Operation After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into the WDTRST register. As soon as it is enabled, there is no way except the chip reset to disable it. If it is not cleared using the previous sequence, the WDT overflows and forces a chip reset. This overflow generates a high level 96 oscillator periods pulse on the RST pin to globally reset the application.
Registers Table 48. WDTRST Register WDTRST (S:A6h Write only) – Watchdog Timer Reset Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7-0 Bit Mnemonic Description - Watchdog Control Value. Reset Value = XXXX XXXXb Table 49. WDTPRG Register WDTPRG (S:A7h) – Watchdog Timer Program Register 7 6 5 4 3 2 1 0 - - - - - WTO2 WTO1 WTO0 Bit Number Bit Mnemonic Description 7-3 - 2-0 WTO2:0 Reserved The values read from these Bits are indeterminate. Do not set these Bits.
AT89C5132 Audio Output Interface The AT89C5132 implement an audio output interface allowing the audio bitstream to be output in various formats. It is compatible with right and left justification PCM and I2S formats and thanks to the on-chip PLL (see Section “Clock Controller”, page 11) allows connection of almost all of the commercial audio DAC families available on the market.
Clock Generator The audio interface clock is generated by division of the PLL clock. The division factor is given by AUCD4:0 Bits in AUDCLK register. Figure 40 shows the audio interface clock generator and its calculation formula. The audio interface clock frequency depends on the audio DAC used. Figure 40.
AT89C5132 Figure 42. Audio Output Format DSEL DCLK DOUT Left Channel 1 2 3 Right Channel 13 14 15 LSB MSB B14 16 B1 1 2 3 13 14 15 LSB MSB B14 16 B1 I2S Format with DSIZ = 0 and JUST4:0 = 00001. DSEL DCLK Left Channel 1 DOUT 2 Right Channel 3 17 MSB B14 LSB 18 32 1 2 3 17 MSB B14 LSB 18 32 I2S Format with DSIZ = 1 and JUST4:0 = 00001.
Table 50. Sample Duplication Factor Interrupt Request DUP1 DUP0 Factor 0 0 No sample duplication, DAC rate = 8 kHz (C51 rate). 0 1 One sample duplication, DAC rate = 16 kHz (2 x C51 rate). 1 0 Two samples duplication, DAC rate = 32 kHz (4 x C51 rate). 1 1 Three samples duplication, DAC rate = 48 kHz (6 x C51 rate).
AT89C5132 Figure 44. Voice or Sound Mode Audio Flows Voice/Song Mode Configuration Program Audio Clock Configure Interface HLR = X DSIZ = X POL = X JUST4:0 = XXXXXb DUP1:0 = XX Enable DAC System Clock AUDEN = 1 Note: Audio Interrupt Service Routine Wait for DAC Enable Time Sample Request? SREQ = 1? Select Audio SRC = 1 Load 4 Samples in the Audio Buffer Under-run Condition1 Load 8 Samples in the Audio Buffer Enable Interrupt Set MSREQ & MUDRN1 EAUD = 1 1.
Registers Table 51. AUDCON0 Register AUDCON0 (S:9Ah) – Audio Interface Control Register 0 7 6 5 4 3 2 1 0 JUST4 JUST3 JUST2 JUST1 JUST0 POL DSIZ HLR Bit Number Bit Mnemonic Description Audio Stream Justification Bits Refer to Section "Data Converter", page 60 for Bits description. 7-3 JUST4:0 2 POL DSEL Signal Output Polarity Set to output the left channel on high level of DSEL output (PCM mode). Clear to output the left channel on the low level of DSEL output (I2S mode).
AT89C5132 Table 53. AUDSTA Register AUDSTA (S:9Ch Read Only) – Audio Interface Status Register 7 6 5 4 3 2 1 0 SREQ UDRN AUBUSY - - - - - Bit Number Bit Mnemonic Description SREQ Audio Sample Request Flag Set in C51 audio source mode when the audio interface request samples (buffer half empty). This bit generates an interrupt if not masked and if enabled in IEN0. Cleared by hardware when samples are loaded in AUDDAT.
Universal Serial Bus The AT89C5132 implement a USB device controller supporting Full-speed data transfer. In addition to the default control endpoint 0, it provides 3 other endpoints, which can be configured in Control, Bulk, Interrupt or Isochronous types. This allows to develop firmware conforming to most USB device classes, for example the AT89C5132 support: USB Mass Storage Class CBI Transport • USB Mass Storage Class Control/Bulk/Interrupt (CBI) Transport, Revision 1.
AT89C5132 Description The USB device controller provides the hardware that the AT89C5132 need to interface a USB link to data flow stored in a double port memory. It requires a 48 MHz reference clock provided by the clock controller as detailed in Section "Clock Controller", page 67. This clock is used to generate a 12 MHz full speed bit clock from the received USB differential data flow and to transmit data according to full speed USB device tolerance.
Figure 47.
AT89C5132 Serial Interface Engine (SIE) The SIE performs the following functions: • NRZI data encoding and decoding • Bit stuffing and unstuffing • CRC generation and checking • ACKs and NACKs automatic generation • TOKEN type identifying • Address checking • Clock recovery (using DPLL) Figure 48.
Figure 49. UFI Block Diagram Transfer Control FSM 12 MHz DPLL Asynchronous Information USBCON USBADDR USBINT USBIEN UEPNUM UEPCONX UEPSTAX UEPRST UEPINT UEPIEN UEPDATX UBYCTX UFNUMH UFNUML To/From C51 Core Endpoint 3 Endpoint 2 Endpoint Control USB side To/From SIE Endpoint Control C51 side Endpoint 1 Endpoint 0 Figure 50.
AT89C5132 Endpoint Interrupt Sources Each endpoint supports four interrupt sources reported in UEPSTAX and combined together to appear as a single endpoint interrupt source in UEPINT. Each endpoint interrupt can be enabled separately in UEPIEN. • TXCMP: Transmitted In Data Interrupt Flag. This flag triggers an interrupt after an IN packet has been transmitted for Isochronous endpoints or after it has been accepted (ACK’ed) by the host for Control, Bulk and Interrupt endpoints.
Registers Table 56. USBCON Register USBCON (S:BCh) – USB Global Control Register 7 6 5 4 3 2 1 0 USBE SUSPCLK SDRMWUP - UPRSM RMWUPE CONFG FADDEN Bit Number Bit Mnemonic Description 7 USBE 6 SUSPCLK 5 Suspend USB Clock Bit Set to disable the 48 MHz clock input (Resume Detection is still active). Clear to enable the 48 MHz clock input. Send Remote Wake-up Bit Set to force an external interrupt on the USB controller for Remote Wake UP purpose.
AT89C5132 Table 57. USBADDR Register USBADDR (S:C6h) – USB Address Register 7 6 5 4 3 2 1 0 FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 Bit Number Bit Mnemonic Description 7 6-0 Function Enable Bit Set to enable the function. The device firmware shall set this bit after it has received a USB reset and participate in the following configuration process with the default address (FEN is reset to 0). Cleared by hardware at power-up, should not be cleared by the device firmware once set.
Table 59. USBIEN Register USBIEN (S:BEh) – USB Global Interrupt Enable Register 7 6 5 4 3 2 1 0 - - EWUPCPU EEORINT ESOFINT - - ESPINT Bit Number Bit Mnemonic Description 7-6 - 5 Reserved The values read from these Bits are always 0. Do not set these Bits. Wake up CPU Interrupt Enable Bit EWUPCPU Set to enable the Wake Up CPU interrupt. Clear to disable the Wake Up CPU interrupt. 4 EEOFINT End Of Reset Interrupt Enable Bit Set to enable the End Of Reset interrupt.
AT89C5132 Table 61. UEPCONX Register UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM) 7 6 5 4 3 2 1 0 EPEN - - - DTGL EPDIR EPTYPE1 EPTYPE0 Bit Number Bit Mnemonic Description 7 EPEN 6-4 - Endpoint Enable Bit Set to enable the endpoint according to the device configuration. Endpoint 0 shall always be enabled after a hardware or USB bus reset and participate in the device configuration. Clear to disable the endpoint according to the device configuration.
Table 62. UEPSTAX Register UEPSTAX (Soh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM) 7 6 5 4 3 2 1 0 DIR - STALLRQ TXRDY STLCRC RXSETUP RXOUT TXCMP Bit Number Bit Mnemonic Description Control Endpoint Direction Bit This bit is relevant only if the endpoint is configured in Control type. Set for the data stage. Clear otherwise. 7 DIR 6 - 5 STALLRQ Stall Handshake Request Bit Set to send a STALL answer to the host for the next handshake.Clear otherwise.
AT89C5132 Table 63. UEPRST Register UEPRST (S:D5h) – USB Endpoint FIFO Reset Register 7 6 5 4 3 2 1 0 - - - - EP3RST EP2RST EP1RST EP0RST Bit Number Bit Mnemonic Description Reserved The values read from these Bits are always 0. Do not set these Bits. 7-4 - 3 EP3RST Endpoint 3 FIFO Reset Set and clear to reset the endpoint 3 FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received.
Table 65. UEPIEN Register UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register 7 6 5 4 3 2 1 0 - - - - EP3INTE EP2INTE EP1INTE EP0INTE Bit Number Bit Mnemonic Description Reserved The values read from these Bits are always 0. Do not set these Bits. 7-4 - 3 EP3INTE Endpoint 3 Interrupt Enable Bit Set to enable the interrupts for endpoint 3. Clear to disable the interrupts for endpoint 3. 2 EP2INTE Endpoint 2 Interrupt Enable Bit Set to enable the interrupts for endpoint 2.
AT89C5132 Table 67. UBYCTLX Register UBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM) 7 6 5 4 3 2 1 0 - BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0 Bit Number Bit Mnemonic Description 7 - 6-0 BYCT7:0 Reserved The values read from this Bits are always 0. Do not set this bit. Byte Count Byte count of a received data packet. This byte count is equal to the number of data Bytes received after the Data PID. Reset Value = 0000 0000b Table 68.
Table 69. UFNUMH Register UFNUMH (S:BBh, Read-only) – USB Frame Number High Register 7 6 5 4 3 2 1 0 - - CRCOK CRCERR - FNUM10 FNUM9 FNUM8 Bit Number Bit Mnemonic 7-3 - 5 Description Reserved The values read from these Bits are always 0. Do not set these Bits. CRCOK Frame Number CRC OK Bit Set by hardware after a non corrupted Frame Number in Start of Frame Packet is received. Updated after every Start Of Frame packet reception.
MultiMedia Card Controller The AT89C5132 implements a MultiMedia Card (MMC) controller. The MMC is used to store files in removable Flash memory cards that can be easily plugged or removed from the application. Card Concept The basic MultiMedia Card concept is based on transferring data via a minimal number of signals. Card Signals The communication signals are: Card Registers • CLK: with each cycle of this signal an one bit transfer on the command and data lines is done.
AT89C5132 Bus Lines The MultiMedia Card bus architecture requires all cards to be connected to the same set of lines. No card has an individual connection to the host or other devices, which reduces the connection costs of the MultiMedia Card system. The bus lines can be divided into three groups: Bus Protocol • Power supply: VSS1 and VSS2, VDD – used to supply the cards. • Data transfer: MCMD, MDAT – used for bidirectional communication.
Figure 52. (Multiple) Block Read Operation Stop Command MCMD Command Response MDAT Command Response Data Block CRC Data Block CRC Data Block CRC Block Read Operation Data Stop Operation Multiple Block Read Operation As shown in Figure 53 and Figure 54 the data write operation uses a simple busy signalling of the write operation duration on the data line (MDAT). Figure 53.
AT89C5132 Table 71. Command Token Format Bit Position 47 46 45:40 39:8 7:1 0 Width (Bits) 1 1 6 32 7 1 Value ‘0’ ‘1’ - - - ‘1’ Start bit Transmission bit Command Index Argument CRC7 End bit Description Response Token Format There are five types of response tokens (R1 to R5). As shown in Figure 57, responses have a code length of 48 Bits or 136 Bits. A response token is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit: a high level on MCMD line.
Table 74. R3 Response Format (OCR Register) Bit Position 47 46 [45:40] [39:8] [7:1] 0 Width (Bits) 1 1 6 32 7 1 Value ‘0’ ‘0’ ‘111111’ - ‘1111111’ ‘1’ Start bit Transmission bit Reserved OCR register Reserved End bit Description Table 75. R4 Response Format (Fast I/O) Bit Position 47 46 [45:40] [39:8] [7:1] 0 Width (Bits) 1 1 6 32 7 1 Value ‘0’ ‘0’ ‘100111’ - - ‘1’ Start bit Transmission bit Command Index Argument CRC7 End bit Description Table 76.
AT89C5132 Clock Control The MMC bus clock signal can be used by the host to turn the cards into energy saving mode or to control the data flow (to avoid under-run or over-run conditions) on the bus. The host is allowed to lower the clock frequency or shut it down.
Clock Generator The MMC clock is generated by division of the oscillator clock (FOSC) issued from the Clock Controller block as detailed in Section "Oscillator", page 11. The division factor is given by MMCD7:0 Bits in MMCLK register. Figure 60 shows the MMC clock generator and its output clock calculation formula. Figure 60. MMC Clock Generator and Symbol OSC CLOCK Controller Clock OSCclk MMCclk = ----------------------------MMCD + 1 MMCLK MMCEN MMCON2.
AT89C5132 Command Line Controller As shown in Figure 62, the command line controller is divided in two channels: the command transmitter channel that handles the command transmission to the card through the MCMD line and the command receiver channel that handles the response reception from the card through the MCMD line. These channels are detailed in the following sections. Figure 62. Command Line Controller Block Diagram TX Pointer CTPTR MMCON0.
The user may abort command loading by setting and clearing the CTPTR bit in MMCON0 register which resets the write pointer to the transmit FIFO. Figure 63. Command Transmission Flow Command Transmission Configure Response RESPEN = X RFMT = X CRCDIS = X Load Command in Buffer MMCMD = Index MMCMD = Argument Transmit Command CMDEN = 1 CMDEN = 0 Command Receiver The end of the response reception is signalled by the EORI flag in MMINT register.
AT89C5132 Data Line Controller The data line controller is based on a 16-byte FIFO used both by the data transmitter channel and by the data receiver channel. Figure 64. Data Line Controller Block Diagram MMINT.0 MMINT.2 MMSTA.3 MMSTA.4 F1EI F1FI DATFS CRC16S CRC16 and Format Checker Data Converter Serial -> // 8-byte TX Pointer FIFO 1 DTPTR MMCON0.6 RX Pointer DRPTR MMCON0.7 FIFO Implementation 16-byte FIFO MMDAT MCBI CBUSY MMINT.1 MMSTA.
Figure 65. Data Controller Configuration Flows Data Stream Configuration Data Single Block Configuration Data Multi-block Configuration Configure Format DFMT = 0 Configure Format DFMT = 1 MBLOCK = 0 BLEN3:0 = XXXXb Configure Format DFMT = 1 MBLOCK = 1 BLEN3:0 = XXXXb Data Transmitter Configuration For transmitting data to the card, user must first configure the data controller in transmission mode by setting the DATDIR bit in MMCON1 register.
AT89C5132 Figure 66.
Figure 67.
AT89C5132 This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving end of frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4). Data Reading Data is read from the FIFO by reading to MMDAT register. Each time one FIFO becomes full (F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data. Figure 68.
Figure 69. Data Block Reception Flows Data Block Reception Data Block Initialization Data Block Reception ISR Start Transmission DATEN = 1 DATEN = 0 Unmask FIFOs Full F1FM = 0 F2FM = 0 FIFO Full? F1EI or F2EI = 1? FIFO Full? F1EI or F2EI = 1? Start Transmission DATEN = 1 DATEN = 0 FIFO Reading read 8 data from MMDAT FIFO Reading read 8 data from MMDAT No More Data To Receive? No More Data To Receive? Mask FIFOs Full F1FM = 1 F2FM = 1 a. Polling Mode b.
AT89C5132 Interrupt Description As shown in Figure 70, the MMC controller implements eight interrupt sources reported in MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These flags were detailed in the previous sections. All of these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM, F1FM, and F2EM mask bits, respectively, in MMMSK register.
Registers Table 78. MMCON0 Register MMCON0 (S:E4h) – MMC Control Register 0 7 6 5 4 3 2 1 0 DRPTR DTPTR CRPTR CTPTR MBLOCK DFMT RFMT CRCDIS Bit Number Bit Mnemonic Description 7 DRPTR Data Receive Pointer Reset Bit Set to reset the read pointer of the data FIFO. Clear to release the read pointer of the data FIFO. 6 DTPTR Data Transmit Pointer Reset Bit Set to reset the write pointer of the data FIFO. Clear to release the write pointer of the data FIFO.
AT89C5132 Table 79. MMCON1 Register MMCON1 (S:E5h) – MMC Control Register 1 7 6 5 4 3 2 1 0 BLEN3 BLEN2 BLEN1 BLEN0 DATDIR DATEN RESPEN CMDEN Bit Number Bit Mnemonic Description 7-4 BLEN3:0 Block Length Bits Refer to Table 77 for Bits description. Do not program value > 1011b. 3 DATDIR Data Direction Bit Set to select data transfer from host to card (write mode). Clear to select data transfer from card to host (read mode).
Table 81. MMSTA Register MMSTA (S:DEh Read Only) – MMC Control and Status Register 7 6 5 4 3 2 1 0 - - CBUSY CRC16S DATFS CRC7S RESPFS CFLCK Bit Number Bit Mnemonic Description Reserved The values read from these Bits are always 0. Do not set these Bits. 7-6 - 5 CBUSY Card Busy Flag Set by hardware when the card sends a busy state on the data line. Cleared by hardware when the card no more sends a busy state on the data line.
AT89C5132 Table 82. MMINT Register MMINT (S:E7h Read Only) – MMC Interrupt Register 7 6 5 4 3 2 1 0 MCBI EORI EOCI EOFI F2FI F1FI F2EI F1EI Bit Number Bit Mnemonic Description 7 MCBI MMC Card Busy Interrupt Flag Set by hardware when the card enters or exits its busy state (when the busy signal is asserted or deasserted on the data line). Cleared when reading MMINT. 6 EORI End of Response Interrupt Flag Set by hardware at the end of response reception. Cleared when reading MMINT.
Table 83. MMMSK Register MMMSK (S:DFh) – MMC Interrupt Mask Register 7 6 5 4 3 2 1 0 MCBM EORM EOCM EOFM F2FM F1FM F2EM F1EM Bit Number Bit Mnemonic Description 7 MCBM MMC Card Busy Interrupt Mask Bit Set to prevent MCBI flag from generating an MMC interrupt. Clear to allow MCBI flag to generate an MMC interrupt. 6 EORM End Of Response Interrupt Mask Bit Set to prevent EORI flag from generating an MMC interrupt. Clear to allow EORI flag to generate an MMC interrupt.
AT89C5132 MMDAT (S:DCh) – MMC Data Register 7 6 5 4 3 2 1 0 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Bit Number 7-0 Bit Mnemonic Description MD7:0 MMC Data Byte Input (write) or output (read) register of the data FIFO. Reset Value = 1111 1111b Table 86. MMCLK Register MMCLK (S:EDh) – MMC Clock Divider Register 7 6 5 4 3 2 1 0 MMCD7 MMCD6 MMCD5 MMCD4 MMCD3 MMCD2 MMCD1 MMCD0 Bit Number 7-0 Bit Mnemonic Description MMCD7:0 MMC Clock Divider 8-bit divider for MMC clock generation.
IDE/ATAPI Interface The AT89C5132 provide an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlash cards, hard disk drive, etc. It consists of a 16-bit data transfer (read or write) between the AT89C5132 and the IDE devices. Description The IDE interface mode is enabled by setting the EXT16 bit in AUXR (see Table 14 on page 27). As soon as this bit is set, all MOVX instructions read or write are done in a 16bit mode compare to the standard 8-bit mode.
AT89C5132 Figure 72. IDE Write Waveforms CPU Clock ALE WR(1) P0 P2 Notes: IDE Device Connection P2 DPL or Ri D7:0 DPH or P2(2),(3) D15:8 P2 1. WR signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. 3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH. Figure 73 and Figure 74 show two examples on how to interface up to two IDE devices to the AT89C5132.
Table 87. External Data Memory Interface Signals Registers Signal Name Type Alternate Function A15:8 I/O Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. P2.7:0 AD7:0 I/O Address/Data Lines Multiplexed lower address and data lines for the IDE interface. P0.7:0 ALE O Address Latch Enable ALE signals indicates that valid address information is available on lines AD7:0.
AT89C5132 Serial I/O Port The serial I/O port in the AT89C5132 provides both synchronous and asynchronous communication modes. It operates as a Synchronous Receiver and Transmitter in one single mode (Mode 0) and operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3). Asynchronous modes support framing error detection and multiprocessor communication with automatic address recognition.
Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the timer. As shown in Figure 76, the Internal Baud Rate Generator is an 8-bit auto-reload timer feed by the peripheral clock or by the peripheral clock divided by 6 depending on the SPD bit in BDRCON register (see Table 95). The Internal Baud Rate Generator is enabled by setting BBR bit in BDRCON register. SMOD1 bit in PCON register allows doubling of the generated baud rate. Figure 76.
AT89C5132 Figure 78. Transmission Waveforms (Mode 0) TXD Write to SBUF RXD D0 D1 D2 D3 D4 D5 D6 D7 TI Reception (Mode 0) To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI Bits and setting the REN bit. As shown in Figure 79, Clock is pulsed and the LSB (D0) is sampled on the RXD pin. The D0 bit is then shifted into the shift register. After eight sampling, the MSB (D7) is shifted into the shift register, and hardware asserts RI bit to indicate a completed reception.
Asynchronous Modes (Modes 1, 2 and 3) The Serial Port has one 8-bit and two 9-bit asynchronous modes of operation. Figure 82 shows the Serial Port block diagram in asynchronous modes. Figure 82. Serial I/O Port Block Diagram (Modes 1, 2 and 3) SCON.6 SCON.7 SCON.3 SM1 SM0 TB8 Mode Decoder SBUF Tx SR TXD Rx SR RXD M3 M2 M1 M0 T1 CLOCK Mode & Clock Controller IBRG CLOCK PER CLOCK Mode 1 SBUF Rx RB8 SCON.2 SM2 TI RI SCON.4 SCON.1 SCON.0 Mode 1 is a full-duplex, asynchronous mode.
AT89C5132 Framing Error Detection (Modes 1, 2 and 3) Framing error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set SMOD0 bit in PCON register as shown in Figure 85. When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two devices.
Table 90. Baud Rate Generator Configuration FPER = 6 MHz(1) FPER = 8 MHz(1) FPER = 10 MHz(1) Baud Rate SPD SMOD1 BRL Error% SPD SMOD1 BRL Error% SPD SMOD1 BRL Error% 115200 - - - - - - - - - - - - 57600 - - - - 1 1 247 3.55 1 1 245 1.36 38400 1 1 246 2.34 1 1 243 0.16 1 1 240 1.73 19200 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 9600 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 4800 1 1 178 0.16 1 1 152 0.16 1 1 126 0.
AT89C5132 Multiprocessor Communication (Modes 2 and 3) Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To enable this feature, set SM2 bit in SCON register. When the multiprocessor communication feature is enabled, the Serial Port can differentiate between data frames (ninth bit clear) and address frames (ninth bit set). This allows the AT89C5132 to function as a slave processor in an environment where multiple slave processors share a single serial line.
The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000B). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with Bits 0 and 1 both set (e.g. 1111 0011B).
AT89C5132 Interrupt The Serial I/O Port handles two interrupt sources that are the “end of reception” (RI in SCON) and “end of transmission” (TI in SCON) flags. As shown in Figure 90 these flags are combined together to appear as a single interrupt source for the C51 core. Flags must be cleared by software when executing the serial interrupt service routine. The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register.
Registers Table 91. SCON Register SCON (S:98h) – Serial Control Register 7 6 5 4 3 2 1 0 FE/SM0 OVR/SM1 SM2 REN TB8 RB8 TI RI Bit Number Bit Mnemonic Description FE 7 Framing Error Bit To select this function, set SMOD0 bit in PCON register. Set by hardware to indicate an invalid stop bit. Must be cleared by software. SM0 Serial Port Mode Bit 0 Refer to Table 89 for mode selection. SM1 Serial Port Mode Bit 1 Refer to Table 89 for mode selection.
AT89C5132 Table 92. SBUF Register SBUF (S:99h) – Serial Buffer Register 7 6 5 4 3 2 1 0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Bit Number 7-0 Bit Mnemonic Description SD7:0 Serial Data Byte Read the last data received by the Serial I/O Port. Write the data to be transmitted by the Serial I/O Port. Reset value = XXXX XXXXb Table 93.
Table 95. BDRCON Register BDRCON (S:92h) – Baud Rate Generator Control Register 7 6 5 4 3 2 1 0 - - - BRR TBCK RBCK SPD M0SRC Bit Number Bit Mnemonic Description Reserved The values read from these Bits are indeterminate. Do not set these Bits. 7-5 - 4 BRR Baud Rate Run Bit Set to enable the baud rate generator. Clear to disable the baud rate generator. 3 TBCK Transmission Baud Rate Selection Bit Set to select the baud rate generator as transmission baud rate generator.
AT89C5132 Synchronous Peripheral Interface The AT89C5132 implement a Synchronous Peripheral Interface with master and slave modes capability. Figure 92 shows an SPI bus configuration using the AT89C5132 as master connected to slave peripherals. Figure 93 shows an SPI bus configuration using the AT89C5132 as slave of an other master. The bus is made of three wires connecting all the devices together: • Master Output Slave Input (MOSI): it is used to transfer data in series from the master to a slave.
Description The SPI controller interfaces with the C51 core through three special function registers: SPCON, the SPI control register (see Table 98); SPSTA, the SPI status register (see Table 99); and SPDAT, the SPI data register (see Table 100). Master Mode The SPI operates in master mode when the MSTR bit in SPCON is set. Figure 94 shows the SPI block diagram in master mode. Only a master SPI module can initiate transmissions. Software begins the transmission by writing to SPDAT.
AT89C5132 Figure 95. SPI Slave Mode Block Diagram MISO/P4.2 I 8-bit Shift Register Q Internal Bus MOSI/P4.1 SPDAT WR SPDAT RD SCK/P4.2 Control and Clock Logic SS/P4.3 SPIF SPSTA.7 SSDIS SPCON.5 Note: CPHA CPOL SPCON.2 SPCON.3 MSTR bit in SPCON is cleared to select slave mode. Bit Rate The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and SPR0 control Bits in SPCON according to Table 97.
Figure 96. Data Transmission Format (CPHA = 0) SCK Cycle Number 1 2 3 4 5 6 7 8 MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) MSB SS (to Slave) to Capture Point Figure 97.
AT89C5132 Figure 98. SS Timing Diagram SI/SO Byte 1 Byte 2 Byte 3 SS (CPHA = 0) SS (CPHA = 1) Error Conditions Interrupt The following flags signal the SPI error conditions: • MODF in SPSTA signals a mode fault. MODF flag is relevant only in master mode when SS usage is enabled (SSDIS bit cleared). It signals when set that another master on the bus has asserted SS pin and so, may create a conflict on the bus with two masters sending data at the same time.
Configuration The SPI configuration is made through SPCON. Master Configuration The SPI operates in master mode when the MSTR bit in SPCON is set. Slave Configuration The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has been loaded in SPDAT.
AT89C5132 Master Mode with Interrupt Policy Figure 101 shows the initialization phase and the transfer phase flows using the interrupt policy. Using this flow prevents any overrun error occurrence. • The bit rate is selected according to Table 97. • The transfer format depends on the slave peripheral. • SS may be deasserted between transfers depending also on the slave peripheral. Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag. Clear is effective when reading SPDAT.
Slave Mode with Polling Policy Figure 102 shows the initialization phase and the transfer phase flows using the polling policy. The transfer format depends on the master controller. SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the “end of reception” check). This policy provides the fastest effective transmission and is well adapted when communicating at high speed with other Microcontrollers. However, the procedure may be interrupted at any time by higher priority tasks.
AT89C5132 Slave Mode with Interrupt Policy Figure 101 shows the initialization phase and the transfer phase flows using the interrupt policy. The transfer format depends on the master controller. Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag. Clear is effective when reading SPDAT. Figure 103.
Bit Number Bit Mnemonic Description SPI Clock Polarity Bit(1) 3 CPOL 2 CPHA 1-0 SPR1:0 Set to have the clock output set to high level in idle state. Clear to have the clock output set to low level in idle state. SPI Clock Phase Bit Set to have the data sampled when the clock returns to idle state (see CPOL). Clear to have the data sampled when the clock leaves the idle state (see CPOL). SPI Rate Bits 0 and 1 Refer to Table 97 for bit rate description. Reset Value = 0001 0100b Note: 1.
AT89C5132 Two-wire Interface (TWI) Controller The AT89C5132 implements a TWI controller supporting the four standard master and slave modes with multimaster capability. Thus, it allows connection of slave devices like LCD controller, audio DAC, etc., but also external master controlling where the AT89C5132 is used as a peripheral of a host. The TWI bus is a bi-directional TWI serial communication standard. It is designed primarily for simple but efficient integrated circuit control.
Figure 105. Complete Data Transfer on TWI Bus SDA MSB Slave Address SCL 1 2 R/W ACK direction signal bit from receiver 8 Nth data Byte 9 S 1 2 ACK signal from receiver 8 9 Clock Line Held Low While Serial Interrupts Are Serviced P/S The four operating modes are: • Master transmitter • Master receiver • Slave transmitter • Slave receiver Data transfer in each mode of operation are shown in Figure 106 through Figure 109.
AT89C5132 Bit Rate The bit rate can be selected from seven predefined bit rates or from a programmable bit rate generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see Table 26). The predefined bit rates are derived from the peripheral clock (FPER) issued from the Clock Controller block as detailed in Section "Oscillator", page 12, while bit rate generator is based on timer 1 overflow output. Table 19.
Master Receiver Mode In the master receiver mode, a number of data Bytes are received from a slave transmitter (see Figure 107). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt routine must load SSDAT with the 7 - bit slave address and the data direction bit (SLA+R). The serial interrupt flag (SSI) must then be cleared before the serial transfer can continue.
AT89C5132 Slave Transmitter Mode In the slave transmitter mode, a number of data Bytes are transmitted to a master receiver (see Figure 109). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the controller waits until it is addressed by its own slave address followed by the data direction bit which must be logic 1 (R) for operating in the slave transmitter mode.
Figure 106.
AT89C5132 Figure 107.
Figure 108. Format and States in the Slave Receiver Mode Reception of the own slave address and one or more data Bytes.
AT89C5132 Figure 109. Format and States in the Slave Transmitter Mode Reception of the own slave address and transmission of one or more data Bytes. S SLA R A Data A8h Arbitration lost as master and addressed as slave A B8h Data A P or S C0h A B0h Last data Byte transmitted. Switched to not addressed slave (SSAA = 0).
Table 20.
AT89C5132 Table 21. Status for Master Receiver Mode Application Software Response Status Code SSSTA To SSCON Status of the TWI Bus and TWI Hardware To/From SSDAT SSSTA SSSTO SSI SSAA X 0 0 X X 0 0 X X 0 0 X SLA+W will be transmitted. Logic will switch to master transmitter mode. 0 0 0 X TWI bus will be released and not addressed slave mode will be entered. 1 0 0 X A START condition will be transmitted when the bus becomes free.
Table 22. Status for Slave Receiver Mode with Own Slave Address Application Software Response Status Code SSSTA 60h 68h 80h To SSCON Status of the TWI Bus and TWI Hardware To/From SSDAT SSSTA SSSTO SSI SSAA Own SLA+W has been received; ACK has been returned No SSDAT action X 0 0 0 Data Byte will be received and NOT ACK will be returned. No SSDAT action X 0 0 1 Data Byte will be received and ACK will be returned.
AT89C5132 Table 23.
Table 24. Status for Slave Transmitter Mode Application Software Response Status Code SSSTA A8h B0h B8h Status of the TWI Bus and TWI Hardware To SSCON To/From SSDAT SSSTA SSSTO SSI SSAA Own SLA+R has been received; ACK has been returned Write data Byte X 0 0 0 Last data Byte will be transmitted. Write data Byte X 0 0 1 Data Byte will be transmitted.
AT89C5132 Registers Table 26. SSCON Register SSCON (S:93h) – Synchronous Serial Control Register 7 6 5 4 3 2 1 0 SSCR2 SSPE SSSTA SSSTO SSI SSAA SSCR1 SSCR0 Bit Number Bit Mnemonic Description Synchronous Serial Control Rate Bit 2 Refer to Table 19 for rate description. 7 SSCR2 6 SSPE Synchronous Serial Peripheral Enable Bit Set to enable the controller. Clear to disable the controller. 5 SSSTA Synchronous Serial Start Flag Set to send a START condition on the bus.
Table 27. SSSTA Register SSSTA (S:94h) – Synchronous Serial Status Register 7 6 5 4 3 2 1 0 SSC4 SSC3 SSC2 SSC1 SSC0 0 0 0 Bit Number Bit Mnemonic Description 7:3 SSC4:0 2:0 0 Synchronous Serial Status Code Bits 0 to 4 Refer to Table 20 to Table 109 for status description. Always 0. Reset Value = F8h Table 28.
AT89C5132 Analog to Digital Converter The AT89C5132 implement a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). First channel of this ADC can be used for battery monitoring while the second one can be used for voice sampling at 8 kHz.
Clock Generator The ADC clock is generated by division of the peripheral clock (see details in Section “X2 Feature”, page 12). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure 112 shows the ADC clock generator and its calculation formula(1). Figure 112. ADC Clock Generator and Symbol Caution: ADCLK PER CLOCK ÷2 ADCD4:0 ADC CLOCK ADC Clock ADC Clock Symbol PERclk ADCclk = ------------------------2 ⋅ ADCD Note: 1.
AT89C5132 Figure 113. ADC Configuration Flow ADC Configuration Program ADC Clock ADCD4:0 = xxxxxb Enable ADC ADIDL = x ADEN = 1 Wait Setup Time Conversion Launching The conversion is launched by setting the ADSST bit in ADCON register, this bit remains set during the conversion. As soon as the conversion is started, it takes 11 clock periods (TCONV) before the data is available in ADDH and ADDL registers. Figure 114.
Registers Table 31. ADCON Register ADCON (S:F3h) – ADC Control Register 7 6 5 4 3 2 1 0 - ADIDL ADEN ADEOC ADSST - - ADCS Bit Number Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. 7 - 6 ADIDL ADC Pseudo-Idle Mode Set to suspend the CPU core activity (pseudo-idle mode) during conversion. Clear by hardware at the end of conversion. 5 ADEN ADC Enable Bit Set to enable the A to D converter.
AT89C5132 Table 33. ADDH Register ADDH (S:F5h Read Only) – ADC Data High Byte Register 7 6 5 4 3 2 1 0 ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 Bit Number 7-0 Bit Mnemonic Description ADAT9:2 ADC Data 8 Most Significant Bits of the 10-bit ADC data. Reset Value = 0000 0000b Table 34.
Keyboard Interface The AT89C5132 implements a keyboard interface allowing the connection of a 4 x n matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1.3:0 and allow exit from idle and power down modes.
AT89C5132 Registers Table 101. KBCON Register KBCON (S:A3h) – Keyboard Control Register 7 6 5 4 3 2 1 0 KINL3 KINL2 KINL1 KINL0 KINM3 KINM2 KINM1 KINM0 Bit Number Bit Mnemonic Description 7-4 KINL3:0 Keyboard Input Level Bit Set to enable a high level detection on the respective KIN3:0 input. Clear to enable a low level detection on the respective KIN3:0 input. 3-0 KINM3:0 Keyboard Input Mask Bit Set to prevent the respective KINF3:0 flag from generating a keyboard interrupt.
Electrical Characteristics Absolute Maximum Ratings Storage Temperature ..................................... -65°C to +150°C Voltage on any other Pin to VSS NOTE: ..................................... -0.3 to +4.0V IOL per I/O Pin ................................................................. 5 mA Power Dissipation ............................................................. 1 W Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only.
AT89C5132 Table 1. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C Symbol Parameter ILI Input Leakage Current (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) ITL Logical 1 to 0 Transition Current (P1, P2, P3, P4 and P5) RRST CIO VRET Typ(1) Min Pull-Down Resistor 50 90 Pin Capacitance Max Units 10 µA 0.45< VIN< VDD -650 µA Vin = 2.0 V 200 kΩ 10 pF VDD Data Retention Limit 1.8 VDD < 3.3 V Operating Current X1 / X2 mode 6.5 / 10.5 8 / 13.5 9.
Figure 2. IDL Test Condition, Idle Mode VDD RST VSS (NC) Clock Signal VDD PVDD UVDD AVDD X2 X1 IDL VDD P0 VSS PVSS UVSS AVSS VSS TST All other pins are unconnected Figure 3.
AT89C5132 A-to-D Converter Table 2. A-to-D Converter DC Characteristics VDD = 2.7 to 3.3V , TA = -40°C to +85°C Symbol Parameter Min Typ Max Units 3.3 V Test Conditions AVDD Analog Supply Voltage AIDD Analog Operating Supply Current 600 µA AVDD = 3.3V AIN1:0 = 0 to AVDD AIPD Analog Standby Current 2 µA AVDD = 3.3V ADEN = 0 or PD = 1 AVIN Analog Input Voltage AVSS AVDD V AVREF Reference Voltage AREFN AREFP AVSS 2.
Phase Lock Loop Schematic Figure 5. PLL Filter Connection FILT R C2 C1 VSS Parameters VSS Table 4. PLL Filter Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C Symbol Parameter Min Typ Max Unit R Filter Resistor 100 Ω C1 Filter Capacitance 1 10 nF C2 Filter Capacitance 2 2.2 nF USB Connection Schematic Figure 6. USB Connection To Power Supply RUSB VBUS D+ D- D+ D- RUSB GND VSS Parameters Table 1. USB Termination Characteristics VDD = 2.7 to 3.
AT89C5132 AC Characteristics External 8-bit Bus Cycles Definition of Symbols Table 1. External 8-bit Bus Cycles Timing Symbol Definitions Signals Timings Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD Z Floating W WR Test conditions: capacitive load on all pins = 50 pF. Table 2. External 8-bit Bus Cycle – Data Read AC Timings VDD = 2.7 to 3.
Table 3. External 8-bit Bus Cycle – Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol Waveforms Parameter Min TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLWL ALE Low to WR Low 3·TCLCL-30 1.
AT89C5132 Figure 2. External 8-bit Bus Cycle – Data Write Waveforms ALE TLHLL TLLWL TWHLH TWLWH WR TAVWL TAVLL P0 TLLAX TQVWH A7:0 TWHQX D7:0 Data Out P2 A15:8 External IDE 16-bit Bus Cycles Definition of Symbols Table 4. External IDE 16-bit Bus Cycles Timing Symbol Definitions Signals Timings Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD Z Floating W WR Test conditions: capacitive load on all pins = 50 pF.
Table 5. External IDE 16-bit Bus Cycle – Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLRL ALE Low to RD Low 3·TCLCL-30 1.
AT89C5132 Waveforms Figure 3. External IDE 16-bit Bus Cycle – Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD TRLDV TRHDZ TRLAZ TAVLL P0 TLLAX TRHDX A7:0 D7:0 TAVRL Data In TAVDV P2 A15:8 D15:81 Data In Note: D15:8 is written in DAT16H SFR. Figure 4. External IDE 16-bit Bus Cycle – Data Write Waveforms ALE TLHLL TLLWL TWHLH TWLWH WR TAVWL TAVLL P0 TLLAX TQVWH A7:0 TWHQX D7:0 Data Out P2 A15:8 D15:81 Data Out Note: D15:8 is the content of DAT16H SFR.
Timings Table 8. SPI Interface Master AC Timing VDD = 2.7 to 3.3V, TA = -40° to +85°C Symbol Parameter Min Max Unit Slave Mode TCHCH Clock Period TCHCX 8 TOSC Clock High Time 3.2 TOSC TCLCX Clock Low Time 3.
AT89C5132 Waveforms Figure 5. SPI Slave Waveforms (SSCPHA = 0) SS (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) TCHCH TCHCX TCLCH TCLSH TCHSH TSHSL TCLCX TCHCL SCK (SSCPOL = 1) (input) TCLOV TCHOV TSLOV MISO (output) SLAVE MSB OUT BIT 6 TCLOX TCHOX TSHOX SLAVE LSB OUT 1 TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN 1. Not Defined but generally the MSB of the character which has just been received. Figure 6.
Figure 7. SPI Master Waveforms (SSCPHA = 0) SS1 (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) TCHCH TCHCX TCLCH TCLSH TCHSH TSHSL TCLCX TCHCL SCK (SSCPOL = 1) (input) TCHOV TCLOV TSLOV MISO (output) 1 SLAVE MSB OUT BIT 6 TCHOX TCLOX TSHOX SLAVE LSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN 1. SS handled by software using general purpose port pin. Figure 8.
AT89C5132 Two-wire Interface Timings Table 1. TWI Interface AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85°C INPUT Min Max OUTPUT Min Max Start condition hold time 14·TCLCL(4) 4.0 µs(1) TLOW SCL low time 16·TCLCL(4) 4.7 µs(1) THIGH SCL high time 14·TCLCL(4) 4.0 µs(1) TRC SCL rise time 1 µs -(2) TFC SCL fall time 0.3 µs 0.
MMC Interface Definition of Symbols Table 9. MMC Interface Timing Symbol Definitions Signals Timings Conditions C Clock H High D Data In L Low O Data Out V Valid X No Longer Valid Min Max Table 10. MMC Interface AC Timings VDD = 2.7 to 3.
AT89C5132 Audio Interface Definition of Symbols Table 11. Audio Interface Timing Symbol Definitions Signals Timings Conditions C Clock H High O Data Out L Low S Data Select V Valid X No Longer Valid Table 12. Audio Interface AC timings VDD = 2.7 to 3.
Analog to Digital Converter Definition of Symbols Table 13. Analog to Digital Converter Timing Symbol Definitions Signals Characteristics Conditions C Clock H High E Enable (ADEN bit) L Low S Start Conversion (ADSST bit) Table 2. Analog to Digital Converter AC Characteristics VDD = 2.7 to 3.
AT89C5132 Figure 13. Analog-to-Digital Converter Characteristics Offset Gain Error Error OSe Ge Code Out 1023 1022 1021 1020 1019 1018 Ideal Transfer Curve Example of an Actual Transfer Curve 7 6 5 Center of a Step 4 Integral Non-linearity (ILe) 3 Differential Non-linearity (DLe) 2 1 0 0 1 LSB (Ideal) AVIN (LSBideal) 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 Offset Error OSe Flash Memory Definition of Symbols Table 14.
Waveforms Figure 14. Flash Memory – ISP Waveforms RST TSVRL TRLSX (1) ISP Note: 1. ISP must be driven through a pull-down resistor (see Section “In-system Programming”, page 22). Figure 15. Flash Memory – Internal Busy Waveforms FBUSY bit TBHBL External Clock Drive and Logic Level References Definition of Symbols Table 16. External Clock Timing Symbol Definitions Signals C Timings Conditions Clock H High L Low X No Longer Valid Min Max Table 17. External Clock AC Timings VDD = 2.
AT89C5132 Figure 17. AC Testing Input/Output Waveforms INPUTS VDD - 0.5 0.45 V Notes: OUTPUTS 0.7 VDD VIH min 0.3 VDD VIL max 1. During AC testing, all inputs are driven at VDD -0.5V for a logic 1 and 0.45V for a logic 0. 2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0. Figure 18. Float Waveforms VLOAD VLOAD + 0.1V VLOAD - 0.1V Note: Timing Reference Points VOH - 0.1V VOL + 0.
Ordering Information Possible Order Entries(1) Part Number Memory Size (Bytes) Supply Voltage Temperature Range Max Frequency (MHz) AT89C5132-ROTIL 64K Flash 3V Industrial 40 Note: 38 Package TQFP80 Packing Tray Product Marking 895132-IL 1. PLCC84 package only available for development board.
AT89C5132 Package Information TQFP80 39 4173C–USB–07/04
PLCC84 40 AT89C5132 4173C–USB–07/04
AT89C5132 Datasheet Change Log for AT89C5132 Changes from 4173A08/02 to 4173B-03/04 1. Supression of ROM product version. Changes from 4173B03/04 - 4173C - 07/04 1. Add USB connection schematic in USB section. 2. Supression of TQFP64 package. 2. Add USB termination characteristics in DC Characteristics section. 3. Page access mode clarification in Data Memory section.
Features ................................................................................................. 1 Description ............................................................................................ 1 Typical Applications ............................................................................. 1 Block Diagram ....................................................................................... 2 Pin Description ...........................................................................
AT89C5132 Timer/Counter Operations .................................................................................. 48 Timer Clock Controller ........................................................................................ 48 Timer 0................................................................................................................ 49 Timer 1................................................................................................................ 51 Interrupt ....................
Multiprocessor Communication (Modes 2 and 3) ..............................................111 Automatic Address Recognition........................................................................ 111 Interrupt .............................................................................................................113 Registers............................................................................................................114 Synchronous Peripheral Interface .................................
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