Datasheet

AT89C5132

4173C–USB–07/04

Table 69. UFNUMH Register

UFNUMH (S:BBh, Read-only) – USB Frame Number High Register

Reset Value = 00h

Table 70. USBCLK Register

USBCLK (S:EAh) – USB Clock Divider Register

Reset Value = 0000 0000b

76543210

- - CRCOK CRCERR - FNUM10 FNUM9 FNUM8

Bit

Number

Bit

Mnemonic Description

7 - 3 -

Reserved

The values read from these Bits are always 0. Do not set these Bits.

5 CRCOK

Frame Number CRC OK Bit

Set by hardware after a non corrupted Frame Number in Start of Frame Packet is

received.

Updated after every Start Of Frame packet reception.

Note: The Start Of Frame interrupt is generated just after the PID receipt.

4 CRCERR

Frame Number CRC Error Bit

Set by hardware after a corrupted Frame Number in Start of Frame Packet is

received.

Updated after every Start Of Frame packet reception.

Note: The Start Of Frame interrupt is generated just after the PID receipt.

Reserved

The values read from this Bits are always 0. Do not set this bit.

2 - 0 FNUM10:8

Frame Number

Upper 3 Bits of the 11-bit Frame Number. It is provided in the last received SOF

packet. FNUM does not change if a corrupted SOF is received.

76543210

------USBCD1 USBCD0

Bit

Number

Bit

Mnemonic Description

7 - 2 -

Reserved

The values read from these Bits are always 0. Do not set these Bits.

1 - 0 USBCD1:0

USB Controller Clock Divider

2-bit divider for USB controller clock generation.