USB Microcontroller with 64K Bytes Flash Memory Specification Sheet

ManualsBrandsAtmel ManualsComputer HardwareAT89C5132

Features

• Programmable Audio Output for Interfacing with Common Audio DAC

– PCM Format Compatible

–I

S Format Compatible

• 8-bit MCU C51 Core-based (F

MAX

= 20 MHz)

• 2304 Bytes of Internal RAM

• 64K Bytes of Code Memory

– AT89C5132: Flash (100K Write/Erase Cycles)

• 4K Bytes of Boot Flash Memory (AT89C5132)

– ISP: Download from USB (standard) or UART (option)

• USB Rev 1.1 Device Controller

– “Full Speed” Data Transmission

• Built-in PLL

• MultiMedia Card

Interface Compatibility

• Atmel DataFlash

SPI Interface Compatibility

• IDE/ATAPI Interface

• 2 Channels 10-bit ADC, 8 kHz (8 True Bits)

– Battery Voltage Monitoring

– Voice Recording Controlled by Software

• Up to 44 Bits of General-purpose I/Os

– 4-bit Interrupt Keyboard Port for a 4 x n Matrix

–SmartMedia

Software Interface

• Two Standard 16-bit Timers/Counters

• Hardware Watchdog Timer

• Standard Full Duplex UART with Baud Rate Generator

• Two Wire Master and Slave Modes Controller

• SPI Master and Slave Modes Controller

• Power Management

– Power-on Reset

– Software Programmable MCU Clock

– Idle Mode, Power-down Mode

• Operating Conditions

–3V, ±10%, 25 mA Typical Operating at 25°C

– Temperature Range: -40°C to +85°C

• Packages

– TQFP80, PLCC84 (Development Board Only)

–Dice

1. Description

The AT89C5132 is a mass storage device controlling data exchange between various

Flash modules, HDD and CD-ROM.

The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Program-

ming through an embedded 4K Bytes of Boot Flash Memory.

The AT89C5132 include 2304 Bytes of RAM memory.

The AT89C5132 provides all the necessary features for man-machine interface

including, timers, keyboard port, serial or parallel interface (USB, SPI, IDE), ADC

input, I

S output, and all external memory interface (NAND or NOR Flash, SmartMe-

dia, MultiMedia, DataFlash cards).

2. Typical Applications

• Flash Recorder/Writer

• PDA, Camera, Mobile Phone

• PC Add-on

USB

Microcontroller

with 64K Bytes

Flash Memory

AT89C5132

4173ES–USB–09/07

Summary of content (38 pages)

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Features • Programmable Audio Output for Interfacing with Common Audio DAC • • • • • • • • • • • • • • • • • • • – PCM Format Compatible – I2S Format Compatible 8-bit MCU C51 Core-based (FMAX = 20 MHz) 2304 Bytes of Internal RAM 64K Bytes of Code Memory – AT89C5132: Flash (100K Write/Erase Cycles) 4K Bytes of Boot Flash Memory (AT89C5132) – ISP: Download from USB (standard) or UART (option) USB Rev 1.
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3. Block Diagram Figure 3-1.
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AT89C5132 4. Pin Description AT89C5132 80-pin TQFP Package 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 Figure 4-1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TQFP80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.
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AT89C5132 84-pin PLCC (1) 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 Figure 4-2. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PLCC84 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.
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AT89C5132 Signal Name Type P2.7:0 I/O Description Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. Alternate Function A15:8 RXD TXD INT0 INT1 T0 T1 WR RD I/O Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups. P4.7:0 I/O Port 4 P4 is an 8-bit bidirectional I/O port with internal pull-ups. MISO MOSI SCK SS P5.3:0 I/O Port 5 P5 is a 4-bit bidirectional I/O port with internal pull-ups. - P3.7:0 Table 2.
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Signal Name Type Alternate Function T0 I Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. P3.4 T1 I Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments the count. P3.5 Description Table 4.
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AT89C5132 Table 7. UART Signal Description Signal Name Type RXD I/O Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. P3.0 TXD O Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. P3.1 Description Alternate Function Table 8.
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Table 11. Keypad Interface Signal Description Signal Name Type KIN3:0 I Alternate Function Description Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. P1.3:0 Table 12. External Access Signal Description Signal Name Type Alternate Function A15:8 I/O Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. P2.
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AT89C5132 Table 14. Power Signal Description Signal Name Type Description Alternate Function VDD PWR Digital Supply Voltage Connect these pins to +3V supply voltage. - VSS GND Circuit Ground Connect these pins to ground. - AVDD PWR Analog Supply Voltage Connect this pin to +3V supply voltage. - AVSS GND Analog Ground Connect this pin to ground. - PVDD PWR PLL Supply voltage Connect this pin to +3V supply voltage. - PVSS GND PLL Circuit Ground Connect this pin to ground.
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4.2 Internal Pin Structure Table 15. Detailed Internal Pin Structure Circuit(1) Type Pins Input TST Input/Output RST Input/Output P1(2) P2(3) P3 P4 P53:0 RTST VDD VDD P RRST Watchdog Output VSS 2 osc periods Latch Output VDD VDD VDD P1 P2 P3 N VSS VDD P Input/Output P0 MCMD MDAT ISP N PSEN VSS ALE SCLK DCLK VDD P Output DOUT DSEL MCLK N VSS D+ Input/Output D+ D- D- Notes: 10 1.
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AT89C5132 5. Address Spaces The AT8xC5132 derivatives implement four different address spaces: 5.0.1 • Program/Code Memory • Boot Memory • Data Memory • Special Function Registers (SFRs) Code Memory The AT89C5132 implements 64K Bytes of on-chip program/code memory in Flash technology. The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and programming.
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Peripherals The AT8xC5132 peripherals are briefly described in the following sections. For further details on how to interface (hardware and software) to these peripherals, please refer to the AT8xC5132 complete datasheet. Clock Generator System The AT8xC5132 internal clocks are extracted from an on-chip PLL fed by an on-chip oscillator. Four clocks are generated respectively for the C51 core, the audio interface, and the other peripherals.
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AT89C5132 Serial I/O Interface Serial Peripheral Interface Two-wire Controller The AT89C5132 implements a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex Universal Asynchronous Receiver Transmitter (UART) communication modes. It is provided for the following purposes: • In System Programming. • Remote control of the AT89C5132 by a host. The AT89C5132 implements a Serial Peripheral Interface (SPI) supporting master and slave modes.
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6. Electrical Characteristics 6.1 Absolute Maximum Ratings Storage Temperature ..................................... -65°C to +150°C Voltage on any other Pin to VSS *NOTICE: ..................................... -0.3 to +4.0V IOL per I/O Pin ................................................................. 5 mA Power Dissipation ............................................................. 1 W Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
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AT89C5132 Table 1. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol Parameter ILI Input Leakage Current (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) ITL Logical 1 to 0 Transition Current (P1, P2, P3, P4 and P5) RRST CIO VRET IDD Typ(1) Min Pull-Down Resistor 50 90 Pin Capacitance Max Units 10 μA 0.45< VIN< VDD -650 μA Vin = 2.0 V 200 kΩ 10 VDD Data Retention Limit pF 1.
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Figure 6-2. IDL Test Condition, Idle Mode VDD VDD PVDD UVDD AVDD RST VSS (NC) Clock Signal X2 X1 IDL VDD P0 VSS PVSS UVSS AVSS VSS Figure 6-3. TST All other pins are unconnected IPD Test Condition, Power-Down Mode VDD VDD PVDD UVDD AVDD RST VSS (NC) X2 X1 6.2.3 MCMD MDAT TST All other pins are unconnected A-to-D Converter Table 2. A-to-D Converter DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol Parameter Min AVDD Analog Supply Voltage 2.
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AT89C5132 6.2.4 6.2.4.1 Oscillator and Crystal Schematic Figure 6-4. Crystal Connection X1 C1 Q C2 VSS Note: 6.2.4.2 X2 For operation with most standard crystals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10 pF). X1 and X2 may not be used to drive other circuits. Parameters Table 3. Oscillator and Crystal Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol 6.2.5.
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6.2.5.2 Parameters Table 4. PLL Filter Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol 6.2.6 6.2.6.1 Parameter Min Typ Max Unit R Filter Resistor 100 Ω C1 Filter Capacitance 1 10 nF C2 Filter Capacitance 2 2.2 nF USB Connection Schematic Figure 6-6. USB Connection VDD To Power Supply VBUS D+ RFS D+ RUSB D- D- RUSB GND VSS 6.2.6.2 Parameters Table 16. USB Characteristics VDD = 3 to 3.3 V, TA = -40 to +85°C Symbol 6.2.7 6.2.7.
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AT89C5132 6.3 6.3.1 6.3.1.1 AC Characteristics External 8-bit Bus Cycles Definition of Symbols Table 6. External 8-bit Bus Cycles Timing Symbol Definitions Signals 6.3.1.2 Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD Z Floating W WR Timings Test conditions: capacitive load on all pins = 50 pF. Table 7. External 8-bit Bus Cycle – Data Read AC Timings VDD = 2.7 to 3.
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Table 8. External 8-bit Bus Cycle – Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol 6.3.1.3 Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLWL ALE Low to WR Low 3·TCLCL-30 1.
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AT89C5132 Figure 6-9. External 8-bit Bus Cycle – Data Write Waveforms ALE TLHLL TLLWL TWHLH TWLWH WR TAVWL TAVLL P0 TLLAX TQVWH A7:0 TWHQX D7:0 Data Out P2 6.3.2 6.3.2.1 A15:8 External IDE 16-bit Bus Cycles Definition of Symbols Table 9. External IDE 16-bit Bus Cycles Timing Symbol Definitions Signals 6.3.2.
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Table 10. External IDE 16-bit Bus Cycle – Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLRL ALE Low to RD Low 3·TCLCL-30 1.
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AT89C5132 6.3.2.3 Waveforms Figure 6-10. External IDE 16-bit Bus Cycle – Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD TRLDV TRHDZ TRLAZ TAVLL P0 TLLAX TRHDX A7:0 D7:0 TAVRL Data In TAVDV P2 A15:8 D15:81 Data In Note: D15:8 is written in DAT16H SFR. Figure 6-11. External IDE 16-bit Bus Cycle – Data Write Waveforms ALE TLHLL TLLWL TWHLH TWLWH WR TAVWL TAVLL P0 TLLAX A7:0 TQVWH TWHQX D7:0 Data Out P2 A15:8 D15:81 Data Out Note: 6.3.3 6.3.3.
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6.3.3.2 Timings Table 13. SPI Interface Master AC Timing VDD = 2.7 to 3.3V, TA = -40° to +85°C Symbol Parameter Min Max Unit Slave Mode TCHCH Clock Period TCHCX 8 TOSC Clock High Time 3.2 TOSC TCLCX Clock Low Time 3.
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AT89C5132 6.3.3.3 Waveforms Figure 6-12. SPI Slave Waveforms (SSCPHA = 0) SS (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) TCHCH TCHCX TCLCH TCLSH TCHSH TSHSL TCLCX TCHCL SCK (SSCPOL = 1) (input) TCLOV TCHOV TSLOV MISO (output) SLAVE MSB OUT BIT 6 TCLOX TCHOX TSHOX SLAVE LSB OUT 1 TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN 1. Not Defined but generally the MSB of the character which has just been received. Figure 6-13.
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Figure 6-14. SPI Master Waveforms (SSCPHA = 0) SS1 (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) TCHCH TCHCX TCLCH TCLSH TCHSH TSHSL TCLCX TCHCL SCK (SSCPOL = 1) (input) TCHOV TCLOV TSLOV MISO (output) 1 SLAVE MSB OUT BIT 6 TCHOX TCLOX TSHOX SLAVE LSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN 1. SS handled by software using general purpose port pin. Figure 6-15.
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AT89C5132 VDD = 2.7 to 3.3 V, TA = -40 to +85°C INPUT Min Max OUTPUT Min Max Start condition hold time 14·TCLCL(4) 4.0 μs(1) TLOW SCL low time 16·TCLCL(4) 4.7 μs(1) THIGH SCL high time 14·TCLCL(4) 4.0 μs(1) TRC SCL rise time 1 μs -(2) TFC SCL fall time 0.3 μs 0.
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6.3.5 6.3.5.1 MMC Interface Definition of Symbols Table 14. MMC Interface Timing Symbol Definitions Signals 6.3.5.2 Conditions C Clock H High D Data In L Low O Data Out V Valid X No Longer Valid Min Max Timings Table 15. MMC Interface AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL ≤ 100pF (10 cards) Symbol 6.3.5.
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AT89C5132 6.3.6 6.3.6.1 Audio Interface Definition of Symbols Table 16. Audio Interface Timing Symbol Definitions Signals 6.3.6.2 Conditions C Clock H High O Data Out L Low S Data Select V Valid X No Longer Valid Timings Table 17. Audio Interface AC timings VDD = 2.7 to 3.
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6.3.7 6.3.7.1 Analog to Digital Converter Definition of Symbols Table 18. Analog to Digital Converter Timing Symbol Definitions Signals 6.3.7.2 Conditions C Clock H High E Enable (ADEN bit) L Low S Start Conversion (ADSST bit) Characteristics Table 18. Analog to Digital Converter AC Characteristics VDD = 2.7 to 3.
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AT89C5132 6.3.7.3 Waveforms Figure 6-19. Analog-to-Digital Converter Internal Waveforms CLK TCLCL ADEN Bit TEHSH ADSST Bit TSHSL Figure 6-20.
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6.3.8 6.3.8.1 Flash Memory Definition of Symbols Table 19. Flash Memory Timing Symbol Definitions Signals 6.3.8.2 Conditions S ISP L Low R RST V Valid B FBUSY flag X No Longer Valid Timings Table 20. Flash Memory AC Timing VDD = 2.7 to 3.3V, TA = -40° to +85°C Symbol 6.3.8.
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AT89C5132 6.3.9.2 Timings Table 22. External Clock AC Timings VDD = 2.7 to 3.3V, TA= -40 to +85°C Symbol Parameter Max Unit TCLCL Clock Period 50 ns TCHCX High Time 10 ns TCLCX Low Time 10 ns TCLCH Rise Time 3 ns TCHCL Fall Time 3 ns Cyclic Ratio in X2 Mode 40 TCR 6.3.9.3 Min 60 % Waveforms Figure 6-23. External Clock Waveform TCLCH VDD - 0.5 0.45 V VIH1 TCHCX TCLCX VIL TCHCL TCLCL Figure 6-24. AC Testing Input/Output Waveforms INPUTS VDD - 0.5 0.
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7. Ordering Information Possible Order Entries(1) Max Frequency (MHz) 3V Industrial 40 TQFP80 Tray 895132-IL 3V Industrial & Green 40 TQFP80 Tray 895132-UL Part Number Supply Voltage AT89C5132-ROTIL 64K Flash AT89C5132-ROTUL Note: 34 Temperature Range Memory Size (Bytes) 64K Flash Package Packing Product Marking 1. PLCC84 package only available for development board.
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AT89C5132 8. Package Information 8.
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8.
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AT89C5132 9. Datasheet Revision History for AT89C5132 9.1 Changes from 4173A-08/02 to 4173B-03/04 1. Suppression of ROM product version. 2. Suppression of TQFP64 package. 9.2 Changes from 4173B-03/04 - 4173C - 07/04 1. Add USB connection schematic in USB section. 2. Add USB termination characteristics in DC Characteristics section. 3. Page access mode clarification in Data Memory section. 9.3 Changes from 4173C-07/04 - 4173D - 01/05 1.
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