Features • • • • • • • • • • • • • Maximum Supply Voltage 40V One Programmable/Adjustable Boost Converter Two Programmable Buck Converters One Programmable Linear Regulator OTP Customer Mode 16-bit Serial Interface Two ISO9141 Interfaces (One Interface Programmable to LIN Functionality) Watchdog Various Diagnosis Functions 5 Voltage Sources Tailored to Resistor Measurement Charge Pump Small, 44-pin Package ESD Protection Against 2kV and 4kV Airbag Power Supply IC ATA6264 1.
Figure 1-1.
ATA6264 [Preliminary] 1.1 Block Description 1.1.1 Integrated Boost Converter EVZ With an external n-channel FET, the integrated boost converter EVZ provides 3 different voltages adjustable via the serial interface for the energy reserve and firing capacitors. Two voltages are fixed values; one voltage can be adjusted using an external resistive divider. 1.1.
2. Pin Configuration Pinning QFP44 COMEVZO GNDB GEVZ OCEVZ FBEVZ CP SVCORE CP-OUT COMCOO COMCOI COMSATO Figure 2-1. 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 31 4 30 5 29 6 7 28 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 K15 EVZ SVSAT VSAT GNDD VINT COMSATI VCORE GNDA SVPERI VPERI RESQ RxD2 RxD1 TxD2 MISO SSQ SCLK MOSI RESQ2 IREF UZP USP K30 K1 K2 IASG1 IASG2 IASG3 IASG4 IASG5 ISENS TxD1 Table 2-1.
ATA6264 [Preliminary] Table 2-1.
3. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ATA6264 [Preliminary] 3. Absolute Maximum Ratings (Continued) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
4. Functional Range Within the functional range, the ATA6264 works as specified. All voltages are referenced to the ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins. At the beginning of each specification table, supply voltage and temperature conditions are described. Table 4-1. Electrical Characteristics – Functional Range No. Parameters 1.1 Test Conditions Pin Symbol Min. Voltage on pins K30, K15, USP 1.1a Voltage on pins K1, K2 Typ. Max. Unit –0.
ATA6264 [Preliminary] 4.1 Protection Against Substrate Currents Due to the fact that the ATA6264 is connected to the wiring harness and to components outside of the ECU, negative voltages at the following pins might occur: • IASG interface: IASG1, IASG2, IASG3, IASG4, IASG5 • USP comparator: USP If substrate currents occur, it is guaranteed by design that no disturbance and malfunction of the following blocks and functions will happen: • No disturbance of RESET block.
5. Supply Currents A minimum current has to flow into each pin for proper functioning of the IC. Table 5-1. Electrical Characteristics – Supply currents No. Parameters Test Conditions Pin Symbol Min. 2.1 Supply current at K30 Standby mode: 0V = VK30 = 18V, VK15 = 3V and KEYLATCH = OFF K30 IK30 2.1a Supply current at K30 Standby mode: 18V < VK30 = 40V, VK15 = 3V and KEYLATCH = OFF K30 2.1b Supply current at K30 Startup mode: 0V < VK30 = 18V, VK15 > 4.
ATA6264 [Preliminary] 5.1 Discharger Circuit Applications using the ATA6264 usually use a reverse polarity protection diode (D1 in Figure 5-1) in the power supply to prevent any damage if the wrong polarity is applied to VK30. Unfortunately, this method includes some risk as can be seen in the following description: During Standby mode (VK15 < 3V and KEYLATCH = OFF) the IC consumes only a low current, IK30.
The following settings can be made at the initial programming: MSBit VR1 Table 5-2. VR3 VR4 EXT ISO/LIN Parity LSBit Lock bit Initial Programming Settings VR1 VR2 VR3 VR4 0 0 0 0 0 0 0 1 1.88V 3.3V 0 0 1 0 1.88V 3.3V 9.1V 0 0 1 1 1.88V 3.3V 10.4V 0 1 0 0 2.5V 3.3V 7.8V 0 1 0 1 2.5V 3.3V 9.1V 0 1 1 0 2.5V 3.3V 10.4V 0 1 1 1 1.88V 5V 7.8V 1 0 0 0 1.88V 5V 9.1V 1 0 0 1 1.88V 5V 10.4V 1 0 1 0 2.5V 5V 7.8V 1 0 1 1 2.
ATA6264 [Preliminary] The IP data is valid only if the parity is odd. If the IP data is not valid, or if the lock bit is not set, the programming will not be executed. Figure 5-2. Programming Sequence Contact pins RESQ, RESQ2 TxD1, TxD2, SSQ, MOSI, SCLK, VPERI, K15, K30 Apply 12V at K15, K30 and5V at VPERI Set RESQ and TxD1 to GND and RESQ2 and TxD2 to 5V Transmit 5A5A(h) via SPI to Enable Testmode Wait until VSAT = 11.
5.3 Start-up and Power-down Procedure The ATA6264 is powered via the pin K30 (battery voltage) and via a diode or a resistor it is connected to the ignition key line K15. In order to detect an interruption on one of these pins correctly, resistors are implemented at these pins. Normally, the main supply pin of ATA6264 is pin K30. In the case of a missing or a too-low voltage at pin K30, the whole IC is supplied from the backup power supply capacitor hooked up to pin EVZ. Figure 5-3.
ATA6264 [Preliminary] Depending on the initial programming of the ATA6264, the start-up procedure takes place in different phases. 5.3.1 Start-up Procedure if VVCORE is Programmed to Be 5V or 2.5V Phase1: After switching on the ignition key, K15 voltage will apply at pin K15. If, in addition, the voltage at pin K30 is larger than 3.85V to 5V, the EVZ regulator will be enabled. The signal K15GOOD can be replaced by the serial interface command KEYLATCH which can be set via the serial interface.
Figure 5-4. Start-Up and Power-Down Procedure if VVCORE Programmed to Be 5V or 2.5V VK30 t VK15 3V to 4.15V 3V to 4.15V t VGEVZ Threshold to enable VCORE regulator t VEVZ 7.5V to 9V Threshold to start VCORE regulator too low EVZ voltage VSAT goes into On Mode charge pump deactivated 5.5V to 6.2V t VVSAT 6.77V to 7.2V 7V to 6.27V t VVPERI t VVCORE t 5.3.3 Start-up Procedure if VVCORE Programmed to Be 1.88V Phase1: After switching on the ignition key, the K15 voltage will appear at pin K15.
ATA6264 [Preliminary] 5.3.4 The Power-down Procedure for VVCORE is Programmed to be 1.88V Phase1: If the ignition key is switched off, the K15 voltage will vanish at pin K15. If the serial interface command KEYLATCH is not set, the EVZ regulator stops working. The external charge pump is still working because EVZ is above VSAT and the VSAT regulator is not in the Permanent-on mode. The charge-pump voltage still supplies the VSAT regulator and the VCORE regulator.
6. Power Supply Sequencing (Only active when initial programming sets VVCORE = 1.88V and VVPERI = 3.3V) In order to meet the requirements of several dual-voltage-supply microcontrollers, a power-sequencing function is implemented. The ATA6264 ensures that the voltage difference VPERI – VCORE will not exceed 2.8V. The voltage difference between VPERI and VCORE is monitored. In error cases, for example, if the VCORE regulator does not start to work, the difference may rise above the 2.8V threshold.
ATA6264 [Preliminary] Figure 6-2. Block Diagram Power Supply Sequencing K15 K15GOOD VEVZ VK15 = 3V to 4.15V (40 mV to 175mV Hysteresis) Comp K30 Serial interface (KEY - LATCH) CP K30GOOD IREF lost signal VK30 VK30 = 3.85V to 5V (50 mV to 150 mV Hysteresis) EVZEN Comp GEVZ VEVZ driver CORESWAP VK30 = 6.1V to 8.1V (ON) (0.5V to 1V Hysteresis) VCP 5V Comp IP VEVZ EVZ VEVZ = 7.5V to 9V (ON) VEVZ = 5.5V to 6.2V (OFF) VCP EVZGOOD Comp VSAT driver SVSAT VVSAT VSAT VEVZ VSATGOOD VSAT = 6.
7. Charge Pump To supply the VSAT and VCORE drivers, an external charge pump is provided. Both FETs(1) are driven by the high charge pump voltage VCP to ensure that they can be switched to a low-ohmic state. For correct function of the charge pump, an external capacitor of C = 47 nF has to be connected to pin SVSAT, and another of C = 100 nF to pin CP. A double diode has to be implemented for proper function of the charge pump.
ATA6264 [Preliminary] Necessary for operation: VEVZ = 5.5V to 40V or VK30 = 5.5V to 40V, VK15 > 3V, VVINT = 3.7V to 5.47V Operating conditions of all other supply pins: VVSAT, VVPERI and VVCORE are within functional range limits, Tj = –40°C to 150°C Other pins: As defined in Section 4. ”Functional Range” on page 8. Table 7-1. Electrical Characteristics – Charge Pump No. Parameters Test Conditions Pin Symbol Min 6.
8. GKEY Function The GKEY function is used to enable or disable the ECU via a powerless signal. If the voltage at pin K15 is larger than 3V to 4.15V, the charge pump and the EVZ regulator (for correct EVZ function, the K30 pin has to be connected to the battery) will start operating. If the K15 pin is open, an internal pull-down resistor of approximately 220 kΩ discharges the pin.
ATA6264 [Preliminary] Figure 8-2. Application With High Current Switch (GKEY Function Not Used) VBATT K15 K30 GKEYLogic GEVZ OCEVZ EVZ GNDB VEVZ EVZ FBEVZ COMEVZO Necessary for operation: VK15 = 3V to 40V, VK30 = 3.85V to 40V Operating conditions of all other supply pins: VEVZ, VSAT, VPERI and VCORE are within functional range limits, Tj = –40°C to 150°C Other pins: As defined in Section 4. ”Functional Range” on page 8. Table 8-2. Electrical Characteristics – GKEY Function No.
9. EVZ Step-up Regulator A boost converter generates the supply voltage for energy reserve and firing capacitors in the system. Using a voltage divider at pin FBEVZ, this voltage can be adjusted between 15V and 40V. Thus, high-voltage charged capacitors will be used to supply the whole system during the stand-alone time (for example, broken K30 line after a crash). The step-up regulator has to start running as soon as a certain threshold voltage at the K15 pin is exceeded.
ATA6264 [Preliminary] Figure 9-2. EVZ Regulator With Internal Divider K30 Max. duty-cycle Bandgap reference L Low battery Sawtooth oscillator + - + - Logic and driver GEVZ PWM comp. Error amp.
Figure 9-3. Functional Principle of the EVZ Regulator Sawtooth t Error amp. output = f (VEVZ) PWM output on off t The output transistor conduction is suppressed immediately if the current through the power FET exceeds a certain level, determined by the voltage drop across an external resistor in the range of 0.2Ω. The ATA6264 itself will see a voltage at the OCEVZ pin. If this voltage exceeds typically 0.5V, the output transistor conduction has to be suppressed.
ATA6264 [Preliminary] Necessary for operation: VK15 = 3V to 40V, VK30 = 5V to 40V, CGEVZ = 200 pF to 2 nF, VINT = 3.7V to 5.47V Operating conditions of all other supply pins: VSAT, VPERI and VCORE are within functional range limits, Tj = –40°C to 150°C Other pins: As defined in Section 4. ”Functional Range” on page 8. Table 9-1. Electrical Characteristics – EVZ Step-up Regulator No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type* 8.
Table 9-1. Electrical Characteristics (Continued)– EVZ Step-up Regulator No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type* 8.19a Overvoltage at pin EVZ to switch VEVZ1 programmed off the regulator VEVZ VEVZ 25 28.5 V A 8.19b Overvoltage at pin EVZ to switch VEVZ2 programmed off the regulator VEVZ VEVZ 35 39.5 V A 8.20 Overvoltage switch-off time Time between reaching overvoltage and reaching 90% of the value at numbers 8.7 and 8.
ATA6264 [Preliminary] Table 9-1. Electrical Characteristics (Continued)– EVZ Step-up Regulator No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type* Error Amplifier 8.32 Output current at pin COMEVZO sinking to low COMEVZO ICOMEVZO 0.4 3 mA A 8.33 Output current at pin COMEVZO driving to high COMEVZO ICOMEVZO –1000 –150 µA A 8.34 Input offset voltage –10 +10 mV D 8.35 DC open-loop gain 70 dB D 8.36 Unity-gain bandwidth 2 MHz D 8.
10. VSAT Power Supply A stabilized VSAT supply is realized by a buck converter. An external inductance is PWM-switched with a frequency of 200 kHz via an internal high-side DMOS power transistor. The VSAT power supply is connected to the boost converter output (EVZ), and uses the stored energy of the boost converter capacitor if the voltage at K30 is missing. The regulator uses both current and voltage feedback.
ATA6264 [Preliminary] Necessary for operation: VEVZ = 5.5V to 40V, VCP > VEVZ + 7V, VINT = 3.7V to 5.45V Operating conditions of all other supply pins: VK30, VPERI and VCORE are within functional range limits, Tj = –40°C to +150°C Other pins: As defined in Section 4. ”Functional Range” on page 8. Table 10-1. Electrical Characteristics – VSAT Power Supply No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type* 9.1 VEVZ voltage for the buck converter to start running EVZ VEVZ 7.
Table 10-1. Electrical Characteristics (Continued)– VSAT Power Supply No. Parameters Test Conditions Pin Symbol Min 9.15 Overcurrent switch-on time Time between reaching overcurrent and reaching 90% of VSVSAT maximum under on condition SVSAT tSVSAToff 9.16 Leakage current at pin SVSAT Output transistor off SVSAT Typ. Max. Unit Type* 0 0.5 µs A ISVSAT –10 +10 µA A Error Amplifier 9.17 Maximum output current at pin COMSATO sinking to low COMSATO ICOMSATO 200 3000 µA A 9.
ATA6264 [Preliminary] 11. VPERI Power Supply With the VPERI regulator a stabilized and ripple-free voltage is generated out of the VSAT supply voltage. This voltage is intended to be used for sensitive components, for example, sensors or reference inputs of A/D converters from microcontrollers. For this reason, a linear regulator is implemented to guarantee high ripple rejection and a precise voltage. The regulator output is short-circuit protected by an overcurrent protection.
Necessary for operation: VSAT > 7.5V, VINT = 3.7V to 5.47V, VCORE < VPERI + 0.3V Operating conditions of all other supply pins: VK30, VEVZ and VCORE are within functional range limits, Tj = –40°C to 150°C Other pins: As defined in Section 4. ”Functional Range” on page 8. Table 11-1. Electrical Characteristics – VPERI Power Supply No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type* 10.1 Voltage level at VSAT to enable VPERI regulator VSAT VVSAT 6.77 7.2 V A 10.
ATA6264 [Preliminary] 12. VCORE Power Supply The voltage of the VCORE regulator is generated out of the K30 voltage using a step-down regulator as long as the K30 voltage is available. During times when K30 is not present (power-down or stand-alone time), the VCORE regulator is supplied out of VEVZ. Depending on the initial programming, the supply switch signal is derived from the CORESWAP comparator or the EVZEN comparator.
Necessary for operation: VEVZ = 5.5V to 40V or VK30 = 5.5V to 40V, VCP > VEVZ + 7V or VCP > VK30 + 7V, VPERI > VCORE – 0.3V, VINT = 3.7V to 5.47V Operating conditions of all other supply pins: VSAT is within functional range limits, Tj = –40°C to 150°C Other pins: As defined in Section 4. ”Functional Range” on page 8. Table 12-1. Electrical Characteristics – VCORE Power Supply No. Parameters 11.1 VEVZ voltage for the VCORE Initial programming: regulator to start running VVCORE = 5V or 2.
ATA6264 [Preliminary] Table 12-1. No. Electrical Characteristics (Continued)– VCORE Power Supply Pin Symbol Max. Unit Type* SVCORE tSVCOREoff 150 ns A 11.14 Overvoltage switch-off time Time between reaching overvoltage and reaching 90% of VSCORE maximum under on condition SVORE tSVCOREoff 0 0.4 µs A 11.15 Overcurrent switch-off time Time between reaching overcurrent and reaching 90% of VSCORE maximum under on condition SVCORE tSVCOREoff 0 0.
Table 12-1. No. Electrical Characteristics (Continued)– VCORE Power Supply Parameters Test Conditions Pin 11.25 Leading-edge blanking time 11.26 Slope of artificial ramp for slope compensation Symbol Min tblank dV/dt Typ. Max. Unit Type* 150 200 ns D 80(1) 150(1) mV/µs D Voltage level at K30 to switch VK30 increasing VCORE supply from EVZ to See number 7.3 of Table 11.27 K30 (VVCORE = 1.8V or 2.5V 8-2 on page 23 programmed) A Hysteresis at K30 to switch VCORE supply from K30 to 11.
ATA6264 [Preliminary] 13. USP Comparator for General Purpose The USP comparator is used for general purposes, for example, low battery detection. An external resistive voltage divider provides the input signal for pin USP. A missing USP connection or VUSP < 2.44V sets the status register bit b7 to low. During normal operation (VUSP > 2.44V) the status register bit b7 stays high. Figure 13-1. Functional Principle of the USP Comparator to AMUX USP + Status register 2.
14. Reference Voltage and Reference Current Generation The pin IREF is an output derived directly from the chip’s internal reference voltage. This reference source is a band gap. All internally used precise voltages are derived from this band-gap voltage. At pin IREF a reference resistor of 12.4 kΩ has to be applied, providing a reference current. All internally used precise currents are derived from this current. In case of a missing resistor at IREF, the regulators will stop.
ATA6264 [Preliminary] 15. Reset Function (Pin RESQ and Pin RESQ2) Pins RESQ and RESQ2 are low-active digital outputs of the ATA6264, which provide a digital “low” signal in the case of a missing or incorrect watchdog transmission or in the case of improper VEVZ, VPERI or VCORE voltage. The voltage at pin RESQ depends on the proper voltages at pins EVZ, VCORE, and VPERI.
Figure 15-2.
ATA6264 [Preliminary] The RESQ2 signal results from a logical AND of the Reset signal and an OK signal from the watchdog circuitry, so RESQ2 will go high after the watchdog triggers correctly. RESQ and RESQ2 have to be set to low if VVPERI or VEVZ are below the specified threshold.
Table 15-1.
ATA6264 [Preliminary] Table 15-2. Electrical Characteristics – Reset Function (Pin RESQ and Pin RESQ2) No. Parameters Test Conditions Pin Symbol Min 14.1 RESQ and RESQ2 high level IRESQ, IRESQ2 = –200 µA to 0 µA RESQ RESQ2 VRESQ VRESQ2 14.2 RESQ and RESQ2 low level IRESQ, IRESQ2 = 0 mA to 2 mA RESQ RESQ2 14.3 Reset threshold at pin VCORE VVCORE is set to 5V Voltage difference 14.3a VVCORE – reset threshold at VCORE (see number 14.3) Max. Unit Type* VVPERI – 0.
Table 15-2. Electrical Characteristics (Continued)– Reset Function (Pin RESQ and Pin RESQ2) No. Parameters Test Conditions Pin Symbol Min Delay time for RESQ and RESQ2 to switch to low after 14.15 reaching the reset threshold of VEVZ RESQ RESQ2 tRESQ tRESQ2 RESQ is switched to low 14.16 Pull-down current at pin RESQ (VRESQ = 0.4V), 1V ≤ VVPERI < 5.5V RESQ RESQ2 is switched to low (VRESQ = 0.4V), 1V ≤ VVPERI < 5.5V 14.17 Pull-down current at pin RESQ2 14.
ATA6264 [Preliminary] 16. Watchdog Function To verify the proper function of the microcontroller, watchdog logic is included. As the ATA6264 is powered up, the RESQ2 signal stays low until the first valid watchdog trigger is detected. Features: • Watchdog trigger has to be done via the serial interface • In case of a watchdog-trigger mismatch, the ATA6264 is set into its default state (latches, MISO status, etc.) and RESQ is set to low.
Requirements for successful trigger: • Minimum one valid different serial interface command between two trigger watchdog commands is necessary. Exception: First trigger watchdog command need not be preceded by a different serial interface command. • Cyclic repetition for the trigger watchdog command within ±25% tolerance is necessary. Incorrect trigger causes RESQ active.
ATA6264 [Preliminary] The trigger watchdog cycle can be set to the following retrigger times: • 4 ms • 8 ms • 16 ms (default) • 32 ms • 64 ms • 128 ms Cyclic phase: Between two trigger commands a different SPI command must be seen by the SPI decoder Figure 16-3.
Figure 16-4.
ATA6264 [Preliminary] Configuration of watchdog trigger: For the configuration of the watchdog prescaler, a special serial interface command is necessary. MSByte LSByte Description 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Hex Code Configure prescaler 0 1 1 0 0 0 0 0 1 1 1 1 0 a b c 60Fx Note: a, b, and c to be set as defined in Table 16-1 Table 16-1.
Necessary for operation: VPERI > Reset threshold, VCORE > Reset threshold Operating conditions of all other supply pins: VK30, VEVZ and VVSAT are within functional range limits, Tj = –40°C to 150°C Other pins: As defined in Section 4. ”Functional Range” on page 8. Table 16-2. Electrical Characteristics – Watchdog Function No. Parameters Test Conditions Pin 15.1 Oscillator frequency 15.2 Power-up extension of RESQ signal RESQ Start of first watchdog trigger 15.3 window after rising edge at RESQ 15.
ATA6264 [Preliminary] Figure 16-5. Watchdog Trigger VCC 5.0V 4.75V t RESQ 15.9 ms 15.2 ms t 15.4 ms 15.8 ms chip internal trigger window 15.3 ms 15.6 ms t Trg Wdg CMD any different serial interface command Trg Wdg CMD re-configure prescaler 15.5 ms Trg Wdg CMD Serial interface communication 15.
17. LIN/ISO 9141 Interfaces The ATA6264 includes two complete ISO 9141 interfaces. Interface #1 is controlled via the pins RxD1 and TxD1, interface #2 is controlled via the pins RxD2 and TxD2. In order to support both ISO9141 and LIN bus requirements, interface #1 can be configured during initial programming. In applications where one or both ISO9141 interfaces are not needed, the output transistors of K1 and K2 may be used as simple low-side transistors, switched on or off by the serial interface.
ATA6264 [Preliminary] Table 17-1. No. Electrical Characteristics – LIN/ISO 9141 Interfaces Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type* –50 –65 µA A General (Valid for All Modes) 16.1 Pull-up current to VPERI at pin TxDx (x = 1, 2) TxDx ITxDx –35 16.2 Kx input receiver low (x = 1, 2) Kx VKx 0 0.4 × VK30 V A 16.3 Kx input receiver high (x = 1, 2) Kx VKx 0.6 × VK30 VK30 V A 16.4 Kx input receiver threshold (x = 1, 2) Kx VKx V A 16.
Table 17-1. No. Electrical Characteristics (Continued)– LIN/ISO 9141 Interfaces Parameters Test Conditions Pin Symbol Min 62.5 Typ. Max. Unit Type* kBd A ISO 9141 Mode Kx fKx Propagation delay TxDx = low to Kx = low (x = 1, 2), measured from TxDx H to L to Kx = 0.9 × VK30 RKx = 510Ω to K30, CKx = 470 pF to GNDB Kx tPDtL 1 µs A Propagation delay TxDx = high to Kx = high (x = 1, 2), measured from TxDx L to H to Kx = 0.
ATA6264 [Preliminary] Table 17-1. No. Electrical Characteristics (Continued)– LIN/ISO 9141 Interfaces Parameters Test Conditions Pin Symbol 16.37 Measured from Propagation delay K1 high to K1 = 0.6 × VK30 to RxD1 = high RxD1 = L to H K1 tPDkH 16.38 Symmetry of transmitter delay tSYM_T1 = tPDtL – tPDtH K1 tSYM_T1 16.39 Symmetry of receiver propagation delay tSYM_R1 = tPDkL – tPDkH K1 tSYM_R1 16.40 Kx output voltage drop IKx = 40 mA IKx = 20 mA Kx 16.
18. Voltage/Current Sources (IASGx Sources) For a variable resistance measurement and especially for buckle-switch detection, five constant voltage sources, switchable between two different voltages (V1 and V2) are implemented. The current delivered by these voltage sources is mirrored by a factor of 1 / 10 or 1 / 15 to the pin ISENS and causes a voltage drop at the external resistor connected to this pin. This voltage drop can be measured at pin UZP by choosing the corresponding AMUX command.
ATA6264 [Preliminary] Figure 18-1.
Table 18-1. Electrical Characteristics – Voltage/Current Sources (IASGx Sources) No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type* 17.1 Output voltage (V1) (x = 1 to 5), –40 mA < IIASGx < –0.5 mA VISENS = 0.96 × VVPERI IASGx V1IASGx –6% 10 +6% V A 17.2 Output voltage (V2) (x = 1 to 5), –40 mA < IIASGx < –0.5 mA VISENS = 0.96 × VVPERI IASGx switched to 5V VEVZ > 11V IASGx V2IASGx –6% 5 +6% V A 17.2a Output voltage (V2) (x = 1 to 5), –25 mA < IIASGx < –0.
ATA6264 [Preliminary] Table 18-1. Electrical Characteristics (Continued)– Voltage/Current Sources (IASGx Sources) No. Parameters Test Conditions Pin Symbol Min (x = 1 to 5), (Y = 1, 2) (VISENS ≤ VVPERI regulator active) ISENSE VISENSE 17.12 ISENS leakage current VISENS = 0V to 0.96 × VVPERI ISENSE 17.13 IASGx leakage current (x = 1 to 5) IASGx channel deactivated, 0V < VIASGx < VEVZ IASGx Typ. Max. Unit Type* 0.96 × VVPERI 1.05 × VVPERI V A IISENSE –1.6 +1.6 µA A IIASGx –1.
19. AMUX (Analog Multiplexer for Voltage Measurements) Various voltages and the chip temperature inside of the ATA6264 can be measured at the analog measurement output UZP. Different voltage dividers ensure that the values of the measured voltages at UZP are in the range of 0V to VPERI. To select a specific measurement, a serial interface command has to be sent to the ATA6264. For the list of measurable voltages and temperatures, refer to Section 22. ”Serial Interface Commands” on page 68.
ATA6264 [Preliminary] Table 19-1. Electrical Characteristics – AMUX (Analog Multiplexer for Voltage Measurements) No. Parameters Test Conditions Pin Symbol Min 18.1 Output offset error Has to be calculated from the values of the differential measurement UZP VUZPoffset –5 18.2 Ratio VK15 / VUZP For VVPERI = 5V (1.5V to 3V) For VVPERI = 5V (> 3V to 25V) UZP Ratio 6.05 ± 4% 6.05 ± 2.3% A A 18.2a Ratio VK15 / VUZP For VVPERI = 3.3V (1.5V to 3V) For VVPERI = 3.
Table 19-1. No. Electrical Characteristics (Continued)– AMUX (Analog Multiplexer for Voltage Measurements) Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type* 18.15 Ratio VUSP / VUZP For VVPERI = 5V (1.5V to 3V) For VVPERI = 5V (> 3V to 25V) UZP Ratio 6.02 ± 6% 6.02 ± 2.3% A A 18.15a Ratio VUSP / VUZP For VVPERI = 3.3V (1.5V to 3V) For VVPERI = 3.3V (> 3V to 25V) UZP Ratio 9.07 ± 6% 9.07 ± 2.3% A A 18.16 Ratio VVINT / VUZP UZP Ratio 3.99 ± 2.6% A Voltage 0.
ATA6264 [Preliminary] 20. UZP Buffer The pin UZP is an analog output pin of the ATA6264. The UZP buffer is realized as a tristate output with the ability to drive to VPERI as well as to GNDA. The selected measurement result is given to the pin UZP as long as no new measurement is selected or the tristate command has been sent. Driver capability is typically 4 mA. Figure 20-1.
Table 20-1. Electrical Characteristics – UZP Buffer No. Parameters Test Conditions Pin Symbol Min Output current high side, 19.1 driving current with measurement activated VUZP = 0V, UZP connected to GND UZP IUZP Output current low side, V = VVPERI 19.2 sink current with measurement UZP UZP connected to GND activated UZP IUZP Typ. Max. Unit Type* –8 –2 mA A 2 8 mA A 19.
ATA6264 [Preliminary] 21. Chip Temperature Measurement A serial interface command allows measuring a chip-temperature–dependent voltage which is generated by two diodes connected in series. Three 2-diode sensors are connected in parallel and located in the following blocks: VPERI, VCORE, and VSAT. The diodes are supplied by a temperature-constant current source, the voltage drop of the diodes is switched via AMUX to pin UZP.
22. Serial Interface Commands 22.1 Overview All functions of the ATA6264 are triggered by 16-bit serial interface commands. Some of these commands are latched because their actions have to continue for a longer time. Other commands have to be executed as long as no other command is received via the serial interface. The pin SSQ (low active) is used to select the ATA6264.
ATA6264 [Preliminary] Table 22-1. Electrical Characteristics (Continued)– Serial Interface Commands No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type* 21.7 Time from SSQ falling edge to MISO MSB valid (2) MISO tMISOMSB_V 0 400 ns A 21.8 Time from SCLK rising edge to MISO valid (2) MISO tMISOV 0 40 ns A 21.9 Time from SSQ rising edge to MISO tristate condition (2) MISO tMISOhiZ 0 40 ns A 21.10 No-data time between serial interface commands tnodata 1.
Figure 22-1. Timing Serial Interface 10. (> 1.5 µs) SSQ 4. (< 20 ns) #1 SCLK 5. (> 20 ns) MOSI not defined 22.2 2. (> 100 ns) 1. (> 100 ns) #16 6. (> 20 ns) MSB LSB 9. (< 40 ns) 8. (< 40 ns) 7. (< 400 ns) MISO 3. (< 20 ns) 14. (> 40 ns) not defined MSB LSB not defined Set Commands After a reset due to the watchdog or undervoltage, all internal control registers and decoded signals are set to their default values. Table 22-2.
ATA6264 [Preliminary] Table 22-3. Key Latch Commands MSByte LSByte Description 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Hex Code Key latch set 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFF Key latch reset (default) 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 3000 Table 22-4.
Table 22-6. Initial Programming (IP Command) MSByte LSByte Description 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Hex Code Write data to IP register 1 0 1 0 1 0 0 1 x x x x x x x x A9xx The initial programming command is only available in Test mode. For more information about the programming flow and the register contents, see Section 5.2 ”Initial Programming of the ATA6264” on page 11. Table 22-7.
ATA6264 [Preliminary] Table 22-7. Diagnosis Commands (Continued) MSByte LSByte Description 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Hex Code Switch VVINT via AMUX to UZP 1 1 0 0 1 0 1 0 1 1 1 0 0 0 1 0 CAE2 Switch voltage at chip-temperature sensor via AMUX to UZP 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 0 CAE4(1) Note: 1.
22.3 Serial Interface Status Register For all serial interface commands except the test-mode commands (55AAh, AA55h, 5500h), the ATA6264 status is available at the MISO line. For the status register a 16-bit structure is used, one bit for each information. Table 22-10. Status Register Byte A Byte B MSBit a7 LSBit MSBit a6 a5 a4 a3 a2 a1 a0 b7 LSBit b6 b5 b4 b3 b2 b1 b0 Table 22-11.
ATA6264 [Preliminary] The overtemperature bits a5, a6 and a7 are latched when overtemperature is detected. These bits will be reset with the next SPI command, unless overtemperature still exists. In the case of a reset, bits b4 and b5 are not set to their default state. These bits show the status before reset so that the microcontroller can detect whether or not the ATA6264 is in power-up state. Table 22-12.
23. Test Mode For better testability of the ATA6264, a test mode is implemented. This mode is activated if the pins RESQ and TxD1 are connected to GND, the pins RESQ2 and TxD2 are connected to VPERI, and the serial interface command 5A5Ah is sent to the ATA6264. Test mode is latched as long as the ATA6264 is powered (VK30 > 4.2V to 5V and VK15 > 3V to 4V). In Test mode the watchdog is disabled, which means that RESQ and RESQ2 depend on the voltage levels of the pins VCORE, VPERI and EVZ.
ATA6264 [Preliminary] 24. Application Circuits Figure 24-1.
K2 KL30 K1 KL30 CP-OUT UZP RESQ2 RxD2 TxD2 TxD2 SSQ SSQ Cp GNDB GNDA GNDD IREF SVCORE VCORE SVSAT VSAT VPERI CP-OUT SVPERI COMCOO COMCOI COMSATI COMSATO EVZ GEVZ OCEVZ FBEVZ COMEVZ USP K30 K15 SCLK SCLK ISENS ATA6264 IASG5 IASG4 IASG3 IASG2 IASG1 K2 K1 UZP TxD1 RxD1 RxD1 TxD1 MOSI MOSI RxD2 MISO MISO VINT RESQ RESQ RESQ2 VCORE (5V) VSAT (9V) VPERI (5V) EVZ (33V) KL15 Figure 24-2.
ATA6264 [Preliminary] 25. Ordering Information Extended Type Number Package Remarks ATA6264-ALTW P-TQFP44 Tray ATA6264-ALQW P-TQFP44 Taped and reeled 26. Package Information Package: P-TQFP 44 (acc. JEDEC OUTLINE No. MO-112) Dimensions in mm 12±0.2 10±0.05 8 34 33 11 23 0.8 1 12 22 0.1±0.05 +0.08 0.37-0.07 Drawing-No.: 6.543-5131.01-4 0.6±0.15 44 0.2 1.4±0.05 technical drawings according to DIN specifications Issue: 1; 11.05.
27. Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 1 1.1 Block Description .................................................................................................3 1.1.1 Integrated Boost Converter EVZ .....................................................................3 1.1.
ATA6264 [Preliminary] 17 LIN/ISO 9141 Interfaces ......................................................................... 54 18 Voltage/Current Sources (IASGx Sources) ......................................... 58 19 AMUX (Analog Multiplexer for Voltage Measurements) ..................... 62 20 UZP Buffer .............................................................................................. 65 21 Chip Temperature Measurement ..........................................................
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