Datasheet

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Features

• High-performance, Low-power AVR

8-bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

• Nonvolatile Program and Data Memories

– 16K Bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 1K Byte Internal SRAM

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels in TQFP Package Only

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad MLF

• Operating Voltages

– 2.7 - 5.5V for ATmega16L

– 4.5 - 5.5V for ATmega16

• Speed Grades

– 0 - 8 MHz for ATmega16L

– 0 - 16 MHz for ATmega16

• Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L

– Active: 1.1 mA

– Idle Mode: 0.35 mA

– Power-down Mode: < 1 µA

8-bit

Microcontroller

with 16K Bytes

In-System

Programmable

Flash

ATmega16

ATmega16L

Preliminary

Summary

Rev. 2466FS–AVR–02/03

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Summary of content (20 pages)

PAGE 1
Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 16K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Program
PAGE 2
Pin Configurations Figure 1.
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ATmega16(L) Overview The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2.
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The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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ATmega16(L) Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
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Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $3F ($5F) SREG I T H S V N Z C 7 $3E ($5E) SPH – – – – – SP10 SP9 SP8 10 SP4 SP3 SP2 SP1 SP0 10 – – – IVSEL IVCE 46, 66 $3D ($5D) SPL $3C ($5C) OCR0 $3B ($5B) GICR INT1 INT0 82 INT2 $3A ($5A) GIFR INTF1 INTF0 INTF2 – – – – – 67 $39 ($59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 82, 113, 131 $38 ($58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B T
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ATmega16(L) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $01 ($21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 180 $00 ($20) TWBR Notes: Two-wire Serial Interface Bit Rate Register 179 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3.
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Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd
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ATmega16(L) Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers 1 Rd, Rr Copy Register Word Rd ← Rr Rd+1:Rd ← Rr+1:Rr None MOVW None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc.
PAGE 10
Mnemonics Operands CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK 10 Flags Description Operation Clear Half Carry Flag in SREG H←0 H No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr.
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ATmega16(L) Ordering Information Speed (MHz) Power Supply 8 2.7 - 5.5V 16 4.5 - 5.5V Ordering Code Package ATmega16L-8AC ATmega16L-8PC ATmega16L-8MC 44A 40P6 44M1 Operation Range Commercial (0oC to 70oC) ATmega16L-8AI ATmega16L-8PI ATmega16L-8MI 44A 40P6 44M1 Industrial (-40oC to 85oC) ATmega16-16AC ATmega16-16PC ATmega16-16MI 44A 40P6 44M1 Commercial (0oC to 70oC) ATmega16-16AI ATmega16-16PI ATmega16-16MC 44A 40P6 44M1 Industrial (-40oC to 85oC) Package Type 44A 44-lead, Thin (1.
PAGE 12
Packaging Information 44A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.
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ATmega16(L) 40P6 D PIN 1 E1 A SEATING PLANE A1 L B1 B e E COMMON DIMENSIONS (Unit of Measure = mm) 0º ~ 15º REF C SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX NOTE A – – 4.826 A1 0.381 – – D 52.070 – 52.578 Note 2 E 15.240 – 15.875 E1 13.462 – 13.970 Note 2 B 0.356 – 0.559 B1 1.041 – 1.
PAGE 14
44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A L Pin #1 Corner D2 SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) E2 SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 b 0.25 REF 0.18 D e b D2 E2 L 0.30 5.20 5.40 7.00 BSC 5.00 e Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-1. 0.23 7.00 BSC 5.00 E BOTTOM VIEW NOTE 5.20 5.40 0.50 BSC 0.35 0.55 0.
PAGE 15
ATmega16(L) Erratas The revision letter in this section refers to the revision of the ATmega16 device. ATmega16(L) Rev. G. There are no errata for this revision of ATmega16. ATmega16(L) Rev. H. There are no errata for this revision of ATmega16.
PAGE 16
Data Sheet Change Log for ATmega16 This section contains a log on the changes made to the data sheet for ATmega16. Changes from Rev. 2466B-09/01 to Rev. 2466C-03/02 All page numbers refer to this document. 1. Updated typical EEPROM programming time, Table 1 on page 18. 2. Updated typical start-up time in the following tables: Table 3 on page 23, Table 5 on page 25, Table 6 on page 26, Table 8 on page 27, Table 9 on page 27, and Table 10 on page 28. 3.
PAGE 17
ATmega16(L) Changes from Rev. 2466C-03/02 to Rev. 2466D-09/02 All page numbers refer to this document. 1. Changed all Flash write/erase cycles from 1,000 to 10,000. 2. Updated the following tables: Table 4 on page 24, Table 15 on page 36, Table 42 on page 82, Table 45 on page 109, Table 46 on page 109, Table 59 on page 141, Table 67 on page 166, Table 90 on page 234, Table 102 on page 258, “DC Characteristics” on page 290, Table 119 on page 292, Table 121 on page 294, and Table 122 on page 296. 3.
PAGE 18
15. Added note about Differential Mode with Auto Triggering in “Prescaling and Conversion Timing” on page 206. 16. Added updated “Packaging Information” on page 12.
PAGE 19
ATmega16(L) 19 2466FS–AVR–02/03
PAGE 20
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