Features • • • • • • • • • • • High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller Advanced RISC Architecture – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments – 64K/128K/256KBytes of In-System Self-Programmable Flash – 4Kbytes EEPROM – 8Kbytes Internal SRAM – Write/Erase Cycles:10,000 Flash/100,000 EE
ATmega640/1280/1281/2560/2561 1.
ATmega640/1280/1281/2560/2561 Figure 1-2. CBGA-pinout ATmega640/1280/2560 Top view 1 2 3 4 5 6 Bottom view 7 8 9 10 10 9 8 7 6 5 4 3 2 1 A A B B C C D D E E F F G G H H J J K K Table 1-1.
ATmega640/1280/1281/2560/2561 (OC0B) PG5 1 (RXD0/PCINT8/PDI) PE0 2 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout ATmega1281/2561 64 Figure 1-3.
ATmega640/1280/1281/2560/2561 2. Overview The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PF7..0 PK7..0 PORT F (8) PORT K (8) PJ7..0 PE7..
ATmega640/1280/1281/2560/2561 The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega640/1280/1281/2560/2561 2.2 Comparison Between ATmega1281/2561 and ATmega640/1280/2560 Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2-1 summarizes the different configurations for the six devices. Table 2-1.
ATmega640/1280/1281/2560/2561 resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as listed on page 82. 2.3.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability.
ATmega640/1280/1281/2560/2561 resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 92. 2.3.11 Port J (PJ7..PJ0) Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability.
ATmega640/1280/1281/2560/2561 2.3.17 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.18 AREF This is the analog reference pin for the A/D Converter.
ATmega640/1280/1281/2560/2561 3. Resources A comprehensive set of development tools and application notes, and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
ATmega640/1280/1281/2560/2561 7. AVR CPU Core 7.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 7.2 Architectural Overview Figure 7-1.
ATmega640/1280/1281/2560/2561 The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
ATmega640/1280/1281/2560/2561 7.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the “Instruction Set Summary” on page 416.
ATmega640/1280/1281/2560/2561 • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Summary” on page 416 for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Summary” on page 416 for detailed information. 7.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega640/1280/1281/2560/2561 Figure 7-3. The X-, Y-, and Z-registers 15 X-register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the “Instruction Set Summary” on page 416 for details). 7.
ATmega640/1280/1281/2560/2561 7.6.1 RAMPZ – Extended Z-pointer Register for ELPM/SPM Bit 7 6 5 4 3 2 1 0 0x3B (0x5B) RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-4. Note that LPM is not affected by the RAMPZ setting. Figure 7-4.
ATmega640/1280/1281/2560/2561 Figure 7-6. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-7.
ATmega640/1280/1281/2560/2561 There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared.
ATmega640/1280/1281/2560/2561 Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 7.8.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum.
ATmega640/1280/1281/2560/2561 8. AVR Memories This section describes the different memories in the ATmega640/1280/1281/2560/2561. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega640/1280/1281/2560/2561 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 8.
ATmega640/1280/1281/2560/2561 An optional external data SRAM can be used with the ATmega640/1280/1281/2560/2561. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the lowest 4,608/8,704 bytes, so when using 64Kbytes (65,536 bytes) of External Memory, 60,478/56,832 Bytes of External Memory are available.
ATmega640/1280/1281/2560/2561 Figure 8-2. Data Memory Map Address (HEX) 0 - 1F 32 Registers 20 - 5F 64 I/O Registers 60 - 1FF 416 External I/O Registers 200 Internal SRAM (8192 × 8) 21FF 2200 External SRAM (0 - 64K × 8) FFFF 8.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 8-3. Figure 8-3.
ATmega640/1280/1281/2560/2561 8.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space, see “Register Description” on page 35. The write access time for the EEPROM is given in Table 8-1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down.
ATmega640/1280/1281/2560/2561 Assembly Code Example(1) EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example(1) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1
ATmega640/1280/1281/2560/2561 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega640/1280/1281/2560/2561 8.4 I/O Memory The I/O space definition of the ATmega640/1280/1281/2560/2561 is shown in “Register Summary” on page 411. All ATmega640/1280/1281/2560/2561 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space.
ATmega640/1280/1281/2560/2561 9. External Memory Interface With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCDdisplay, A/D, and D/A. The main features are: • • • • 9.
ATmega640/1280/1281/2560/2561 9.1.1 Using the External Memory Interface The interface consists of: • AD7:0: Multiplexed low-order address bus and data bus • A15:8: High-order address bus (configurable number of bits) • ALE: Address latch enable • RD: Read strobe • WR: Write strobe The control bits for the External Memory Interface are located in two registers, the External Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB.
ATmega640/1280/1281/2560/2561 Figure 9-2. External SRAM Connected to the AVR AVR SRAM D[7:0] AD7:0 D ALE G A15:8 9.1.3 Q A[7:0] A[15:8] RD RD WR WR Pull-up and Bus-keeper The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep. The XMEM interface also provides a bus-keeper on the AD7:0 lines.
ATmega640/1280/1281/2560/2561 Figure 9-3. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)(1) T1 T2 T3 T4 System Clock (CLKCPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev. data Address Address Data Write XX WR XXXXX Data XXXXXXXX Read Data RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
ATmega640/1280/1281/2560/2561 Figure 9-5. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1) T1 T2 T3 T4 T5 T6 System Clock (CLKCPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev. data Address Data Write XX WR Address Read Data Data RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
ATmega640/1280/1281/2560/2561 the Application software, the external 32Kbytes memory will appear as one linear 32Kbytes address space from 0x2200 to 0xA1FF. This is illustrated in Figure 9-7. Figure 9-7. Address Map with 32Kbytes External Memory AVR Memory Map 0x0000 External 32K SRAM 0x0000 Internal Memory 0x21FF 0x2200 0x7FFF 0x8000 External 0x7FFF Memory 0x90FF 0x9100 9.1.
ATmega640/1280/1281/2560/2561 Assembly Code Example(1) ; ; ; ; ; OFFSET is defined to 0x4000 to ensure external memory access Configure Port C (address high byte) to output 0x00 when the pins are released for normal Port Pin operation ldi r16, 0xFF out DDRC, r16 ldi r16, 0x00 out PORTC, r16 ; release PC7:6 ldi r16, (1<
ATmega640/1280/1281/2560/2561 9.2 9.2.1 9.2.1.
ATmega640/1280/1281/2560/2561 Table 9-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time 0 0 3.4ms Erase and Write in one operation (Atomic Operation) 0 1 1.8ms Erase only 1 0 1.8ms Write only 1 1 – Reserved for future use Operation • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.
ATmega640/1280/1281/2560/2561 • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
ATmega640/1280/1281/2560/2561 Figure 9-1 on page 28. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address space is treated as one sector. When the entire SRAM address space is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits. Table 9-2.
ATmega640/1280/1281/2560/2561 • Bit 7– XMBK: External Memory Bus-keeper Enable Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tristated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is one.
ATmega640/1280/1281/2560/2561 10. System Clock and Clock Options This section describes the clock options for the AVR microcontroller. 10.1 Overview Figure 10-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 52. The clock systems are detailed below.
ATmega640/1280/1281/2560/2561 10.2.2 I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
ATmega640/1280/1281/2560/2561 10.3.1 Default Clock Source The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that all users can make their desired clock source setting using any available programming interface. 10.3.
ATmega640/1280/1281/2560/2561 C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 10-3. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 10-2.
ATmega640/1280/1281/2560/2561 Table 10-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued) Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1:0 Ceramic resonator, fast rising power 1K CK 14CK + 4.1ms(2) 0 11 Ceramic resonator, slowly rising power 1K CK 14CK + 65ms(2) 1 00 Crystal Oscillator, BOD enabled 16K CK 14CK Crystal Oscillator, fast rising power 16K CK 14CK + 4.
ATmega640/1280/1281/2560/2561 Table 10-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1:0 Ceramic resonator, fast rising power 258 CK 14CK + 4.1ms(1) 0 00 Ceramic resonator, slowly rising power 258 CK 14CK + 65ms(1) 0 01 Ceramic resonator, BOD enabled 1K CK 14CK(2) 0 10 Ceramic resonator, fast rising power 1K CK 14CK + 4.
ATmega640/1280/1281/2560/2561 The capacitance (Ce + Ci) needed at each XTAL/TOSC pin can be calculated by using: Ce + Ci = 2 CL – C s where: Ce - is optional external capacitors as described in Figure 10-3 on page 46. Ci - is the pin capacitance in Table 10-7 on page 45. CL - is the load capacitance for a 32.768kHz crystal specified by the crystal vendor. CS - is the total stray capacitance for one XTAL/TOSC pin.
ATmega640/1280/1281/2560/2561 10.7 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 31-1 on page 371 and “Internal Oscillator Speed” on page 404 for more details. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 49 for more details.
ATmega640/1280/1281/2560/2561 When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 10-12. Table 10-12. Start-up Times for the 128kHz Internal Oscillator Power Conditions Start-up Time from Powerdown and Power-save Additional Delay from Reset SUT1:0 BOD enabled 6CK 14CK 00 Fast rising power 6CK 14CK + 4ms 01 Slowly rising power 6CK 14CK + 64ms 10 Reserved 10.
ATmega640/1280/1281/2560/2561 Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” for details. 10.10 Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system.
ATmega640/1280/1281/2560/2561 10.13 Register Description 10.13.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
ATmega640/1280/1281/2560/2561 source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 10-15.
ATmega640/1280/1281/2560/2561 11. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 11.1 Sleep Modes Figure 10-1 on page 40 presents the different clock systems in the ATmega640/1280/1281/2560/2561, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
ATmega640/1280/1281/2560/2561 Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode.
ATmega640/1280/1281/2560/2561 stopped during sleep. If the Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for the Timer/Counter2. 11.6 Standby Mode When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode.
ATmega640/1280/1281/2560/2561 to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “AC – Analog Comparator” on page 271 for details on how to configure the Analog Comparator. 11.9.3 Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off.
ATmega640/1280/1281/2560/2561 There are three alternative ways to disable the OCD system: • Disable the OCDEN Fuse • Disable the JTAGEN Fuse • Write one to the JTD bit in MCUCR 11.10 Register Description 11.10.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management.
ATmega640/1280/1281/2560/2561 • Bit 6 - PRTIM2: Power Reduction Timer/Counter2 Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown. • Bit 5 - PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.
ATmega640/1280/1281/2560/2561 • Bit 2 - PRUSART3: Power Reduction USART3 Writing a logic one to this bit shuts down the USART3 by stopping the clock to the module. When waking up the USART3 again, the USART3 should be re initialized to ensure proper operation. • Bit 1 - PRUSART2: Power Reduction USART2 Writing a logic one to this bit shuts down the USART2 by stopping the clock to the module. When waking up the USART2 again, the USART2 should be re initialized to ensure proper operation.
ATmega640/1280/1281/2560/2561 12. System Control and Reset 12.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega640/1280/1281/2560/2561 Figure 12-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 12.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “System and Reset Characteristics” on page 372.
ATmega640/1280/1281/2560/2561 Figure 12-3. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET 12.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see “System and Reset Characteristics” on page 372) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
ATmega640/1280/1281/2560/2561 Figure 12-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNAL RESET 12.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. See “Watchdog Timer” on page 55. for details on operation of the Watchdog Timer. Figure 12-6. Watchdog Reset During Operation CC CK 12.
ATmega640/1280/1281/2560/2561 ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 12.4 12.4.
ATmega640/1280/1281/2560/2561 tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows: 1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation.
ATmega640/1280/1281/2560/2561 Assembly Code Example(1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<
ATmega640/1280/1281/2560/2561 Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence in r16, WDTCSR ori r16, (1<
ATmega640/1280/1281/2560/2561 12.5 12.5.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset.
ATmega640/1280/1281/2560/2561 • Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF.
ATmega640/1280/1281/2560/2561 . Table 12-2. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16ms 0 0 0 1 4K (4096) cycles 32ms 0 0 1 0 8K (8192) cycles 64ms 0 0 1 1 16K (16384) cycles 0.125s 0 1 0 0 32K (32768) cycles 0.25s 0 1 0 1 64K (65536) cycles 0.5s 0 1 1 0 128K (131072) cycles 1.0s 0 1 1 1 256K (262144) cycles 2.0s 1 0 0 0 512K (524288) cycles 4.
ATmega640/1280/1281/2560/2561 13. I/O-Ports 13.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega640/1280/1281/2560/2561 Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 13-2.
ATmega640/1280/1281/2560/2561 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 13.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 13.2.
ATmega640/1280/1281/2560/2561 Figure 13-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATmega640/1280/1281/2560/2561 The following code example shows how to set port B pins 0 and 1 high, pins 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
ATmega640/1280/1281/2560/2561 above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 13.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
ATmega640/1280/1281/2560/2561 Figure 13-5.
ATmega640/1280/1281/2560/2561 Table 13-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 13-5 on page 76 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 13-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATmega640/1280/1281/2560/2561 13.3.1 Alternate Functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. Table 13-3.
ATmega640/1280/1281/2560/2561 Table 13-5. 13.3.
ATmega640/1280/1281/2560/2561 PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt source. • OC1B/PCINT6, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT6, Pin Change Interrupt source 6: The PB6 pin can serve as an external interrupt source.
ATmega640/1280/1281/2560/2561 Table 13-7 and Table 13-8 relate the alternate functions of Port B to the overriding signals shown in Figure 13-5 on page 76. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source. Table 13-7.
ATmega640/1280/1281/2560/2561 13.3.3 Alternate Functions of Port C The Port C alternate function is as follows: Table 13-9.
ATmega640/1280/1281/2560/2561 Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0 13.3.
ATmega640/1280/1281/2560/2561 • INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. • INT2/RXD1 – Port D, Bit 2 INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU. RXD1, Receive Data (Data input pin for the USART1).
ATmega640/1280/1281/2560/2561 Table 13-13. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PD7/T0 PD6/T1 PD5/XCK1 PD4/ICP1 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 XCK1 OUTPUT ENABLE 0 DDOV 0 0 1 0 PVOE 0 0 XCK1 OUTPUT ENABLE 0 PVOV 0 0 XCK1 OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI T0 INPUT T1 INPUT XCK1 INPUT ICP1 INPUT AIO – – – – Table 13-14.
ATmega640/1280/1281/2560/2561 13.3.5 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 13-15. Table 13-15.
ATmega640/1280/1281/2560/2561 • INT4/OC3B – Port E, Bit 4 INT4, External Interrupt source 4: The PE4 pin can serve as an External Interrupt source. OC3B, Output Compare Match B output: The PE4 pin can serve as an External output for the Timer/Counter3 Output Compare B. The pin has to be configured as an output (DDE4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWM mode timer function. • AIN1/OC3A – Port E, Bit 3 AIN1 – Analog Comparator Negative input.
ATmega640/1280/1281/2560/2561 Table 13-16. Overriding Signals for Alternate Functions PE7:PE4 Signal Name PE7/INT7/ICP3 PE6/INT6/T3 PE5/INT5/OC3C PE4/INT4/OC3B PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 OC3C ENABLE OC3B ENABLE PVOV 0 0 OC3C OC3B DIEOE INT7 ENABLE INT6 ENABLE INT5 ENABLE INT4 ENABLE DIEOV 1 1 1 1 DI INT7 INPUT/ICP3 INPUT INT7 INPUT/T3 INPUT INT5 INPUT INT4 INPUT AIO – – – – Table 13-17.
ATmega640/1280/1281/2560/2561 13.3.6 Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in Table 13-18. If some Port F pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. Table 13-18.
ATmega640/1280/1281/2560/2561 Table 13-19. Overriding Signals for Alternate Functions in PF7:PF4 Signal Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV 1 0 1 1 DDOE JTAGEN JTAGEN JTAGEN JTAGEN DDOV 0 SHIFT_IR + SHIFT_DR 0 0 PVOE 0 JTAGEN 0 0 PVOV 0 TDO 0 0 DIEOE JTAGEN JTAGEN JTAGEN JTAGEN DIEOV 0 0 0 0 DI – – – – AIO TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5 INPUT TCK/ADC4 INPUT Table 13-20.
ATmega640/1280/1281/2560/2561 • OC0B – Port G, Bit 5 OC0B, Output Compare match B output: The PG5 pin can serve as an external output for the TImer/Counter0 Output Compare. The pin has to be configured as an output (DDG5 set) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function.
ATmega640/1280/1281/2560/2561 Table 13-23. Overriding Signals for Alternate Functions in PG3:PG0 13.3.
ATmega640/1280/1281/2560/2561 • OC4B – Port H, Bit 4 OC4B, Output Compare Match B output: The PH4 pin can serve as an external output for the Timer/Counter2 Output Compare B. The pin has to be configured as an output (DDH4 set) to serve this function. The OC4B pin is also the output pin for the PWM mode timer function. • OC4A – Port H, Bit 3 OC4C, Output Compare Match A output: The PH3 pin can serve as an external output for the Timer/Counter4 Output Compare A.
ATmega640/1280/1281/2560/2561 Table 13-26. Overriding Signals for Alternate Functions in PH3:PH0 13.3.
ATmega640/1280/1281/2560/2561 • TXD3/PCINT10 - Port J, Bit 1 TXD3, USART3 Transmit pin. PCINT10, Pin Change Interrupt Source 10. The PJ1 pin can serve as External Interrupt Sources. • RXD3/PCINT9 - Port J, Bit 0 RXD3, USART3 Receive pin. Receive Data (Data input pin for the USART3). When the USART3 Receiver is enabled, this pin is configured as an input regardless of the value of DDJ0. When the USART3 forces this pin to be an input, a logical one in PORTJ0 will turn on the internal pull-up.
ATmega640/1280/1281/2560/2561 Table 13-28. Overriding Signals for Alternate Functions in PJ7:PJ4 Signal Name PJ7 PJ6/ PCINT15 PJ5/ PCINT14 PJ4/ PCINT13 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE - - - - DIEOE 0 PCINT15·PCIE1 PCINT14·PCIE1 PCINT13·PCIE1 DIEOV 0 1 1 1 DI 0 PCINT15 INPUT PCINT14 INPUT PCINT13 INPUT AIO - - - - Table 13-29. Overriding Signals for Alternate Functions in PJ3:PJ0 13.3.
ATmega640/1280/1281/2560/2561 Table 13-30.
ATmega640/1280/1281/2560/2561 Table 13-32. Overriding Signals for Alternate Functions in PK3:PK0 13.3.
ATmega640/1280/1281/2560/2561 • T5 – Port L, Bit 2 T5, Timer/Counter5 counter source. • ICP5 – Port L, Bit 1 ICP5, Input Capture Pin 5: The PL1 pin can serve as an Input Capture pin for Timer/Counter5. • ICP4 – Port L, Bit 0 ICP4, Input Capture Pin 4: The PL0 pin can serve as an Input Capture pin for Timer/Counter4. Table 13-34 and Table 13-35 relates the alternate functions of Port L to the overriding signals shown in Figure 13-5 on page 76. Table 13-34.
ATmega640/1280/1281/2560/2561 13.4 13.4.1 Register Description for I/O-Ports MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the I/O ports pull-up resistors are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-up resistor ({DDxn, PORTxn} = 0b01).
ATmega640/1280/1281/2560/2561 13.4.8 PORTC – Port C Data Register Bit 13.4.9 7 6 5 4 3 2 1 0 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRC – Port C Data Direction Register Bit 13.4.
ATmega640/1280/1281/2560/2561 13.4.16 PINE – Port E Input Pins Address Bit 7 6 5 4 3 2 1 0 PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 0x0C (0x2C) 13.4.17 PORTF – Port F Data Register Bit 13.4.
ATmega640/1280/1281/2560/2561 13.4.24 DDRH – Port H Data Direction Register Bit 7 6 5 4 3 2 1 0 DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x101) 13.4.25 PINH – Port H Input Pins Address Bit 7 6 5 4 3 2 1 0 PINH5 PINH5 PINH5 PINH4 PINH3 PINGH PINH1 PINH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A (0x100) 13.4.
ATmega640/1280/1281/2560/2561 13.4.32 PORTL – Port L Data Register Bit 7 6 5 4 3 2 1 0 PORTL7 PORTL6 PORTL5 PORTL4 PORTL3 PORTL2 PORTL1 PORTL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x10B) 13.4.33 DDRL – Port L Data Direction Register Bit 7 6 5 4 3 2 1 0 DDL7 DDL6 DDL5 DDL4 DDL3 DDL2 DDL1 DDL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x10A) 13.4.
ATmega640/1280/1281/2560/2561 14. Interrupts This section describes the specifics of the interrupt handling as performed in ATmega640/1280/1281/2560/2561. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 18. 14.1 Interrupt Vectors in ATmega640/1280/1281/2560/2561 Table 14-1. Reset and Interrupt Vectors Vector No.
ATmega640/1280/1281/2560/2561 Table 14-1. Vector No.
ATmega640/1280/1281/2560/2561 14.2 Reset and Interrupt Vector placement Table 14-2 shows Reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.
ATmega640/1280/1281/2560/2561 0x0040 jmp TIM3_COMPA ; Timer3 CompareA Handler 0x0042 jmp TIM3_COMPB ; Timer3 CompareB Handler 0x0044 jmp TIM3_COMPC ; Timer3 CompareC Handler 0x0046 jmp TIM3_OVF ; Timer3 Overflow Handler 0x0048 jmp USART1_RXC ; USART1 RX Complete Handler 0x004A jmp USART1_UDRE ; USART1,UDR Empty Handler 0x004C jmp USART1_TXC ; USART1 TX Complete Handler 0x004E jmp TWI ; 2-wire Serial Handler 0x0050 jmp SPM_RDY ; SPM Ready Handler 0x0052 jmp TIM4_CAPT ;
ATmega640/1280/1281/2560/2561 When the BOOTRST Fuse is programmed and the Boot section size set to 8Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org 0x0002 0x00002 jmp EXT_INT0 ; IRQ0 Handler 0x00004 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x00070 jmp USART3_TXC ; USART3 TX Complete Handler ; .
ATmega640/1280/1281/2560/2561 Assembly Code Example Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<
ATmega640/1280/1281/2560/2561 Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
ATmega640/1280/1281/2560/2561 15. External Interrupts The External Interrupts are triggered by the INT7:0 pin or any of the PCINT23:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT23:0 pins are configured as outputs. This feature provides a way of generating a software interrupt.
ATmega640/1280/1281/2560/2561 Figure 15-1. Normal pin change interrupt. pcint_in_(0) pin_lat PCINT(0) D LE pcint_syn 0 Q pcint_setflag PCIF pin_sync x clk PCINT(0) in PCMSK(x) clk clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF 15.2 15.2.1 Register Description EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control.
ATmega640/1280/1281/2560/2561 Interrupt Sense Control(1) Table 15-1. ISCn1 ISCn0 Description 0 0 The low level of INTn generates an interrupt request 0 1 Any edge of INTn generates asynchronously an interrupt request 1 0 The falling edge of INTn generates asynchronously an interrupt request 1 1 The rising edge of INTn generates asynchronously an interrupt request Note: 1. n = 3, 2, 1or 0.
ATmega640/1280/1281/2560/2561 15.2.3 EIMSK – External Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 0x1D (0x3D) INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bits 7:0 – INT7:0: External Interrupt Request 7 - 0 Enable When an INT7:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled.
ATmega640/1280/1281/2560/2561 • Bit 0 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register. 15.2.
ATmega640/1280/1281/2560/2561 • Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8 Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 15.2.
ATmega640/1280/1281/2560/2561 16. 8-bit Timer/Counter0 with PWM 16.1 Features • • • • • • • 16.
ATmega640/1280/1281/2560/2561 uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B).
ATmega640/1280/1281/2560/2561 Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero).
ATmega640/1280/1281/2560/2561 Figure 16-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
ATmega640/1280/1281/2560/2561 generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.
ATmega640/1280/1281/2560/2561 16.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 16-2 on page 129.
ATmega640/1280/1281/2560/2561 Figure 16-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega640/1280/1281/2560/2561 togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 16-6.
ATmega640/1280/1281/2560/2561 16.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5.
ATmega640/1280/1281/2560/2561 generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ----------------N 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
ATmega640/1280/1281/2560/2561 Figure 16-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 16-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 16-10.
ATmega640/1280/1281/2560/2561 16.9 16.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
ATmega640/1280/1281/2560/2561 Table 16-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected WGM02 = 1: Toggle OC0A on Compare Match 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting 1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting Note: 1.
ATmega640/1280/1281/2560/2561 Table 16-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 16-7. COM0B1 COM0B0 Description 0 0 Normal port operation, OC0B disconnected 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting Note: 1.
ATmega640/1280/1281/2560/2561 16.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
ATmega640/1280/1281/2560/2561 Table 16-9. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge 1 1 1 External clock source on T0 pin.
ATmega640/1280/1281/2560/2561 16.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6E) – – – – – OCIE0B OCIE0A TOIE0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK0 • Bits 7:3, 0 – Res: Reserved Bits These bits are reserved bits and will always read as zero.
ATmega640/1280/1281/2560/2561 • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting.
ATmega640/1280/1281/2560/2561 17. 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5) 17.1 Features • • • • • • • • • • • 17.
ATmega640/1280/1281/2560/2561 Figure 17-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic TCLK Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCFnA (Int.Req.) Waveform Generation = OCnA OCRnA OCFnB (Int.Req.) Fixed TOP Values Waveform Generation DATABUS = OCnB OCRnB OCFnC (Int.Req.) Waveform Generation = OCnC OCRnC ( From Analog Comparator Ouput ) ICFn (Int.Req.
ATmega640/1280/1281/2560/2561 See “Output Compare Units” on page 145. The compare match event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (see “AC – Analog Comparator” on page 271).
ATmega640/1280/1281/2560/2561 Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. See “About Code Examples” on page 11. The assembly code example returns the TCNTn value in the r17:r16 register pair.
ATmega640/1280/1281/2560/2561 Assembly Code Example(1) TIM16_ReadTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNTn( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNTn into i */ i = TCNTn; /* Restore global interrupt flag */ SREG = sreg
ATmega640/1280/1281/2560/2561 The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
ATmega640/1280/1281/2560/2561 17.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 17-2 shows a block diagram of the counter and its surroundings. Figure 17-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATmega640/1280/1281/2560/2561 17.6 Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, for the Timer/Counter1 only, via the Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied.
ATmega640/1280/1281/2560/2561 The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL.
ATmega640/1280/1281/2560/2561 Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 17.7 Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match.
ATmega640/1280/1281/2560/2561 The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATmega640/1280/1281/2560/2561 17.8 Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 17-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega640/1280/1281/2560/2561 non-PWM modes refer to Table 17-3 on page 159. For fast PWM mode refer to Table 17-4 on page 159, and for phase correct and phase and frequency correct PWM refer to Table 17-5 on page 160. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 17.
ATmega640/1280/1281/2560/2561 17.9.1 Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero.
ATmega640/1280/1281/2560/2561 TCNTn, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered.
ATmega640/1280/1281/2560/2561 Figure 17-7. Fast PWM Mode, Timing Diagram OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value.
ATmega640/1280/1281/2560/2561 The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ---------------------------------N 1 + TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle.
ATmega640/1280/1281/2560/2561 Figure 17-8. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM.
ATmega640/1280/1281/2560/2561 the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega640/1280/1281/2560/2561 Figure 17-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
ATmega640/1280/1281/2560/2561 The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 17.
ATmega640/1280/1281/2560/2561 Figure 17-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. Figure 17-12.
ATmega640/1280/1281/2560/2561 17.11 Register Description 17.11.1 TCCR1A – Timer/Counter 1 Control Register A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x80) 17.11.
ATmega640/1280/1281/2560/2561 • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 17-2 on page 148. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes.
ATmega640/1280/1281/2560/2561 Table 17-5 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct and frequency correct PWM mode. Table 17-5. COMnA1 COMnB1 COMnC1 COMnA0 COMnB0 COMnC0 Description 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected 0 1 WGM13:0 =9 or 11: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal port operation).
ATmega640/1280/1281/2560/2561 • Bit 6 – ICESn: Input Capture Edge Select This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn).
ATmega640/1280/1281/2560/2561 17.11.10 TCCR3C – Timer/Counter 3 Control Register C Bit 7 6 5 4 3 2 1 FOC3A FOC3B FOC3C – – – – – Read/Write W W W R R R R R Initial Value 0 0 0 0 0 0 0 0 0 (0x92) 0 TCCR3C 17.11.11 TCCR4C – Timer/Counter 4 Control Register C Bit 7 6 5 4 3 2 1 FOC4A FOC4B FOC4C – – – – – Read/Write W W W R R R R R Initial Value 0 0 0 0 0 0 0 0 0 (0xA2) TCCR4C 17.11.
ATmega640/1280/1281/2560/2561 17.11.15 TCNT4H and TCNT4L –Timer/Counter 4 Bit 7 6 5 4 3 (0xA5) TCNT4[15:8] (0xA4) TCNT4[7:0] 2 1 0 TCNT4H TCNT4L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 17.11.
ATmega640/1280/1281/2560/2561 17.11.20 OCR3AH and OCR3AL – Output Compare Register 3 A Bit 7 6 5 4 3 (0x99) OCR3A[15:8] (0x98) OCR3A[7:0] 2 1 0 OCR3AH OCR3AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 4 3 2 1 0 17.11.
ATmega640/1280/1281/2560/2561 17.11.27 OCR5BH and OCR5BL – Output Compare Register 5 B Bit 7 6 5 4 3 (0x12B) OCR5B[15:8] (0x12A) OCR5B[7:0] 2 1 0 OCR5BH OCR5BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 4 3 2 1 0 17.11.
ATmega640/1280/1281/2560/2561 The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP).
ATmega640/1280/1281/2560/2561 • Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 105) is executed when the OCFnA Flag, located in TIFRn, is set.
ATmega640/1280/1281/2560/2561 • Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB). Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag. OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.
ATmega640/1280/1281/2560/2561 18. Timer/Counter 0, 1, 3, 4, and 5 Prescaler Timer/Counter 0, 1, 3, 4, and 5 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1, 3, 4, or 5. 18.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
ATmega640/1280/1281/2560/2561 The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling.
ATmega640/1280/1281/2560/2561 • Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters When this bit is one, Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 share the same prescaler and a reset of this prescaler will affect all timers.
ATmega640/1280/1281/2560/2561 19. Output Compare Modulator (OCM1C0A) 19.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0.
ATmega640/1280/1281/2560/2561 When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. 19.2.1 Timing example Figure 19-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 19-3.
ATmega640/1280/1281/2560/2561 20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • • • • • • • 20.
ATmega640/1280/1281/2560/2561 20.1.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
ATmega640/1280/1281/2560/2561 Figure 20-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following. top Signalizes that TCNT2 has reached maximum value.
ATmega640/1280/1281/2560/2561 20.4.1 Normal Mode The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero.
ATmega640/1280/1281/2560/2561 the pin is set to output. The waveform generated will have a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ------------------------------------------------2 N 1 + OCRnx The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
ATmega640/1280/1281/2560/2561 in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0 bits). A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero.
ATmega640/1280/1281/2560/2561 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to three.
ATmega640/1280/1281/2560/2561 Figure 20-6. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
ATmega640/1280/1281/2560/2561 The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the COM2x1:0 bits will take effect immediately. 20.
ATmega640/1280/1281/2560/2561 20.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 20-5 on page 188.
ATmega640/1280/1281/2560/2561 Figure 20-10 shows the setting of OCF2A in all modes except CTC mode. Figure 20-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 20-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 20-11.
ATmega640/1280/1281/2560/2561 • The CPU main clock frequency must be more than four times the Oscillator frequency. • When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination.
ATmega640/1280/1281/2560/2561 • 20.9 During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. Timer/Counter Prescaler Figure 20-12.
ATmega640/1280/1281/2560/2561 20.10 Register Description 20.10.1 TCCR2A –Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior.
ATmega640/1280/1281/2560/2561 Table 20-4. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected WGM22 = 1: Toggle OC2A on Compare Match 1 0 Clear OC2A on Compare Match when up-counting Set OC2A on Compare Match when down-counting 1 1 Set OC2A on Compare Match when up-counting Clear OC2A on Compare Match when down-counting Note: 1.
ATmega640/1280/1281/2560/2561 Table 20-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 20-7. COM2B1 COM2B0 Description 0 0 Normal port operation, OC2B disconnected 0 1 Reserved 1 0 Clear OC2B on Compare Match when up-counting Set OC2B on Compare Match when down-counting 1 1 Set OC2B on Compare Match when up-counting Clear OC2B on Compare Match when down-counting Note: 1.
ATmega640/1280/1281/2560/2561 20.10.2 TCCR2B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 FOC2A FOC2B – – WGM22 CS22 CS21 CS20 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB1) TCCR2B • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
ATmega640/1280/1281/2560/2561 Table 20-9.
ATmega640/1280/1281/2560/2561 20.10.6 ASSR – Asynchronous Status Register Bit 7 6 5 4 3 2 1 0 (0xB6) – EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal.
ATmega640/1280/1281/2560/2561 The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 20.10.
ATmega640/1280/1281/2560/2561 • Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed.
ATmega640/1280/1281/2560/2561 21. SPI – Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega640/1280/1281/2560/2561 and peripheral devices or between several AVR devices.
ATmega640/1280/1281/2560/2561 Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line.
ATmega640/1280/1281/2560/2561 When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 21-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 75. Table 21-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
ATmega640/1280/1281/2560/2561 Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
ATmega640/1280/1281/2560/2561 The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega640/1280/1281/2560/2561 21.1 21.1.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega640/1280/1281/2560/2561 Figure 21-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 21-4.
ATmega640/1280/1281/2560/2561 21.2 21.2.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
ATmega640/1280/1281/2560/2561 • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in Table 21-5. Table 21-5. 21.2.
ATmega640/1280/1281/2560/2561 21.2.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
ATmega640/1280/1281/2560/2561 22. USART 22.
ATmega640/1280/1281/2560/2561 Figure 22-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1.
ATmega640/1280/1281/2560/2561 UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode. Figure 22-2 shows a block diagram of the clock generation logic. Figure 22-2.
ATmega640/1280/1281/2560/2561 Table 22-1.
ATmega640/1280/1281/2560/2561 duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency is limited by the following equation: f OSC f XCK ----------4 Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 22.2.
ATmega640/1280/1281/2560/2561 Figure 22-4. Frame Formats FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting.
ATmega640/1280/1281/2560/2561 check that there are no unread data in the receive buffer. Note that the TXCn Flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.
ATmega640/1280/1281/2560/2561 22.5 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
ATmega640/1280/1281/2560/2561 22.5.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
ATmega640/1280/1281/2560/2561 When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn.
ATmega640/1280/1281/2560/2561 Assembly Code Example(1) USART_Receive: ; Wait for data to be received lds r17, UCSRnA sbrs r17, RXCn rjmp USART_Receive ; Get and return received data from buffer lds r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<
ATmega640/1280/1281/2560/2561 Assembly Code Example(1) USART_Receive: ; Wait for data to be received lds r17, UCSRnA sbrs r17, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer lds r18, UCSRnA lds r17, UCSRnB lds r16, UDRn ; If error, return -1 andi r18,(1<
ATmega640/1280/1281/2560/2561 buffer is empty (that is, does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled).
ATmega640/1280/1281/2560/2561 22.6.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost. 22.6.
ATmega640/1280/1281/2560/2561 Figure 22-5. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
ATmega640/1280/1281/2560/2561 Figure 22-7. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
ATmega640/1280/1281/2560/2561 Table 22-2 and Table 22-3 list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. Table 22-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ±3.0 6 94.12 105.79 +5.79/-5.88 ±2.5 7 94.81 105.11 +5.11/-5.19 ±2.0 8 95.
ATmega640/1280/1281/2560/2561 nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
ATmega640/1280/1281/2560/2561 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDRn Register location. Reading the UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).
ATmega640/1280/1281/2560/2561 • Bit 3 – DORn: Data OverRun This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.
ATmega640/1280/1281/2560/2561 • Bit 3 – TXENn: Transmitter Enable n Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed, that is, when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted.
ATmega640/1280/1281/2560/2561 Receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 22-5. UPMn Bits Settings UPMn1 UPMn0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 22-6.
ATmega640/1280/1281/2560/2561 22.9.5 UBRRnL and UBRRnH – USART Baud Rate Registers Bit 15 14 13 12 – – – – 11 10 9 8 UBRR[11:8] UBRRHn UBRR[7:0] 7 Read/Write Initial Value 6 5 UBRRLn 4 3 2 1 0 R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written.
ATmega640/1280/1281/2560/2561 Table 22-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 1.0000MHz fosc = 1.8432MHz fosc = 2.0000MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 57.6K 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8K – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2K – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4K – – – – – – 0 0.
ATmega640/1280/1281/2560/2561 Table 22-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4K 15 0.0% 31 0.0% 16 2.1% 34 -0.
ATmega640/1280/1281/2560/2561 Table 22-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 11.0592MHz fosc = 8.0000MHz fosc = 14.7456MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4K 34 -0.8% 68 0.6% 47 0.
ATmega640/1280/1281/2560/2561 Table 22-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4K 68 0.6% 138 -0.
ATmega640/1280/1281/2560/2561 23. USART in SPI Mode The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the following features: • • • • • • • • 23.
ATmega640/1280/1281/2560/2561 A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 23-4 on page 240. 23.2.1 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. For USART MSPIM mode of operation only internal clock generation (that is, master operation) is supported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one (that is, as output) for the USART in MSPIM to operate correctly.
ATmega640/1280/1281/2560/2561 Figure 23-1. UCPHAn and UCPOLn data transfer timing diagrams. UCPHA=0 UCPHA=1 UCPOL=0 23.4 UCPOL=1 XCK XCK Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) XCK XCK Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits.
ATmega640/1280/1281/2560/2561 The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume polling (no interrupts enabled). The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. Assembly Code Example(1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode.
ATmega640/1280/1281/2560/2561 23.5 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, that is, the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
ATmega640/1280/1281/2560/2561 Assembly Code Example(1) USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRnA, UDREn rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDRn,r16 ; Wait for data to be received USART_MSPIM_Wait_RXCn: sbis UCSRnA, RXCn rjmp USART_MSPIM_Wait_RXCn ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
ATmega640/1280/1281/2560/2561 23.6.2 UCSRnA – USART MSPIM Control and Status Register n A • Bit 7 6 5 4 3 2 1 RXCn TXCn UDREn - - - - 0 - Read/Write R/W R/W R/W R R R R R Initial Value 0 0 0 0 0 1 1 0 UCSRnA • Bit 7 - RXCn: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (that is, does not contain any unread data).
ATmega640/1280/1281/2560/2561 • Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. • Bit 4 - RXENn: Receiver Enable Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override normal port operation for the RxDn pin when enabled.
ATmega640/1280/1281/2560/2561 • Bit 2 - UDORDn: Data Order When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to “SPI Data Modes and Timing” on page 233 for details. • Bit 1 - UCPHAn: Clock Phase The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCKn. Refer to “SPI Data Modes and Timing” on page 233 for details.
ATmega640/1280/1281/2560/2561 24. 2-wire Serial Interface 24.1 Features • • • • • • • • • • 24.
ATmega640/1280/1281/2560/2561 The Power Reduction TWI bit, PRTWI bit in “PRR0 – Power Reduction Register 0” on page 56 must be written to zero to enable the 2-wire Serial Interface. 24.2.2 Electrical Interconnection As depicted in Figure 24-1 on page 241, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
ATmega640/1280/1281/2560/2561 Figure 24-3. START, REPEATED START and STOP conditions SDA SCL START 24.3.3 STOP REPEATED START START STOP Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
ATmega640/1280/1281/2560/2561 24.3.4 Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled.
ATmega640/1280/1281/2560/2561 24.4 Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • An algorithm must be implemented allowing only one of the masters to complete the transmission.
ATmega640/1280/1281/2560/2561 Figure 24-8. Arbitration Between Two Masters START SDA from Master A Master A Loses Arbitration, SDAA SDA SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
ATmega640/1280/1281/2560/2561 Figure 24-9. Overview of the TWI Module Slew-rate Control SDA Spike Filter Slew-rate Control Spike Filter Bus Interface Unit START / STOP Control Spike Suppression Arbitration detection Address/Data Shift Register (TWDR) Address Match Unit Address Register (TWAR) Address Comparator Bit Rate Generator Prescaler Bit Rate Register (TWBR) Ack Control Unit Status Register (TWSR) Control Register (TWCR) State Machine and Status control TWI Unit SCL 24.5.
ATmega640/1280/1281/2560/2561 The SCL frequency is generated according to the following equation: CPU Clock frequency SCL frequency = ----------------------------------------------------------TWPS 16 + 2(TWBR) 4 • TWBR = Value of the TWI Bit Rate Register • TWPS = Value of the prescaler bits in the TWI Status Register Note: 24.5.3 Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load.
ATmega640/1280/1281/2560/2561 The TWINT Flag is set in the following situations: 24.
ATmega640/1280/1281/2560/2561 1. The first step in a TWI transmission is to transmit a START condition. This is done by writing a specific value into TWCR, instructing the TWI hardware to transmit a START condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.
ATmega640/1280/1281/2560/2561 Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be summarized as follows: • When the TWI has finished an operation and expects application response, the TWINT Flag is set. The SCL line is pulled low until TWINT is cleared. • When the TWINT Flag is set, the user must update all TWI Registers with the value relevant for the next TWI bus cycle.
ATmega640/1280/1281/2560/2561 Assembly Code Example 6 wait3: in C Example Comments while (!(TWCR & (1<
ATmega640/1280/1281/2560/2561 24.7.1 Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see Figure 24-11). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
ATmega640/1280/1281/2560/2561 This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition.
ATmega640/1280/1281/2560/2561 Figure 24-12.
ATmega640/1280/1281/2560/2561 Figure 24-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........
ATmega640/1280/1281/2560/2561 Table 24-3.
ATmega640/1280/1281/2560/2561 Figure 24-14. Formats and States in the Master Receiver Mode MR Successfull reception from a slave receiver S SLA R A $08 DATA A $40 DATA $50 A P $58 Next transfer started with a repeated start condition RS SLA R $10 Not acknowledge received after the slave address A W P $48 MT Arbitration lost in slave address or data byte A or A Other master continues A $38 Arbitration lost and addressed as slave A $68 From slave to master 24.7.
ATmega640/1280/1281/2560/2561 The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI.
ATmega640/1280/1281/2560/2561 Table 24-4.
ATmega640/1280/1281/2560/2561 Figure 24-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
ATmega640/1280/1281/2560/2561 To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
ATmega640/1280/1281/2560/2561 Table 24-5.
ATmega640/1280/1281/2560/2561 Figure 24-18. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S $C8 DATA From master to slave From slave to master 24.7.
ATmega640/1280/1281/2560/2561 Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation.
ATmega640/1280/1281/2560/2561 • Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit.
ATmega640/1280/1281/2560/2561 • Bit 7 – TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine.
ATmega640/1280/1281/2560/2561 • Bit 0 – TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT Flag is high. 24.9.
ATmega640/1280/1281/2560/2561 • Bits 7:0 – TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial Bus. 24.9.
ATmega640/1280/1281/2560/2561 • Bit 0 – Res: Reserved Bit This bit is reserved and will always read as zero.
ATmega640/1280/1281/2560/2561 25. AC – Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega640/1280/1281/2560/2561 Table 25-1. 25.2 25.2.
ATmega640/1280/1281/2560/2561 • Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. When the bandgap reference is used as input to the Analog Comparator, it will take a certain time for the voltage to stabilize. If not stabilized, the first conversion may give a wrong value.
ATmega640/1280/1281/2560/2561 25.2.3 DIDR1 – Digital Input Disable Register 1 Bit 7 6 5 4 3 2 1 0 (0x7F) – – – – – – AIN1D AIN0D Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR1 • Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
ATmega640/1280/1281/2560/2561 26. ADC – Analog to Digital Converter 26.1 Features • • • • • • • • • • • • • • • 10-bit Resolution 1 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 13µs - 260µs Conversion Time Up to 76.9kSPS (Up to 15kSPS at Maximum Resolution) 16 Multiplexed Single Ended Input Channels 14 Differential input channels 4 Differential Input Channels with Optional Gain of 10× and 200× Optional Left Adjustment for ADC Result Readout 0V - VCC ADC Input Voltage Range 2.
ATmega640/1280/1281/2560/2561 Figure 26-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] ADFR ADSC TRIGGER SELECT AREF ADC[9:0] ADIF ADPS[2:0] ADEN MUX[5] DIFF / GAIN SELECT CHANNEL SELECTION INTERNAL REFERENCE (1.1V/2.
ATmega640/1280/1281/2560/2561 If differential channels are selected, the voltage difference between the selected input channel pair then becomes the analog input to the ADC. If single ended channels are used, the amplifier is bypassed altogether. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set.
ATmega640/1280/1281/2560/2561 Figure 26-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
ATmega640/1280/1281/2560/2561 The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles.
ATmega640/1280/1281/2560/2561 Figure 26-5. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 9 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update MUX and REFS Update Figure 26-6.
ATmega640/1280/1281/2560/2561 Table 26-1. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 1.5/2.5 13/14 Condition Auto Triggered conversions Normal conversions, differential 26.4.1 Differential Channels When using differential channels, certain aspects of the conversion need to be taken into consideration.
ATmega640/1280/1281/2560/2561 26.5 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started.
ATmega640/1280/1281/2560/2561 26.5.2 ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 1.1V reference, internal 2.56V reference or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is generated from the internal bandgap reference (VBG) through an internal amplifier.
ATmega640/1280/1281/2560/2561 26.6.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 26-8. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
ATmega640/1280/1281/2560/2561 Figure 26-9. ADC Power Connections, ATmega1281/2561. PA0 VCC 10μΗ 51 52 GND 53 (ADC7) PF7 54 (ADC6) PF6 55 (ADC5) PF5 56 (ADC4) PF4 57 (ADC3) PF3 58 (ADC2) PF2 59 (ADC1) PF1 60 (ADC0) PF0 61 AREF 62 GND AVCC 63 64 100nF 100nF 1 PG5 Ground Plane Figure 26-10.
ATmega640/1280/1281/2560/2561 26.6.3 Offset Compensation Schemes The stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. This offset residue can be then subtracted in software from the measurement results. Using this kind of software based offset correction, offset on any channel can be reduced below one LSB. 26.
ATmega640/1280/1281/2560/2561 • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 26-13. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF • Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB).
ATmega640/1280/1281/2560/2561 26.7 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 26-3 on page 289 and Table 26-4 on page 290).
ATmega640/1280/1281/2560/2561 Table 26-2. Correlation Between Input Voltage and Output Codes VADCn Read Code Corresponding Decimal Value VADCm + VREF / GAIN 0x1FF 511 VADCm + 0.999 VREF / GAIN 0x1FF 511 VADCm + 0.998 VREF / GAIN 0x1FE 510 ... ... ... VADCm + 0.001 VREF / GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001 VREF / GAIN 0x3FF -1 ... ... ... VADCm - 0.999 VREF / GAIN 0x201 -511 VADCm - VREF / GAIN 0x200 -512 Example: ADMUX = 0xFB (ADC3 - ADC2, 10× gain, 2.
ATmega640/1280/1281/2560/2561 • Bit 5 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “ADCL and ADCH – The ADC Data Register” on page 294.
ATmega640/1280/1281/2560/2561 Table 26-4.
ATmega640/1280/1281/2560/2561 Table 26-4.
ATmega640/1280/1281/2560/2561 • Bit 6 – ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC.
ATmega640/1280/1281/2560/2561 26.8.4 26.8.4.1 ADCL and ADCH – The ADC Data Register ADLAR = 0 Bit 15 14 13 12 11 10 9 8 (0x79) – – – – – – ADC9 ADC8 ADCH (0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 Read/Write Initial Value 26.8.4.
ATmega640/1280/1281/2560/2561 ger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Table 26-6. Note: 26.8.
ATmega640/1280/1281/2560/2561 27. JTAG Interface and On-chip Debug System 27.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
ATmega640/1280/1281/2560/2561 Figure 27-1.
ATmega640/1280/1281/2560/2561 Figure 27-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 27.3.
ATmega640/1280/1281/2560/2561 • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The ExitIR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
ATmega640/1280/1281/2560/2561 A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 300. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system to work.
ATmega640/1280/1281/2560/2561 27.7 Using the JTAG Programming Capabilities Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and TDO. These are the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the JTAG Test Access Port.
ATmega640/1280/1281/2560/2561 28. IEEE 1149.1 (JTAG) Boundary-scan 28.1 Features • • • • • 28.2 JTAG (IEEE std. 1149.
ATmega640/1280/1281/2560/2561 28.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. 28.3.2 Device Identification Register Figure 28-1 shows the structure of the Device Identification Register. Figure 28-1.
ATmega640/1280/1281/2560/2561 Figure 28-2. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 28.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See “Boundary-scan Chain” on page 305 for a complete description. 28.
ATmega640/1280/1281/2560/2561 The active states are: 28.4.3 • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain • Shift-DR: The IDCODE scan chain is shifted by the TCK input SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
ATmega640/1280/1281/2560/2561 Control corresponds to the Data Direction - DD Register, and the Pull-up Enable - PUExn - corresponds to logic expression PUD · DDxn · PORTxn. Digital alternate port functions are connected outside the dotted box in Figure 28-4 on page 307 to make the scan chain read the actual pin value. For analog function, there is a direct connection from the external pin to the analog circuit.
ATmega640/1280/1281/2560/2561 Figure 28-4. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn PUD Q D DDxn Q CLR RESET OCxn WDx Q Pxn ODxn D PORTxn Q CLR WRx IDxn DATA BUS RDx RESET SLEEP RRx SYNCHRONIZER D Q D RPx Q PINxn L Q Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 28.5.
ATmega640/1280/1281/2560/2561 28.6 28.6.1 Boundary-scan Related Register in I/O Memory MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bits 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.
ATmega640/1280/1281/2560/2561 Table 28-1. ATmega640/1280/2560 Boundary-scan Order Bit Number Signal Name 164 PG5.Data 163 PG5.Control 162 PE0.Data 161 PE0.Control 160 PE1.Data 159 PE1.Control 158 PE2.Data 157 PE2.Control 156 PE3.Data 155 PE3.Control 154 PE4.Data 153 PE4.Control 152 PE5.Data 151 PE5.Control 150 PE6.Data 149 PE6.Control 148 PE7.Data 147 PE7.Control 146 PH0.Data 145 PH0.Control 144 PH1.Data 143 PH1.Control 142 PH2.Data 141 PH2.
ATmega640/1280/1281/2560/2561 Table 28-1. ATmega640/1280/2560 Boundary-scan Order (Continued) Bit Number Signal Name 132 PB0.Data 131 PB0.Control 130 PB1.Data 129 PB1.Control 128 PB2.Data 127 PB2.Control 126 PB3.Data 125 PB3.Control 124 PB4.Data 123 PB4.Control 122 PB5.Data 121 PB5.Control 120 PB6.Data 119 PB6.Control 118 PB7.Data 117 PB7.Control 116 PH7.Data 115 PH7.Control 114 PG3.Data 113 PG3.Control 112 PG4.Data 111 PG4.Control 110 RSTT 109 PL0.
ATmega640/1280/1281/2560/2561 Table 28-1. ATmega640/1280/2560 Boundary-scan Order (Continued) Bit Number Signal Name 104 PL2.Control 103 PL3.Data 102 PL3.Control 101 PL4.Data 100 PL4.Control 99 PL5.Data 98 PL5.Control 97 PL6.Data 96 PL6.Control 95 PL7.Data 94 PL7.Control 93 PD0.Data 92 PD0.Control 91 PD1.Data 90 PD1.Control 89 PD2.Data 88 PD2.Control 87 PD3.Data 86 PD3.Control 85 PD4.Data 84 PD4.Control 83 PD5.Data 82 PD5.Control 81 PD6.Data 80 PD6.
ATmega640/1280/1281/2560/2561 Table 28-1. ATmega640/1280/2560 Boundary-scan Order (Continued) Bit Number Signal Name 68 PC2.Control 67 PC3.Data 66 PC3.Control 65 PC4.Data 64 PC4.Control 63 PC5.Data 62 PC5.Control 61 PC6.Data 60 PC6.Control 59 PC7.Data 58 PC7.Control 57 PJ0.Data 56 PJ0.Control 55 PJ1.Data 54 PJ1.Control 53 PJ2.Data 52 PJ2.Control 51 PJ3.Data 50 PJ3.Control 49 PJ4.Data 48 PJ4.Control 47 PJ5.Data 46 PJ5.Control 45 PJ6.Data 44 PJ6.
ATmega640/1280/1281/2560/2561 Table 28-1. ATmega640/1280/2560 Boundary-scan Order (Continued) Bit Number Signal Name 32 PA3.Control 31 PA2.Data 30 PA2.Control 29 PA1.Data 28 PA1.Control 27 PA0.Data 26 PA0.Control 25 PJ7.Data 24 PJ7.Control 23 PK7.Data 22 PK7.Control 21 PK6.Data 20 PK6.Control 19 PK5.Data 18 PK5.Control 17 PK4.Data 16 PK4.Control 15 PK3.Data 14 PK3.Control 13 PK2.Data 12 PK2.Control 11 PK1.Data 10 PK1.Control 9 PK0.Data 8 PK0.
ATmega640/1280/1281/2560/2561 Table 28-2. ATmega1281/2561 Boundary-scan Order Bit Number Signal Name 100 PG5.Data 99 PG5.Control 98 PE0.Data 97 PE0.Control 96 PE1.Data 95 PE1.Control 94 PE2.Data 93 PE2.Control 92 PE3.Data 91 PE3.Control 90 PE4.Data 89 PE4.Control 88 PE5.Data 87 PE5.Control 86 PE6.Data 85 PE6.Control 84 PE7.Data 83 PE7.Control 82 PB0.Data 81 PB0.Control 80 PB1.Data 79 PB1.Control 78 PB2.Data 77 PB2.Control 76 PB3.Data 75 PB3.
ATmega640/1280/1281/2560/2561 Table 28-2. ATmega1281/2561 Boundary-scan Order (Continued) Bit Number Signal Name 65 PG3.Control 64 PG4.Data 63 PG4.Control 62 RSTT 61 PD0.Data 60 PD0.Control 59 PD1.Data 58 PD1.Control 57 PD2.Data 56 PD2.Control 55 PD3.Data 54 PD3.Control 53 PD4.Data 52 PD4.Control 51 PD5.Data 50 PD5.Control 49 PD6.Data 48 PD6.Control 47 PD7.Data 46 PD7.Control 45 PG0.Data 44 PG0.Control 43 PG1.Data 42 PG1.Control 41 PC0.Data 40 PC0.
ATmega640/1280/1281/2560/2561 Table 28-2. ATmega1281/2561 Boundary-scan Order (Continued) Bit Number Signal Name 29 PC6.Data 28 PC6.Control 27 PC7.Data 26 PC7.Control 25 PG2.Data 24 PG2.Control 23 PA7.Data 22 PA7.Control 21 PA6.Data 20 PA6.Control 19 PA5.Data 18 PA5.Control 17 PA4.Data 16 PA4.Control 15 PA3.Data 14 PA3.Control 13 PA2.Data 12 PA2.Control 11 PA1.Data 10 PA1.Control 9 PA0.Data 8 PA0.Control 7 PF3.Data 6 PF3.Control 5 PF2.Data 4 PF2.
ATmega640/1280/1281/2560/2561 29. Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
ATmega640/1280/1281/2560/2561 divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 291 and Figure 29-1 on page 319.
ATmega640/1280/1281/2560/2561 Figure 29-1. Read-While-Write vs.
ATmega640/1280/1281/2560/2561 Figure 29-2.
ATmega640/1280/1281/2560/2561 Table 29-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or (E)LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and (E)LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
ATmega640/1280/1281/2560/2561 29.5 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers ZL and ZH in the register file, and RAMPZ in the I/O space. The number of bits actually used is implementation dependent. Note that the RAMPZ register is only implemented when the program space is larger than 64Kbytes.
ATmega640/1280/1281/2560/2561 29.6 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
ATmega640/1280/1281/2560/2561 29.6.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation.
ATmega640/1280/1281/2560/2561 29.6.8 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 29.6.
ATmega640/1280/1281/2560/2561 SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will work as described in the Instruction set Manual. Table 29-5.
ATmega640/1280/1281/2560/2561 29.6.13 Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
ATmega640/1280/1281/2560/2561 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
ATmega640/1280/1281/2560/2561 Table 29-8. Read-While-Write Limit, ATmega640 Section(1) Pages Address Read-While-Write section (RWW) 224 0x0000 - 0x6FFF No Read-While-Write section (NRWW) 32 0x7000 - 0x7FFF Note: 1. For details about these two section, see “NRWW – No Read-While-Write Section” on page 318 and “RWW – Read-While-Write Section” on page 318. Table 29-9.
ATmega640/1280/1281/2560/2561 29.6.15 ATmega1280/1281 Boot Loader Parameters In Table 29-10 and Table 29-11, the parameters used in the description of the Self-Programming are given. Boot Reset Address (Start Boot Loader Section) End Application Section Boot Loader Flash Section Appli-cation Flash Section Pages Boot Size BOOTSZ0 BOOTSZ1 Table 29-10.
ATmega640/1280/1281/2560/2561 Table 29-12. Explanation of different variables used in Figure 29-3 on page 322 and the mapping to the Z-pointer, ATmega1280/1281 (Continued) Corresponding Z-value(2) Variable PAGEMSB Description(1) Most significant bit which is used to address the words within one page (128 words in a page requires seven bits PC [6:0]). 6 ZPCMSB Z16(3) Bit in Z-pointer that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1.
ATmega640/1280/1281/2560/2561 Table 29-14. Read-While-Write Limit, ATmega2560/2561 Section(1) Pages Address Read-While-Write section (RWW) 992 0x00000 - 0x1EFFF No Read-While-Write section (NRWW) 32 0x1F000 - 0x1FFFF Note: 1. For details about these two section, see “NRWW – No Read-While-Write Section” on page 318 and “RWW – Read-While-Write Section” on page 318. Table 29-15.
ATmega640/1280/1281/2560/2561 • Bit 6 – RWWSB: Read-While-Write Section Busy When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated.
ATmega640/1280/1281/2560/2561 • Bit 0 – SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored.
ATmega640/1280/1281/2560/2561 30. Memory Programming 30.1 Program And Data Memory Lock Bits The ATmega640/1280/1281/2560/2561 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 30-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 30-1.
ATmega640/1280/1281/2560/2561 Lock Bit Protection Modes(1)(2) (Continued) Table 30-2. Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or (E)LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega640/1280/1281/2560/2561 Table 30-4. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega640/1280/1281/2560/2561 30.2.1 30.3 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
ATmega640/1280/1281/2560/2561 30.6.1 Signal Names In this section, some pins of the ATmega640/1280/1281/2560/2561 are referenced by signal names describing their functionality during parallel programming, see Figure 30-1 and Table 309. Pins not described in the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 30-12 on page 340.
ATmega640/1280/1281/2560/2561 Table 30-10. BS2 and BS1 Encoding Flash Data Loading / Reading Fuse Programming Reading Fuse and Lock Bits BS2 BS1 Flash / EEPROM Address 0 0 Low Byte Low Byte Low Byte Fuse Low Byte 0 1 High Byte High Byte High Byte Lockbits 1 0 Extended High Byte Reserved Extended Byte Extended Fuse Byte 1 1 Reserved Reserved Reserved Fuse High Byte Table 30-11.
ATmega640/1280/1281/2560/2561 30.7 30.7.1 Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5V - 5.5V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 30-11 on page 340 to “0000” and wait at least 100ns. 4. Apply 11.5V - 12.5V to RESET.
ATmega640/1280/1281/2560/2561 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B. Load Address Low byte (Address bits 7:0) 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS2, BS1 to “00”. This selects the address low byte. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2.
ATmega640/1280/1281/2560/2561 K. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 30-2.
ATmega640/1280/1281/2560/2561 follows (refer to “Programming the Flash” on page 341 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. C: Load Data (0x00 - 0xFF). 5. E: Latch data (give PAGEL a positive pulse). K: Repeat 3 through 5 until the entire buffer is filled L: Program EEPROM page 1. Set BS2, BS1 to “00”. 2. Give WR a negative pulse. This starts programming of the EEPROM page.
ATmega640/1280/1281/2560/2561 30.7.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 341 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 30.7.
ATmega640/1280/1281/2560/2561 Figure 30-5. Programming the FUSES Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 30.7.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 341 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2.
ATmega640/1280/1281/2560/2561 Figure 30-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte BS1 1 BS2 30.7.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 341 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS to “0”.
ATmega640/1280/1281/2560/2561 Figure 30-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 30-7 on page 347 (that is, tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 30-9.
ATmega640/1280/1281/2560/2561 Table 30-14.
ATmega640/1280/1281/2560/2561 30.8.1 Serial Programming Pin Mapping Table 30-15. Pin Mapping Serial Programming Symbol Pins (TQFP-100) Pins (TQFP-64) I/O Description PDI PB2 PE0 I Serial Data in PDO PB3 PE1 O Serial Data out SCK PB1 PB1 I Serial Clock Figure 30-10. Serial Programming and Verify(1) +1.8V - 5.5V VCC +1.8V - 5.5V(2) PDI AVCC PDO SCK XT AL1 RESET GND Notes: 1.
ATmega640/1280/1281/2560/2561 To program and verify the ATmega640/1280/1281/2560/2561 in the serial programming mode, the following sequence is recommended (see four byte instruction formats in Table 30-17 on page 352): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up.
ATmega640/1280/1281/2560/2561 30.8.3 Serial Programming Instruction set Table 30-17 and Figure 30-11 on page 353 describes the Instruction set. Table 30-17.
ATmega640/1280/1281/2560/2561 Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 30-11. Figure 30-11.
ATmega640/1280/1281/2560/2561 30.9 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
ATmega640/1280/1281/2560/2561 Figure 30-13. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 30.9.
ATmega640/1280/1281/2560/2561 30.9.4 30.9.5 30.9.6 30.9.7 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register.
ATmega640/1280/1281/2560/2561 30.9.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register.
ATmega640/1280/1281/2560/2561 Figure 30-15.
ATmega640/1280/1281/2560/2561 Table 30-18. JTAG Programming Instruction Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
ATmega640/1280/1281/2560/2561 Table 30-18. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 5c.
ATmega640/1280/1281/2560/2561 Table 30-18. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 8d. Read Fuse Low Byte(8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8e. Read Lock Bits(9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) 8f.
ATmega640/1280/1281/2560/2561 Figure 30-16. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 30.9.
ATmega640/1280/1281/2560/2561 ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 30-17.
ATmega640/1280/1281/2560/2561 30.9.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 30-14 on page 348). 30.9.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 364. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3.
ATmega640/1280/1281/2560/2561 A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b, 3c and 3d. PCWORD (refer to Table 30-7 on page 338) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5.
ATmega640/1280/1281/2560/2561 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 30-14 on page 348). 6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a “1” will unprogram the fuse. 7. Write Fuse low byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 30-14 on page 348). 30.9.21 Programming the Lock Bits 1.
ATmega640/1280/1281/2560/2561 31. Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.
ATmega640/1280/1281/2560/2561 TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition (5) Min. Typ. Max. Active 1MHz, VCC = 2V (ATmega640/1280/2560/1V) 0.5 0.8 Active 4MHz, VCC = 3V (ATmega640/1280/2560/1L) 3.2 5 Active 8MHz, VCC = 5V (ATmega640/1280/1281/2560/2561) 10 14 Idle 1MHz, VCC = 2V (ATmega640/1280/2560/1V) 0.14 0.22 Idle 4MHz, VCC = 3V (ATmega640/1280/2560/1L) 0.7 1.1 Idle 8MHz, VCC = 5V (ATmega640/1280/1281/2560/2561) 2.
ATmega640/1280/1281/2560/2561 5)The sum of all IOH, for ports F0-F7, K0-K7 should not exceed 100mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Values with “PRR1 – Power Reduction Register 1” enabled (0xFF). 31.2 Speed Grades Maximum frequency is depending on VCC. As shown in Figure 31-1 trough Figure 31-4 on page 370, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.
ATmega640/1280/1281/2560/2561 31.2.2 16 MHz Figure 31-3. Maximum Frequency vs. VCC, ATmega640/ATmega1280/ATmega1281 16 MHz 8 MHz Safe Operating Area 2.7V 4.5V 5.5V Figure 31-4. Maximum Frequency vs. VCC, ATmega2560/ATmega2561 16 MHz Safe Operating Area 4.5V 5.
ATmega640/1280/1281/2560/2561 31.3 31.3.1 Clock Characteristics Calibrated Internal RC Oscillator Accuracy Table 31-1. Calibration Accuracy of Internal RC Oscillator Factory Calibration Frequency VCC 8.0MHz 3V Temperature Calibration Accuracy 25C ±10% -40C - 85C ±1% (1) User Calibration Notes: 1.8V - 5.5V 2.7V - 5.5V(2) 7.3MHz - 8.1MHz 1. Voltage range for ATmega640V/1281V/1280V/2561V/2560V. 2. Voltage range for ATmega640/1281/1280/2561/2560. 31.3.
ATmega640/1280/1281/2560/2561 31.5 System and Reset Characteristics Table 31-3. Symbol Reset, Brown-out and Internal voltage CharacteristicsCharacteristics Parameter Condition VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin VHYST Min Typ 0.2VCC Max Units 0.9VCC V 2.5 µs Brown-out Detector Hysteresis 50 mV tBOD Min Pulse Width on Brown-out Reset 2 µs VBG Bandgap reference voltage VCC=2.
ATmega640/1280/1281/2560/2561 31.5.2 Enhanced Power-On Reset This implementation of power-on reset exists in newer versions of ATmega640/1280/1281/2560/2561. The table below describes the characteristics of this poweron reset and it is valid for the following devices only: • ATmega640: revision B and newer • ATmega1280: revision B and newer • ATmega1281: revision B and newer • ATmega2560: revision F and newer • ATmega2561: revision F and newer Table 31-5.
ATmega640/1280/1281/2560/2561 Table 31-7. 2-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys (1) Min Max Input Low-voltage -0.5 0.3 VCC Input High-voltage 0.7 VCC Hysteresis of Schmitt Trigger Inputs VOL(1) Output Low-voltage tr(1) Rise Time for both SDA and SCL tof(1) Output Fall Time from VIHmin to VILmax tSP(1) Spikes Suppressed by Input Filter Ii Input Current each I/O Pin Ci(1) Capacitance for each I/O Pin fSCL Rp tHD;STA SCL Clock Frequency 0.
ATmega640/1280/1281/2560/2561 5. This requirement applies to all ATmega640/1280/1281/2560/2561 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz. 7.
ATmega640/1280/1281/2560/2561 Figure 31-7. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 8 7 MOSI (Data Output) MSB ... LSB Figure 31-8. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
ATmega640/1280/1281/2560/2561 31.8 ADC Characteristics – Preliminary Data Table 31-9. Symbol ADC Characteristics, Singel Ended Channels Typ(1) Max(1) Condition Resolution Single Ended Conversion 10 Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC= 200kHz 2.
ATmega640/1280/1281/2560/2561 Table 31-10.
ATmega640/1280/1281/2560/2561 Table 31-10. ADC Characteristics, Differential Channels (Continued) Symbol Parameter AVCC Analog Supply Voltage VREF Reference Voltage Condition Min(1) Typ(1) Max(1) VCC - 0.3 VCC + 0.3 2.7 AVCC - 0.
ATmega640/1280/1281/2560/2561 Table 31-12. External Data Memory Characteristics, 4.5 to 5.5 Volts, 1 Cycle Wait-state 8MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 240 2.0tCLCL-10 15 tDVWH Data Valid to WR High 240 2.0tCLCL 16 tWLWH WR Pulse Width 240 2.0tCLCL-10 200 2.0tCLCL-50 ns Table 31-13. External Data Memory Characteristics, 4.5 to 5.
ATmega640/1280/1281/2560/2561 Table 31-15. External Data Memory Characteristics, 2.7 to 5.5 Volts, No Wait-state (Continued) 4MHz Oscillator Max Variable Oscillator Symbol Parameter Min Min Max Unit 1 tLHLL ALE Pulse Width 235 tCLCL-15 2 tAVLL Address Valid A to ALE Low 115 0.5tCLCL-10(1) 3a tLLAX_ST Address Hold After ALE Low, write access 5 5 3b tLLAX_LD Address Hold after ALE Low, read access 5 5 4 tAVLLC Address Valid C to ALE Low 115 0.
ATmega640/1280/1281/2560/2561 Table 31-17. External Data Memory Characteristics, 2.7 to 5.5 Volts, SRWn1 = 1, SRWn0 = 0 4MHz Oscillator Min Variable Oscillator Symbol Parameter Max Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 8 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 735 3.0tCLCL-15 15 tDVWH Data Valid to WR High 750 3.0tCLCL 16 tWLWH WR Pulse Width 735 3.0tCLCL-15 690 3.0tCLCL-60 ns Table 31-18. External Data Memory Characteristics, 2.7 to 5.
ATmega640/1280/1281/2560/2561 Figure 31-10. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 3a DA7:0 Prev. data Address 13 Data XX 14 16 6 Write 2 WR 3b DA7:0 (XMBK = 0) 11 9 Data 5 Read Address 10 8 12 RD Figure 31-11. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T4 T5 T6 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 DA7:0 Prev.
ATmega640/1280/1281/2560/2561 Figure 31-12. External Memory Timing (SRWn1 = 1, SRWn0 = 1)() T1 T2 T3 T4 T6 T5 T7 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 3a DA7:0 Prev. data Address 13 XX Data 14 16 6 Write 2 WR 9 3b Address 11 Data 5 Read DA7:0 (XMBK = 0) 10 8 12 RD The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external).
ATmega640/1280/1281/2560/2561 32. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off.
ATmega640/1280/1281/2560/2561 Figure 32-2. Active Supply Current vs. Frequency (1MHz - 16MHz) 25 5.5V 5.0V 20 ICC (m A) 4.5V 15 4.0V 10 3.3V 2.7V 5 1.8V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 32-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 14 85°C 25°C -40°C 12 ICC (mA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 Figure 32-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 2.5 -40°C 85°C 25°C 2 ICC (mA) 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.7 0.6 -40°C ICC (mA) 0.5 0.4 25°C 85°C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 32.2 Idle Supply Current Figure 32-6. Idle Supply Current vs. Low Frequency (0.1MHz - 1.0MHz) 0.6 5.5V 0.5 5.0V ICC (mA) 0.4 4.5V 4.0V 0.3 3.3V 0.2 2.7V 1.8V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 32-7. Idle Supply Current vs. Frequency (1MHz - 16MHz) 8 7 5.5V 6 5.0V ICC (m A) 5 4.5V 4 4.0V 3 2 3.3V 2.7V 1 1.
ATmega640/1280/1281/2560/2561 Figure 32-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 3.5 85°C 25°C -40°C 3 ICC (mA) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.9 -40°C 0.8 0.7 85°C 25°C ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 Figure 32-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)I 0.3 -40°C 0.25 ICC (m A) 0.2 0.15 25°C 85°C 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 32.2.1 Supply Current of IO modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register.
ATmega640/1280/1281/2560/2561 Table 32-2. Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock Additional Current consumption compared to Idle with external clock PRUSART3 3.0% 17% PRUSART2 3.0% 17% PRUSART1 3.0% 17% PRUSART0 3.0% 17% PRTWI 4.4% 24% PRTIM5 1.8% 10% PRTIM4 1.8% 10% PRTIM3 1.8% 10% PRTIM2 4.3% 23% PRTIM1 1.8% 10% PRTIM0 1.5% 8.0% PRSPI 3.3% 18% PRADC 4.
ATmega640/1280/1281/2560/2561 32.3 Power-down Supply Current Figure 32-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 4 85°C 3.5 3 ICC (µA) 2.5 2 1.5 -40°C 25°C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 12 85°C 10 -40°C 25°C ICC (µA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 32.4 Power-save Supply Current Figure 32-13. Power-save Supply Current vs. VCC g (Watchdog Timer Disabled) 11 25°C 10 ICC(uA) 9 8 7 6 5 4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-14. Power-save Supply Current vs. VCC (Watchdog Timer Enabled) 9 8 25°C 7 I CC (µA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 32.5 Standby Supply Current Figure 32-15. Standby Supply Current vs. VCC (Watchdog Timer Disabled) 0.2 6MHz xtal 6MHz res 0.18 0.16 ICC (mA) 0.14 4MHz res 4MHz xtal 0.12 0.1 0.08 2MHz res 2MHz xtal 0.06 1MHz res 455kHz res 0.04 0.02 32kHz xtal 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 32.6 Pin Pull-up Figure 32-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 60 50 IOP (µA) 40 30 20 10 25°C 85°C -40°C 0 0 0.2 0.4 0.6 0.8 1 1.
ATmega640/1280/1281/2560/2561 Figure 32-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 90 80 70 IOP (µA) 60 50 40 30 20 85°C 25°C -40°C 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 32-18. I/O Pin Pull-up Resistor Current vs.
ATmega640/1280/1281/2560/2561 Figure 32-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET (µA) 30 25 20 15 10 25°C -40°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) Figure 32-20. Reset pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 70 60 IRESET (µA) 50 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1 1.5 2 2.
ATmega640/1280/1281/2560/2561 Figure 32-21. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET (µA) 80 60 40 20 25°C -40°C 85°C 0 0 1 2 3 4 5 6 VRESET (V) 32.7 Pin Driver Strength Figure 32-22. I/O Pin output Voltage vs.Sink Current (VCC = 3V) 1 0.9 85°C VOL (V) 0.8 0.7 25°C 0.6 -40°C 0.5 0.4 0.3 0.2 0.
ATmega640/1280/1281/2560/2561 Figure 32-23. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 85°C 0.5 25°C -40°C VOL (V) 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 IOL (mA) Figure 32-24. I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.5 3 VOH (V) 2.5 -40°C 25°C 85°C 2 1.5 1 0.
ATmega640/1280/1281/2560/2561 Figure 32-25. I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 0 5 10 15 20 25 IOH (mA) 32.8 Pin Threshold and Hysteresis Figure 32-26. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as “1“) 3.5 -40°C 25°C 85°C 3 Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 Figure 32-27. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as “0“) 2.5 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-28. I/O Pin Input Hysteresis 0.8 -40°C Input Hyst eresis (mV) 0.7 0.6 0.5 25°C 85°C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 Figure 32-29. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as “1“) 2.5 -40°C 25°C 85°C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-30. Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as “0“) 2.5 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 Figure 32-31. Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 0.1 -40°C 25°C 85°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 80 100 VCC (V) 32.9 BOD Threshold and Analog Comparator Offset Figure 32-32. BOD Threshold vs. Temperature (BOD Level is 4.3V) 4.4 4.35 Threshold (V) Rising Vcc 4.3 4.25 Falling Vcc 4.
ATmega640/1280/1281/2560/2561 Figure 32-33. BOD Threshold vs. Temperature (BOD Level is 2.7V) 2.8 Rising Vcc Threshold (V) 2.75 2.7 Falling Vcc 2.65 2.6 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 32-34. BOD Threshold vs. Temperature (BOD Level is 1.8V) 1.9 1.85 T hre shold ( V ) Rising Vcc 1.8 Fallling Vcc 1.75 1.
ATmega640/1280/1281/2560/2561 32.10 Internal Oscillator Speed Figure 32-35. Watchdog Oscillator Frequency vs. VCC 128 126 -40°C FRC (kHz) 124 25°C 122 120 118 116 85°C 114 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-36. Watchdog Oscillator Frequency vs. Temperature 128 126 FRC (kHz) 124 122 120 2.1V 2.7V 3.3V 4.0V 5.
ATmega640/1280/1281/2560/2561 Figure 32-37. Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.3 85°C 8.2 FRC (MHz) 8.1 25°C 8 7.9 -40°C 7.8 7.7 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-38. Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.5 5.0V 8.4 3.0V FRC (MHz) 8.3 8.2 8.1 8 7.
ATmega640/1280/1281/2560/2561 Figure 32-39. Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value 16 85°C 25°C -40°C 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 32.11 Current Consumption of Peripheral Units Figure 32-40. Brownout Detector Current vs. VCC 30 85°C 25°C -40°C 25 ICC (µA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 Figure 32-41. ADC Current vs. VCC (AREF = AVCC) 350 -40°C 25°C 85°C 300 ICC (µA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-42. AREF External Reference Current vs. VCC 250 -40°C 25°C 85°C 200 ICC (µA) 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 Figure 32-43. Watchdog Timer Current vs. VCC 9 -40°C 8 25°C 85°C 7 ICC (µA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-44. Analog Comparator Current vs. VCC 100 -40°C 25°C 85°C 90 80 ICC (µA) 70 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 Figure 32-45. Programming Current vs. VCC 16 -40°C 14 12 25°C ICC (mA) 10 8 85°C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 32.12 Current Consumption in Reset and Reset Pulsewidth Figure 32-46. Reset Supply Current vs VCC (0.1MHz - 1.0MHz, Excluding Current Through The Reset Pull-up) 0.35 5.5V 0.3 5.0V 0.25 ICC (m A) 4.5V 0.2 4.0V 0.15 3.3V 0.1 2.7V 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega640/1280/1281/2560/2561 Figure 32-47. Reset Supply Current vs. VCC (1MHz - 16MHz, Excluding Current Through The Reset Pull-up) 4 5.5V 3.5 5.0V ICC (m A) 3 4.5V 2.5 2 4.0V 1.5 1 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 32-48. Minimum Reset Pulse Width vs. VCC 2500 Pu lsewidth (ns) 2000 1500 1000 85°C 25°C -40°C 500 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega640/1280/1281/2560/2561 33. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x1FF) Reserved - - - - - - - - - - - - - - - - - - - ...
ATmega640/1280/1281/2560/2561 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x100) PINH PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 103 (0xFF) Reserved - - - - - - - - (0xFE) Reserved - - - - - - - - (0xFD) Reserved - - - - - - - - (0xFC) Reserved - - - - - - - - (0xFB) Reserved - - - - - - - - (0xFA) Reserved - - - - - - - - (0xF9) Reserved - - - - - - - - (0xF8) Reserved - - - - - -
ATmega640/1280/1281/2560/2561 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBE) Reserved - - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - 269 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE 266 (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 269 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 268 2-wire Serial Interface Data Register Page 268 (0xB8) TWBR (0xB7) Reserved
ATmega640/1280/1281/2560/2561 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Page 289 (0x7B) ADCSRB - ACME - - MUX5 ADTS2 ADTS1 ADTS0 272, 290, 294 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 292 (0x79) ADCH ADC Data Register High byte (0x78) ADCL ADC Data Register Low byte (0x77) Reserved (0x76) (0x75) 294 294 - - - - - - - - Reserved - - - - - - - - XMCR
ATmega640/1280/1281/2560/2561 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1A (0x3A) TIFR5 - - ICF5 - OCF5C OCF5B OCF5A TOV5 166 0x19 (0x39) TIFR4 - - ICF4 - OCF4C OCF4B OCF4A TOV4 167 0x18 (0x38) TIFR3 - - ICF3 - OCF3C OCF3B OCF3A TOV3 167 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 193 0x16 (0x36) TIFR1 - - ICF1 - OCF1C OCF1B OCF1A TOV1 167 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 134 0x14 (0x34) PORT
ATmega640/1280/1281/2560/2561 34.
ATmega640/1280/1281/2560/2561 Mnemonics Operands Description Operation Flags #Clocks BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 N
ATmega640/1280/1281/2560/2561 Mnemonics ELPM Operands Rd, Z+ SPM Description Operation Flags #Clocks Extended Load Program Memory Rd (RAMPZ:Z), RAMPZ:Z RAMPZ:Z+1 None Store Program Memory (Z) R1:R0 None - Rd P None 1 3 IN Rd, P In Port OUT P, Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 None 1 MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep (see specific descr.
ATmega640/1280/1281/2560/2561 35. Ordering Information 35.1 ATmega640 Speed (MHz)(2) Power Supply 8 16 Notes: Ordering Code Package(1)(3) 1.8 - 5.5V ATmega640V-8AU ATmega640V-8AUR(4) ATmega640V-8CU ATmega640V-8CUR(4) 100A 100A 100C1 100C1 2.7 - 5.5V ATmega640-16AU ATmega640-16AUR(4) ATmega640-16CU ATmega640-16CUR(4) 100A 100A 100C1 100C1 Operation Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form.
ATmega640/1280/1281/2560/2561 35.2 ATmega1280 Speed (MHz)(2) Power Supply 8 16 Notes: Ordering Code Package(1)(3) 1.8V - 5.5V ATmega1280V-8AU ATmega1280V-8AUR(4) ATmega1280V-8CU ATmega1280V-8CUR(4) 100A 100A 100C1 100C1 2.7V - 5.5V ATmega1280-16AU ATmega1280-16AUR(4) ATmega1280-16CU ATmega1280-16CUR(4) 100A 100A 100C1 100C1 Operation Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form.
ATmega640/1280/1281/2560/2561 35.3 ATmega1281 Speed (MHz)(2) 8 16 Notes: Ordering Code Package(1)(3) 1.8 - 5.5V ATmega1281V-8AU ATmega1281V-8AUR(4) ATmega1281V-8MU ATmega1281V-8MUR(4) 64A 64A 64M2 64M2 2.7 - 5.5V ATmega1281-16AU ATmega1281-16AUR(4) ATmega1281-16MU ATmega1281-16MUR(4) 64A 64A 64M2 64M2 Power Supply Operation Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form.
ATmega640/1280/1281/2560/2561 35.4 ATmega2560 Speed (MHz)(2) Power Supply 8 16 Notes: Ordering Code Package(1)(3) 1.8V - 5.5V ATmega2560V-8AU ATmega2560V-8AUR(4) ATmega2560V-8CU ATmega2560V-8CUR(4) 100A 100A 100C1 100C1 4.5V - 5.5V ATmega2560-16AU ATmega2560-16AUR(4) ATmega2560-16CU ATmega2560-16CUR(4) 100A 100A 100C1 100C1 Operation Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form.
ATmega640/1280/1281/2560/2561 35.5 ATmega2561 Speed (MHz)(2) Power Supply 8 16 Notes: Ordering Code Package(1)(3) 1.8V - 5.5V ATmega1281V-8AU ATmega1281V-8AUR(4) ATmega1281V-8MU ATmega1281V-8MUR(4) 64A 64A 64M2 64M2 4.5V - 5.5V ATmega1281-16AU ATmega1281-16AUR(4) ATmega1281-16MU ATmega1281-16MUR(4) 64A 64A 64M2 64M2 Operation Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form.
ATmega640/1280/1281/2560/2561 36. Packaging Information 36.1 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.
ATmega640/1280/1281/2560/2561 36.2 100C1 0.12 Z E Marked A1 Identifier SIDE VIEW D A TOP VIEW A1 Øb e A1 Corner 0.90 TYP 10 9 8 7 6 5 4 3 2 1 A 0.90 TYP B C D COMMON DIMENSIONS (Unit of Measure = mm) E D1 F e SYMBOL MIN NOM MAX H A 1.10 – 1.20 I A1 0.30 0.35 0.40 D 8.90 9.00 9.10 E 8.90 9.00 9.10 G J E1 BOTTOM VIEW D1 7.10 7.20 7.30 E1 7.10 7.20 7.30 Øb 0.35 0.40 0.45 e NOTE 0.
ATmega640/1280/1281/2560/2561 36.3 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.
ATmega640/1280/1281/2560/2561 36.4 64M2 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 – 0.02 0.05 0.18 0.25 0.30 A1 b K Option C b e BOTTOM VIEW Notes: Pin #1 Notch (0.20 R) D 8.90 9.00 9.10 D2 5.20 5.40 5.60 E 8.90 9.00 9.10 E2 5.20 5.40 5.60 e NOTE 0.
ATmega640/1280/1281/2560/2561 37. Errata 37.1 ATmega640 rev. B • Inaccurate ADC conversion in differential mode with 200× gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None. 2.
ATmega640/1280/1281/2560/2561 Problem Fix/Workaround None. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 37.4 ATmega1280 rev.
ATmega640/1280/1281/2560/2561 37.6 ATmega1281 rev. A • Inaccurate ADC conversion in differential mode with 200× gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None. 2.
ATmega640/1280/1281/2560/2561 37.12 ATmega2560 rev. A • • • • • • 1. Non-Read-While-Write area of flash not functional Part does not work under 2.4 volts Incorrect ADC reading in differential mode Internal ADC reference has too low value IN/OUT instructions may be executed twice when Stack is in external RAM EEPROM read from application code does not work in Lock Bit Mode 3 Non-Read-While-Write area of flash not functional The Non-Read-While-Write area of the flash is not working as expected.
ATmega640/1280/1281/2560/2561 Problem Fix/Workaround There are two application work-arounds, where selecting one of them, will be omitting the issue: - Replace IN and OUT with LD/LDS/LDD and ST/STS/STD instructions. - Use internal RAM for stack pointer. 6. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code.
ATmega640/1280/1281/2560/2561 1. Non-Read-While-Write area of flash not functional The Non-Read-While-Write area of the flash is not working as expected. The problem is related to the speed of the part when reading the flash of this area. Problem Fix/Workaround - Only use the first 248K of the flash. - If boot functionality is needed, run the code in the Non-Read-While-Write area at maximum 1/4th of the maximum frequency of the device at any given voltage.
ATmega640/1280/1281/2560/2561 Problem Fix/Workaround Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM.
ATmega640/1280/1281/2560/2561 38. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision. 38.1 Rev. 2549O-05/12 1. 2. 3. 38.2 Rev. 2549N-05/11 1. 2. 3. 4. 5. 6. 7. 38.3 The datasheet changed status from Preliminary to Complete. Removed “Preliminary” from the front page. Replaced Figure 10-3 on page 46 by a new one.
ATmega640/1280/1281/2560/2561 38.4 Rev. 2549L-08/07 1. 2. 3. 4. 5. 6. 7. 8. 9. 38.5 Rev. 2549K-01/07 1. 2. 3. 4. 5. 6: 7. 8. 9. 10. 38.6 Updated Table 1-1 on page 3. Updated “Pin Descriptions” on page 7. Updated “Stack Pointer” on page 16. Updated “Bit 1 – EEPE: EEPROM Programming Enable” on page 36.
ATmega640/1280/1281/2560/2561 38.8 Rev. 2549H-06/06 1. 2. 3. 38.9 Updated “” on page 46. Updated “OSCCAL – Oscillator Calibration Register” on page 50. Added Table 31-1 on page 371. Rev. 2549G-06/06 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Updated “Features” on page 1. Added Figure 1-2 on page 3, Table 1-1 on page 3. Updated “” on page 46. Updated “Power Management and Sleep Modes” on page 52. Updated note for Table 12-1 on page 68. Updated Figure 26-9 on page 285 and Figure 26-10 on page 285.
ATmega640/1280/1281/2560/2561 9. 10. 11. 12. 13. 14. Updated Note for Table 4 on page 43, Table 13-15 on page 86, Table 26-3 on page 289 and Table 26-6 on page 295. Updated Table 31-9 on page 377 and Table 31-10 on page 378. Updated “Filling the Temporary Buffer (Page Loading)” on page 323. Updated “Typical Characteristics” on page 385. Updated “Packaging Information” on page 424. Updated “Errata” on page 428. 38.13 Rev. 2549C-09/05 1. 2. 3. 4. 5. 6. 7. 8.
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg.
ATmega640/1280/1281/2560/2561 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 5 2.1 Block Diagram ...................................................................................................5 2.
ATmega640/1280/1281/2560/2561 10.2 Clock Systems and their Distribution ...............................................................40 10.3 Clock Sources .................................................................................................41 10.4 Low Power Crystal Oscillator ...........................................................................42 10.5 Full Swing Crystal Oscillator ............................................................................44 10.
ATmega640/1280/1281/2560/2561 14.1 Interrupt Vectors in ATmega640/1280/1281/2560/2561 ................................105 14.2 Reset and Interrupt Vector placement ...........................................................107 14.3 Moving Interrupts Between Application and Boot Section .............................109 14.4 Register Description ......................................................................................110 15 External Interrupts .............................................
ATmega640/1280/1281/2560/2561 19 Output Compare Modulator (OCM1C0A) ........................................... 172 19.1 Overview ........................................................................................................172 19.2 Description .....................................................................................................172 20 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 174 20.1 Overview ..............................................................
ATmega640/1280/1281/2560/2561 24 2-wire Serial Interface .......................................................................... 241 24.1 Features ........................................................................................................241 24.2 2-wire Serial Interface Bus Definition ............................................................241 24.3 Data Transfer and Frame Format ..................................................................242 24.
ATmega640/1280/1281/2560/2561 28.3 Data Registers ...............................................................................................302 28.4 Boundary-scan Specific JTAG Instructions ...................................................304 28.5 Boundary-scan Chain ....................................................................................305 28.6 Boundary-scan Related Register in I/O Memory ...........................................308 28.
ATmega640/1280/1281/2560/2561 32.1 Active Supply Current ....................................................................................385 32.2 Idle Supply Current ........................................................................................388 32.3 Power-down Supply Current ..........................................................................392 32.4 Power-save Supply Current ...........................................................................393 32.
ATmega640/1280/1281/2560/2561 37.9 ATmega2560 rev. D ......................................................................................430 37.10 ATmega2560 rev. C ......................................................................................430 37.11 ATmega2560 rev. B .......................................................................................430 37.12 ATmega2560 rev. A .......................................................................................431 37.
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 16F, Shin-Osaki Kangyo Bldg.
