Datasheet

21
8011GS–AVR–08/07
ATmega164P/324P/644P
10. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
10.1 Rev. 8011G- 08/07
10.2 Rev. 8011F- 04/07
10.3 Rev. 8011E - 04/07
1. Updated ”Features” on page 1
2. Added ”Data Retention” on page 8.
3. Updated ”SPH and SPL – Stack Pointer High and Stack pointer Low” on page 14.
4. LCD reference removed from table note in ”Sleep Modes” on page 42.
5. Updated code example in ”Bit 0 – IVCE: Interrupt Vector Change Enable” on page 65.
6. Removed reference to External Memory Interface in ”Alternate Functions of Port A” on
page 80.
7. Updated ”Data Reception – The USART Receiver” on page 180.
8. Updated ”ADCSRB – ADC Control and Status Register B” on page 238.
9. Updated overview in ”ADC - Analog-to-digital Converter” on page 240.
10. Added ”ATmega644P Typical Characteristic” on page 388.
11. Updated Figure 28-31 on page 354, Figure 28-32 on page 355,Figure 28-33 on page
355
12. Updated notes in Table 8-3 on page 32.Table 8-8 on page 35, Table 8-9 on page 36,
and Table 8-11 on page 37.
13. Updated Table 13-7 on page 84, Table 13-8 on page 84, Table 13-10 on page 86,
Table 13-11 on page 87, Table 13-14 on page 90, Table 27-1 on page 327,Table 27-2
on page 327,Table 27-5 on page 330, Table 27-9 on page 332, and Table 27-12 on
page 336
14. Updated ”ATmega324P DC Characteristics” on page 327 and ”ATmega644P DC Char-
acteristics” on page 328.
15. Updated Table 27-7 on page 331 and Table 8-13 on page 37.
1. Updated ”Watchdog Timer Configuration” on page 59.
1. Updated ”GTCCR – General Timer/Counter Control Register” on page 159.
2. Updated ”EECR – The EEPROM Control Register” on page 23.