Datasheet

14
8011O–AVR–07/10
ATmega164P/324P/644P
4.5.1 SPH and SPL – Stack Pointer High and Stack pointer Low
Note: 1. Initial values respectively for the ATmega164P/324P/644P.
4.5.2 RAMPZ – Extended Z-pointer Register for ELPM/SPM
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in Figure 4-4. Note that LPM is not affected by the RAMPZ setting.
Figure 4-4. The Z-pointer used by ELPM and SPM
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
4.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
CPU
, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 4-5 on page 15 shows the parallel instruction fetches and instruction executions enabled
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Bit 151413121110 9 8
0x3E (0x5E) – – – SP12 SP11 SP10 SP9 SP8 SPH
0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R R R R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0/0/1
(1)
0/1/0
(1)
1/0/0
(1)
00
11111111
Table 4-2. Stack Pointer size
Device Stack Pointer size
ATmega164P SP[10:0]
ATmega324P SP[11:0]
ATmega644P SP[12:0]
Bit 765432 1 0
0x3B (0x5B)
RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0
RAMPZ
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value000000 0 0
Bit (Individually) 7 0 7 0 7 0
RAMPZ ZH ZL
Bit (Z-pointer) 23 16 15 8 7 0