Datasheet

334
8011O–AVR–07/10
ATmega164P/324P/644P
Notes: 1. In ATmega164P/324P/644P, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100 kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega32 Two-wire Serial Interface operation. Other devices connected to the Two-wire
Serial Bus need only obey the general fSCL requirement.
6. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater
than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.
7. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time require-
ment will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega32 devices connected to the bus may
communicate at full speed (400 kHz) with other ATmega32 devices, as well as any other device with a proper tLOW accep-
tance margin.
Figure 25-6. 2-wire Serial Bus Timing
t
HD;STA
Hold Time (repeated) START Condition
f
SCL
≤ 100 kHz 4.0 –
µs
f
SCL
> 100 kHz 0.6 –
t
LOW
Low Period of the SCL Clock
f
SCL
≤ 100 kHz
(6)
4.7 –
f
SCL
> 100 kHz
(7)
1.3 –
t
HIGH
High period of the SCL clock
f
SCL
≤ 100 kHz 4.0 –
f
SCL
> 100 kHz 0.6 –
t
SU;STA
Set-up time for a repeated START condition
f
SCL
≤ 100 kHz 4.7 –
f
SCL
> 100 kHz 0.6 –
t
HD;DAT
Data hold time
f
SCL
≤ 100 kHz 0 3.45
f
SCL
> 100 kHz 0 0.9
t
SU;DAT
Data setup time
f
SCL
≤ 100 kHz 250 –
ns
f
SCL
> 100 kHz 100 –
t
SU;STO
Setup time for STOP condition
f
SCL
≤ 100 kHz 4.0 –
µs
f
SCL
> 100 kHz 0.6 –
t
BUF
Bus free time between a STOP and START
condition
f
SCL
≤ 100 kHz 4.7 –
f
SCL
> 100 kHz 1.3 –
Table 25-10. 2-wire Serial Bus Requirements (Continued)
Symbol Parameter
Condition Min Max Units
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r