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Table Of Contents

Class-D Audio Power Amplifier

ADAU1592

Rev. A

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FEATURES

Integrated stereo modulator and power stage

0.005% THD + N

101 dB dynamic range

PSRR > 65 dB

DS-ON

< 0.3 Ω (per transistor)

Efficiency > 90% (8 Ω)

EMI-optimized modulator

On/off-mute pop-noise suppression

Short-circuit protection

Overtemperature protection

APPLICATIONS

Flat panel televisions

PC audio systems

Mini-components

GENERAL DESCRIPTION

The ADAU1592 is a 2-channel, bridge-tied load (BTL)

switching audio power amplifier with an integrated Σ-

modulator.

The modulator accepts an analog input signal and generates

a switching output to drive speakers directly. A digital,

microcontroller-compatible interface provides control of reset,

mute, and PGA gain as well as output signals for thermal and

overcurrent error conditions. The output stage can operate

from supply voltages ranging from 9 V to 18 V. The analog

modulator and digital logic operate from a 3.3 V supply.

FUNCTIONAL BLOCK DIAGRAM

PVDD

OUTL+

PGND

PVDD

OUTL–

PGND

PVDD

OUTR+

PGND

PVDD

OUTR–

PGND

LEVEL SHIFT

AND DEAD

TIME CONTROL

Σ-Δ

MODULATOR

TEMPERATURE/

OVERCURRENT

PROTECTION

MODE CONTROL

LOGIC

CLOCK

OSCILLATOR

PGA

ADAU1592

CLK

VOLTAGE

REFERENCE

PGA

SLICER

AINL

SLC_TH

PGA0 PGA1

AINR

VREF

AVDD

AGND

DVDD

DGND

OTWXTOXTI ERRMUTESTDN

MO/ST

06749-001

Figure 1.

Summary of content (24 pages)

PAGE 1
Class-D Audio Power Amplifier ADAU1592 FEATURES GENERAL DESCRIPTION Integrated stereo modulator and power stage 0.005% THD + N 101 dB dynamic range PSRR > 65 dB RDS-ON < 0.3 Ω (per transistor) Efficiency > 90% (8 Ω) EMI-optimized modulator On/off-mute pop-noise suppression Short-circuit protection Overtemperature protection The ADAU1592 is a 2-channel, bridge-tied load (BTL) switching audio power amplifier with an integrated Σ-Δ modulator.
PAGE 2
ADAU1592 TABLE OF CONTENTS Features .............................................................................................. 1 Power Stage ................................................................................. 16 Applications....................................................................................... 1 Gain.............................................................................................. 16 General Description ......................................................
PAGE 3
ADAU1592 SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, PVDD = 15 V, ambient temperature = 25°C, load impedance = 6 Ω, clock frequency = 24.576 MHz, measurement bandwidth = 20 Hz to 20 kHz, unless otherwise specified. AUDIO PERFORMANCE Table 1.
PAGE 4
ADAU1592 DC SPECIFICATIONS Table 2. Parameter INPUT IMPEDANCE OUTPUT DC OFFSET VOLTAGE Min Typ 20 ±3 Max Unit kΩ mV Test Conditions/Comments AINL/AINR Min 3.0 3.0 9 Typ 3.3 3.3 15 Max 3.6 3.6 18 Unit V V V Test Conditions/Comments 5 0.1 0.082 60 0.24 0.25 μA mA mA 13 1.7 5.4 20 3.2 8 mA mA mA POWER SUPPLIES Table 3.
PAGE 5
ADAU1592 DIGITAL TIMING Table 5. Parameter tWAIT tINT tHOLD tOUTx+/OUTx− SW tOUTx+/OUTx− MUTE Min 0.01 1 101 Typ 1000 2 650 250 3 200 200 Unit ms ms μs μs μs Test Conditions/Comments Wait time for unmute Internal mute time Wait time for shutdown Time delay after MUTE held high until output starts switching Time delay after MUTE held low until output stops switching 1 tWAIT MIN and tHOLD MIN are the minimum times for fast turn-on and do not guarantee pop-and-click suppression.
PAGE 6
ADAU1592 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter DVDD to DGND AVDD to AGND PVDD to PGND1 MUTE/STDN Inputs Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +20.0 V DGND − 0.3 V to DVDD + 0.
PAGE 7
ADAU1592 48 47 46 45 44 43 42 41 40 39 38 37 PGND PGND PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PGND PGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADAU1592 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 OUTR– OUTR– OUTR– OUTR+ OUTR+ OUTR+ TEST13 TEST12 AINR AINL TEST9 TEST8 NOTES 1. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO PGND, DGND, AND AGND FOR TQFP-48. 2. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO PGND AND DGND FOR LFCSP-48.
PAGE 8
ADAU1592 Pin Number 34, 35, 36 37, 38, 47, 48 39, 40, 41, 42, 43, 44, 45, 46 1 Mnemonic OUTR− PGND PVDD Type 1 O P P Description Output of High Power Transistors, Right Channel Negative Polarity. Power Ground for High Power Transistors. Internally connected to ePAD. Positive Power Supply for High Power Transistors. I = input, O = output, P = power. Rev.
PAGE 9
ADAU1592 0 –10 –20 –20 –30 –30 –40 –50 THD + N –80 –90 –100 –110 –110 100m 1 10 –20 –20 –30 –30 THD OR THD + N (dB) 0 –10 –40 –50 –60 THD + N –80 –90 –50 –60 –70 THD + N –80 THD –100 –110 100m 1 10 OUTPUT POWER (W) –120 10m 06749-006 –120 10m 100m 1 10 OUTPUT POWER (W) Figure 9. THD or THD + N vs. Output Power, 6 Ω, PVDD = 12 V Figure 6. THD or THD + N vs.
PAGE 10
ADAU1592 0 30 POWER LIMITED DUE TO PACKAGE DISSIPATION –10 –20 25 4Ω OUTPUT POWER (W) THD OR THD + N (dB) –30 –40 –50 –60 –70 THD + N –80 –90 20 6Ω 15 8Ω 10 THD –100 5 100m 1 10 OUTPUT POWER (W) 0 06749-011 –120 10m 9 10 11 12 13 14 15 16 17 Figure 11. THD or THD + N vs. Output Power, 4 Ω, PVDD = 15 V Figure 14. Output Power vs. PVDD @ 0.
PAGE 11
ADAU1592 0 –10 –20 –30 –40 –30 –40 –50 –50 –60 –70 –60 –70 OUTPUT (dBr) –20 –80 –90 –100 –140 –150 –140 –150 0 2 4 6 8 10 12 14 16 18 20 Figure 17.
PAGE 12
0 –10 –20 –40 OUTPUT (dBr) –50 –60 –70 –80 THD + N –90 –100 THD 100 1k 10k FREQUENCY (Hz) Figure 23. THD or THD + N vs. Frequency @ 1 W, 4 Ω, PVDD = 15 V, PGA = 0 dB 41 39 –20 35 33 –40 GAIN (dB) THD OR THD + N (dB) PGA 18dB 37 –30 –50 –60 –70 –80 PGA 12dB 31 29 27 PGA 6dB 25 23 THD + N –90 21 –100 PGA 0dB 19 THD 17 100 1k 10k FREQUENCY (Hz) 15 20 06749-024 –110 100 1k 10k FREQUENCY (Hz) Figure 24. THD or THD + N vs.
PAGE 13
ADAU1592 90 12 POWER LIMITED DUE TO PACKAGE DISSIPATION 11 80 10 POWER DISSIPATION (W) EFFICIENCY (%) 70 60 50 40 30 20 9 8 7 6 5 4 3 2 10 5 10 15 20 25 30 OUTPUT POWER (W) 0 06749-029 0 Figure 29. Efficiency vs. Output Power, 15 V, 4 Ω 0 5 10 15 20 25 OUTPUT POWER PER CHANNEL, STEREO MODE (W) 06749-032 1 POWER LIMITED DUE TO PACKAGE DISSIPATION 0 Figure 32. Power Dissipation vs.
PAGE 14
ADAU1592 30 6 3Ω OUTPUT POWER (W) 5 3 2 8Ω 15 10 5 1 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 06749-035 0 TAMBIENT (°C) 11 10 12 13 14 15 16 17 18 Figure 38. Output Power vs. PVDD, Mono Mode, 60 dB THD + N 40 90 POWER LIMITED DUE TO PACKAGE DISSIPATION 35 POWER LIMITED DUE TO PACKAGE DISSIPATION 9 PVDD (V) Figure 35. Power Dissipation Derating vs.
PAGE 15
ADAU1592 THEORY OF OPERATION The Σ-Δ modulators require feedback to generate PDM stream with respect to the input. The feedback for the modulators comes from the power stage. This helps reduce the nonlinearity in the power stages and achieve excellent THD + N performance. The feedback also helps in achieving good PSRR. In the ADAU1592, the feedback from the power stage is internally connected. This helps reduce the external connections for ease in PCB layout.
PAGE 16
ADAU1592 GAIN VCM The gain of the amplifier is set internally using feedback resistors optimized for 15 V nominal operation. The typical gain values are tabulated in Table 1. The typical gain is 19 dB with PGA set to 0 dB. PGA0 (Pin 14) and PGA1 (Pin 13) are used for setting the desired gain. 50kΩ SLICER_LEVEL VTH PIN 24 (SLC_TH) The gain can be set according to Table 10. Note that the amplifier full-scale input level changes as per the PGA gain setting. REXTERNAL 06749-043 Table 10.
PAGE 17
ADAU1592 on the outputs after the LC filter. Typical short-circuit conditions include shorting of the output load and shorting to either PVDD or PGND. This option allows device operation that is safely below the shutdown temperature of 150°C and allows the amplifier to recover itself without the need for microcontroller intervention. UNDERVOLTAGE PROTECTION Option 2: Using ERR The ADAU1592 is also comprised of an undervoltage protection circuit, which senses the undervoltage on PVDD.
PAGE 18
ADAU1592 AVDD/DVDD POWER-UP/POWER-DOWN SEQUENCE Figure 46 shows the recommended power-up sequence for the ADAU1592. PVDD AVDD/DVDD STDN tINT PVDD INTERNAL MUTE tWAIT MUTE STDN tINT PVDD/2 OUTx+/OUTx– INTERNAL MUTE tPDL-H tWAIT AVDD/2 AINx MUTE NOTES 1. INTERNAL MUTE IS INTERNAL TO CHIP. AVDD/2 AINx NOTES 1. INTERNAL MUTE IS INTERNAL TO CHIP. Figure 47. Power-Up Sequence, tWAIT < tINT 06749-046 tINT = 650ms @ 24.
PAGE 19
ADAU1592 To shut down the power supplies to save power, it is highly recommended to mute the amplifier before shutting down any of the supplies. To achieve this, first pull down MUTE, then shut down the power supplies in the following order: PVDD, DVDD, and then AVDD. Where AVDD and DVDD are generated from a single source, shut down PVDD before shutting down DVDD and AVDD, and after issuing MUTE. DC OFFSET AND POP NOISE This section describes the cause of dc offset and pop noise during turn-on/turn-off.
PAGE 20
ADAU1592 capacitors must be placed very close to their respective pins with direct connection. This is important for reliable and safe operation of the device. One additional 1 μF capacitor in parallel to the 100 nF capacitor is also recommended. A bulk bypass capacitor of 470 μF is also recommended to remove the low frequency ripple due to load current. The ADAU1592 uses 24.576 MHz for the master clock, which is 512 × fS (fS = 48 kHz). There are several options for providing the clock.
PAGE 21
ADAU1592 APPLICATIONS INFORMATION For applications with PVDD > 15 V, add components R1 and R2 (10 Ω typical), C5 and C6 (680 pF typical), and D1 through D8 (CRS01/02). 3.3V ANALOG INPUT LEFT 100nF 100nF 1µF 470µF DVDD PVDD 100nF AVDD TEST3 100nF PVDD PVDD 2.2µF AINL 100kΩ L1 D1 OUTL+ R1 10Ω D2 PVDD SLC_TH OUTL– R3 C5 680pF D3 C1 L2 D4 C2 PVDD VREF 4.7µF OUTR+ 100nF L3 D5 R2 10Ω D6 ADAU1592 ANALOG INPUT RIGHT PVDD 2.
PAGE 22
ADAU1592 For applications with PVDD > 15 V, add components R1 (10 Ω typical), C5 (680 pF typical), and D1 through D4 (CRS01/02). 3.3V ANALOG INPUT LEFT 100nF 100nF 1µF 470µF PVDD 100nF DVDD AVDD TEST3 MO/ST 100nF PVDD PVDD 2.2µF AINL 100kΩ OUTL+ L1 D1 D2 R1 10Ω PVDD SLC_TH OUTL– R3 D3 C5 680pF C1 L2 D4 C2 VREF 4.7µF OUTR+ 100nF ADAU1592 ANALOG INPUT RIGHT 2.
PAGE 23
ADAU1592 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 48 1 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 12 13 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 0.60 MAX 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF SEATING PLANE COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 51.