Specifications
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- TABLE OF CONTENTS
- REVISION HISTORY
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- THEORY OF OPERATION
- OVERVIEW
- MODULATOR
- SLICER
- POWER STAGE
- GAIN
- PROTECTION CIRCUITS
- THERMAL PROTECTION
- OVERCURRENT PROTECTION
- UNDERVOLTAGE PROTECTION
- CLOCK LOSS DETECTION
- AUTOMATIC RECOVERY FROM PROTECTIONS
- MUTE AND STDN
- POWER-UP/POWER-DOWN SEQUENCE
- DC OFFSET AND POP NOISE
- SELECTING VALUES FOR CREF AND CIN
- MONO MODE
- POWER SUPPLY DECOUPLING
- EXTERNAL PROTECTION FOR PVDD > 15 V
- CLOCK
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS

ADAU1592
Rev. A | Page 10 of 24
06749-011
OUTPUT POWER (W)
THD OR THD + N (dB)
–120
0
–10
–20
–110
–100
–90
–80
–70
–60
–50
–40
–30
10m 10100m 1
THD + N
THD
Figure 11. THD or THD + N vs. Output Power, 4 Ω, PVDD = 15 V
06749-012
OUTPUT POWER (W)
THD OR THD + N (dB)
–120
0
–10
–20
–110
–100
–90
–80
–70
–60
–50
–40
–30
10m 10100m 1
THD + N
THD
Figure 12. THD or THD + N vs. Output Power, 6 Ω, PVDD = 15 V
0
6749-013
OUTPUT POWER (W)
THD OR THD + N (dB)
–120
0
–10
–20
–110
–100
–90
–80
–70
–60
–50
–40
–30
10m 10100m 1
THD + N
THD
Figure 13. THD or THD + N vs. Output Power, 8 Ω, PVDD = 15 V
0
6749-014
PVDD (V)
OUTPUT POWER (W)
0
30
25
5
10
15
20
18910 1211 1413 16 1715
6Ω
POWER LIMITED DUE TO PACKAGE DISSIPATION
4Ω
8Ω
Figure 14. Output Power vs. PVDD @ 0.1% THD + N
06749-015
PVDD (V)
OUTPUT POWER (W)
0
30
25
5
10
15
20
18910 1211 1413 16 1715
6Ω
4Ω
8Ω
POWER LIMITED DUE TO PACKAGE DISSIPATION
Figure 15. Output Power vs. PVDD @ 1% THD + N
06749-016
PVDD (V)
OUTPUT POWER (W)
0
40
35
5
10
15
20
18910 1211 1413 16 1715
30
25
4Ω
8Ω
6Ω
POWER LIMITED DUE TO PACKAGE DISSIPATION
Figure 16. Output Power vs. PVDD @ 10% THD + N










