Specifications
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- TABLE OF CONTENTS
- REVISION HISTORY
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- THEORY OF OPERATION
- OVERVIEW
- MODULATOR
- SLICER
- POWER STAGE
- GAIN
- PROTECTION CIRCUITS
- THERMAL PROTECTION
- OVERCURRENT PROTECTION
- UNDERVOLTAGE PROTECTION
- CLOCK LOSS DETECTION
- AUTOMATIC RECOVERY FROM PROTECTIONS
- MUTE AND STDN
- POWER-UP/POWER-DOWN SEQUENCE
- DC OFFSET AND POP NOISE
- SELECTING VALUES FOR CREF AND CIN
- MONO MODE
- POWER SUPPLY DECOUPLING
- EXTERNAL PROTECTION FOR PVDD > 15 V
- CLOCK
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS
ADAU1592
Rev. A | Page 14 of 24
06749-038
PVDD (V)
OUTPUT POWER (W)
0
30
25
5
10
15
20
911211 1413 1615
8
10 17
4Ω
3Ω
8Ω
6Ω
POWER LIMITED DUE TO PACKAGE DISSIPATION
0
1
2
3
4
5
6
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160
P
DISS
MAX (W)
06749-035
T
AMBIENT
(°C)
Figure 35. Power Dissipation Derating vs. Ambient Temperature
Figure 38. Output Power vs. PVDD, Mono Mode, 60 dB THD + N
0
5
10
15
20
25
30
35
40
3Ω
06749-036
PVDD (V)
OUTPUT POWER (W)
9181211 1413 1615
6Ω
10 17
4Ω
8Ω
POWER LIMITED DUE TO PACKAGE DISSIPATION
Figure 36. Output Power vs. PVDD, Mono Mode, 20 dB THD + N
06749-037
PVDD (V)
OUTPUT POWER (W)
0
30
25
5
10
15
20
91
81211 1413 1615
10 17
4Ω
3Ω
8Ω
6Ω
POWER LIMITED DUE TO PACKAGE DISSIPATION
Figure 37. Output Power vs. PVDD, Mono Mode, 40 dB THD + N
EFFICIENCY (%)
06749-039
OUTPUT POWER (W)
0
10
20
30
40
50
60
70
80
90
0246810121416182022242628 36343230
POWER LIMITED DUE TO PACKAGE DISSIPATION
Figure 39. Efficiency vs. Output Power, Mono Mode, 15 V, 3 Ω
EFFICIENCY (%)
06749-040
OUTPUT POWER (W)
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
0
10
20
30
40
50
60
70
80
90
Figure 40. Efficiency vs. Output Power, Mono Mode, 15 V, 4 Ω