Specifications
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- TABLE OF CONTENTS
- REVISION HISTORY
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- THEORY OF OPERATION
- OVERVIEW
- MODULATOR
- SLICER
- POWER STAGE
- GAIN
- PROTECTION CIRCUITS
- THERMAL PROTECTION
- OVERCURRENT PROTECTION
- UNDERVOLTAGE PROTECTION
- CLOCK LOSS DETECTION
- AUTOMATIC RECOVERY FROM PROTECTIONS
- MUTE AND STDN
- POWER-UP/POWER-DOWN SEQUENCE
- DC OFFSET AND POP NOISE
- SELECTING VALUES FOR CREF AND CIN
- MONO MODE
- POWER SUPPLY DECOUPLING
- EXTERNAL PROTECTION FOR PVDD > 15 V
- CLOCK
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS

ADAU1592
Rev. A | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
DVDD to DGND −0.3 V to +3.6 V
AVDD to AGND −0.3 V to +3.6 V
PVDD to PGND
1
−0.3 V to +20.0 V
MUTE/STDN Inputs
DGND − 0.3 V to DVDD + 0.3 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Lead Temperature
Soldering (10 sec) 260°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1
Includes any induced voltage due to inductive load.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type θ
JA
1
θ
JC
1,2
Ψ
JB
Ψ
JT
Unit
LFCSP-48 24.6 2.0 8.05 0.18 °C/W
TQFP-48 24.7 1.63 11 0.8 °C/W
1
With exposed pad (ePAD) soldered to 4-layer JEDEC standard PCB.
2
Through the bottom (ePAD) surface.
ESD CAUTION










