Specifications

ADAU1592
Rev. A | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06749-004
13 14 15 16 17 18 19 20 21 22 23 24
PGA1 PGA0
MUTE
STDN
XTI
XTO
DGND
DVDD AVDD
AGND
VREF
SLC_TH
48 47 46 45 44 43 42 41 40 39 38 37
PGND PGND PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PGND PGND
1
2
3
4
5
6
7
8
9
10
11
12
OUTL–
OUTL–
OUTL–
OUTL+
OUTL+
OUTL+
TEST1
TEST0
OTW
MO/ST
TEST3
OUTR–
OUTR–
OUTR+
OUTR+
OUTR+
TEST13
TEST12
AINR
AINL
TEST9
TEST8
35
OUTR–36
34
33
32
31
30
29
28
27
26
25
ADAU1592
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
ERR
NOTES
1. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO
PGND, DGND, AND AGND FOR TQFP-48.
2. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO
PGND AND DGND FOR LFCSP-48.
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin Number Mnemonic Type
1
Description
1, 2, 3 OUTL− O Output of High Power Transistors, Left Channel Negative Polarity.
4, 5, 6 OUTL+ O Output of High Power Transistors, Left Channel Positive Polarity.
7 TEST1 I Reserved for Internal Use. Connect to DGND.
8 TEST0 I Reserved for Internal Use. Connect to DGND.
9
ERR
O Error Indicator (Active Low, Open-Drain Output).
10
OTW
O Overtemperature Warning Indicator (Active Low, Open-Drain Output).
11
MO/
ST
I Mono/Stereo Mode Setting Pin for Stereo. Connect to DGND (for mono mode, connect to DVDD).
12 TEST3 I Reserved for Internal Use. Connect to DVDD.
13 PGA1 I Programmable Gain Amplifier Select, MSB.
14 PGA0 I Programmable Gain Amplifier Select, LSB.
15
MUTE
I Mute (Active Low Input).
16
STDN
I Shutdown/Reset Input (Active Low Input).
17 XTI I Quartz Crystal Connection/External Clock Input.
18 XTO O Quartz Crystal Connection/Clock Output.
19 DGND P Digital Ground for Digital Circuitry. Internally connected to exposed pad (ePAD).
20 DVDD P Positive Supply for Digital Circuitry.
21 AVDD P Positive Supply for Analog Circuitry. (Can be tied to DVDD.)
22 AGND P Analog Ground for Analog Circuitry. (See the notes in Figure 4 for connection to ePAD.)
23 VREF I AVDD/2 Voltage Reference Connection for External Filter.
24 SLC_TH I Slicer Threshold Adjust. (Connect to AGND via a resistor for slicer operation.)
25 TEST8 I Reserved for Internal Use. Connect to DGND.
26 TEST9 I Reserved for Internal Use. Connect to DGND.
27 AINL I Analog Input Left Channel.
28 AINR I Analog Input Right Channel.
29 TEST12 I Reserved for Internal Use. Connect to DGND.
30 TEST13 I Reserved for Internal Use. Connect to DGND.
31, 32, 33 OUTR+ O Output of High Power Transistors, Right Channel Positive Polarity.