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FEATURES

APPLICATIONS

DESCRIPTION

TLV320AIC34

SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007

FOUR-CHANNEL, LOW-POWER AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY

• Digital Microphone Input Support

234

• Four-Channel Audio DAC • Concurrent Digital Microphone and Analog

Microphone Support Available

– 102-dBA Signal-to-Noise Ratio

• Extensive Modular Power Control

– 16/20/24/32-Bit Data

• Power Supplies:

– Supports Rates From 8 kHz to 96 kHz

– Analog: 2.7 V – 3.6 V

– 3D/Bass/Treble/EQ/De-Emphasis Effects

– Digital Core: 1.65 V – 1.95 V

– Flexible Power Saving Modes and

Performance Are Available – Digital I/O: 1.1 V – 3.6 V

• Four-Channel Audio ADC • Package: 6-mm × 6-mm 87-BGA

– 92-dBA Signal-to-Noise Ratio

– Supports Rates From 8 kHz to 96 kHz

• Digital Cameras

– Digital Signal Processing and Noise

• Smart Cellular Phones

Filtering Available During Record

• Twelve Audio Inputs

– Programmable in Single-Ended or Fully

The TLV320AIC34 is a low-power four-channel audio

Differential Configurations

codec with four-channel headphone amplifier, as well

– 3-State Capability for Floating Input

as multiple inputs and outputs programmable in

Configurations

single-ended or fully differential configurations.

Extensive register-based power control is included,

• Fourteen Audio Output Drivers

enabling four-channel 48-kHz DAC playback as low

– Stereo 8- Ω , 500-mW/Channel Speaker Drive

as 15 mW from a 3.3-V analog supply, making it ideal

Capability

for portable battery-powered audio and telephony

– Multiple Fully Differential or Single-Ended

applications.

Headphone Drivers

The record path of the TLV320AIC34 contains

– Multiple Fully Differential or Single-Ended

integrated microphone bias, digitally controlled

Line Outputs

four-channel microphone preamplifier, and automatic

gain control (AGC), with mix/mux capability among

– Fully Differential Mono Outputs

the multiple analog inputs. Programmable filters are

• Low Power: 15-mW Stereo 48-kHz Playback

available during record which can remove audible

With 3.3-V Analog Supply

noise that can occur during optical zooming in digital

• Ultralow-Power Mode With Passive Analog

cameras. The playback path includes mix/mux

Bypass

capability from the four-channel DAC and selected

inputs, through programmable volume controls, to the

• Programmable Input/Output Analog Gains

various outputs.

• Automatic Gain Control (AGC) for Record

• Programmable Microphone Bias Level

• Dual Programmable PLLs for Flexible Clock

Generation

• I

C Control Bus

• Dual Audio Serial Data Busses

– Support I

S, Left/Right-Justified, DSP, PCM,

and TDM Modes

– Enable Asynchronous Simultaneous

Operation of Busses and Data Converters

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 MicroStar Junior is a trademark of Texas Instruments.

3 Bluetooth is a trademark of Bluetooth SIG, Inc.

4 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (98 pages)

PAGE 1
TLV320AIC34 SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 FOUR-CHANNEL, LOW-POWER AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY FEATURES 1 • Four-Channel Audio DAC – 102-dBA Signal-to-Noise Ratio – 16/20/24/32-Bit Data – Supports Rates From 8 kHz to 96 kHz – 3D/Bass/Treble/EQ/De-Emphasis Effects – Flexible Power Saving Modes and Performance Are Available • Four-Channel Audio ADC – 92-dBA Signal-to-Noise Ratio – Supports Rates From 8 kHz to 96 kHz – Digital Signal Proces
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TLV320AIC34 SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The TLV320AIC34 contains eight high-power output drivers as well as six line-level output drivers.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 AVDD_DAC AVSS_DAC DRVDD DRVSS AVSS_ADC DVDD DVSS IOVDD RESETB_A GPIO1_A GPIO2_A ADDR_A MICDET_A MICBIAS_A MCLK_A DIN_A DOUT_A BCLK_A WCLK_A SCL SDA SIMPLIFIED BLOCK DIAGRAM Voltage Supplies Reset, GPIO Bias, Detect Audio Serial Data Bus A I C Serial Control Bus 2 Block A Codec HPLOUT_A LINE2LP_A LINE2LM_A HPLCOM_A MIC3L_A LINE1LP_A LINE1LM_A LINE1RP_A LINE1RM_A PGA 0/+59.5dB 0.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 TERMINAL ASSIGNMENTS ZAS Package (Top View) A B C D E F G H J K L 1 2 3 4 5 6 7 8 9 10 11 P0061-01 Table 1. TERMINAL FUNCTIONS, ALPHABETIC TERMINAL NAME BGA BALL I/O DESCRIPTION ADDR_A L7 I I2C address control A ADDR_B L8 I I2C address control B AVDD_DAC B3 – Analog DAC voltage supply, 2.7 V–3.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Table 1. TERMINAL FUNCTIONS, ALPHABETIC (continued) TERMINAL NAME BGA BALL I/O DESCRIPTION HPRCOM_B A6 O High-power output driver (right minus or multifunctional) B HPROUT_A B5 O High-power output driver (right plus) A, capable of driving 8-Ω load HPROUT_B A5 O High-power output driver (right plus) B H7, K7 – I/O voltage supply, 1.1 V–3.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Table 1. TERMINAL FUNCTIONS, ALPHABETIC (continued) TERMINAL NAME BGA BALL I/O DESCRIPTION WCLK_A K4 I/O Audio serial data bus word clock (input/output) A WCLK_B L3 I/O Audio serial data bus word clock (input/output) B Table 2.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Table 2.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE UNIT DRVDD to AVSS_ADC, AVDD_DAC to AVSS_DAC –0.3 to 3.9 V DRVDD to DRVSS –0.3 to 3.9 V IOVDD to DVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.5 V AVDD_DAC to DRVDD –0.1 to 0.1 V –0.3 to IOVDD + 0.3 V Digital input voltage to DVSS Analog input voltage to AVSS_ADC, AVSS_DAC –0.3 to AVDD_DAC + 0.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 ELECTRICAL CHARACTERISTICS At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48-kHz, 16-bit audio data (unless otherwise noted) TEST CONDITIONS MIN TYP MAX UNIT ADC DIGITAL DECIMATION FILTER, fS = 48 kHz, Codec Block A, B Filter gain from 0 to 0.39 fS Filter gain at 0.4125 fS Filter gain at 0.45 fS Filter gain at 0.5 fS Filter gain from 0.55 fS to 64 fS Filter group delay ±0.1 dB –0.25 dB –3 dB –17.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48-kHz, 16-bit audio data (unless otherwise noted) TEST CONDITIONS MIN TYP MAX UNIT AUDIO DAC – SINGLE-ENDED HEADPHONE OUTPUT, Load = 16 Ω, Codec Block A, B 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 0.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48-kHz, 16-bit audio data (unless otherwise noted) TEST CONDITIONS MIN TYP MAX UNIT POWER CONSUMPTION, DRVDD, AVDD_DAC = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V Currents Listed are for Codec Block A or Block B.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS (FOR A AND B INTERFACES) All specifications at 25°C, DVDD = 1.8 V WCLK_x td(WS) BCLK_x td(DO-WS) td(DO-BCLK) DOUT_x tS(DI) th(DI) DIN_x T0145-04 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 All specifications at 25°C, DVDD = 1.8 V WCLK_x td(WS) td(WS) BCLK_x td(DO-BCLK) DOUT_x tS(DI) th(DI) DIN_x T0146-03 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 All specifications at 25°C, DVDD = 1.8 V WCLK_x tS(WS) th(WS) tH(BCLK) BCLK_x td(DO-WS) tL(BCLK) td(DO-BCLK) DOUT_x tS(DI) th(DI) DIN_x T0145-05 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 All specifications at 25°C, DVDD = 1.8 V WCLK_x tS(WS) tS(WS) th(WS) th(WS) tL(BCLK) BCLK_x td(DO-BCLK) tH(BCLK) DOUT_x tS(DI) th(DI) DIN_x T0146-04 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs HEADPHONE OUT POWER SIGNAL-TO-NOISE RATIO vs ADC PGA SETTING 45 0 2.7 VDD_CM 1.35_LDAC 40 3.6 VDD_CM 1.8_LDAC -20 SNR - Signal-To-Noise - dB THD - Total Harmonic Distortion - dB -10 3.3 VDD_CM1.65_LDAC 2.7 VDD_CM 1.35_RDAC -30 -40 3.3 VDD_CM 1.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) LEFT-DAC FFT 0 Load = 10 kW, FS = 48 kHz, fs = 64 kHz, 4096 Samples, AVDD = DRVDD = 3.3 V, Amplitude - dB -20 -40 -60 -80 -100 -120 -140 -160 0 1 2 3 4 5 6 7 8 9 10 11 12 f - Frequency - kHz 13 14 15 16 17 18 19 20 Figure 9. RIGHT-DAC FFT 0 Load = 10 kW, FS = 48 kHz, fs = 64 kHz, AVDD = DRVDD = 3.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) RIGHT-ADC FFT 0 Load = 10 kW, FS = 48 kHz, fs = 64 kHz, 2048 Samples, AVDD = DRVDD = 3.3 V, Amplitude - dB -20 -40 -60 -80 -100 -120 -140 -160 0 1 2 3 4 5 6 7 8 9 10 11 12 13 f - Frequency - kHz Figure 12.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) IOVDD Applications/Multimedia Processor Rp Rp 2 ADDR_A DIN_A DOUT_A BCLK_A MCLK_A WCLK_A SCL SDA RESET_A I C ADDRESS SELECT 0.47 mF LINE1LP_A LINE1LM_A FM/ Line In AVDD AVDD_ADC AVDD_DAC DRVDD DRVDD DRVDD DRVDD LINE1RP_A LINE1RM_A 0.1 mF 1 mF From Codec Block B LINE2LP_A LINE2LM_A LEFT_LOP_B LEFT_LOM_B AIC34 Codec Block A 0.1 mF 0.1 mF 0.1 mF 1 mF 1 mF 10 mF 0.1 mF 1 mF 0.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) Applications/Multimedia Processor Bluetooth Module (Mono) 2 ADDR_B MCLK_B WCLK_B BCLK_B DIN_B DOUT_B RESET_B I C ADDRESS SELECT 0.47 mF MONO_LOP_B MONO_LOM_B LINE2RP_B LINE2RM_B Analog Baseband/ Modem AIC34 Codec Block B From Codec Block A MONO_LOP_A MONO_LOM_A LINE2LP_B LINE2LM_B MICBIAS_B LEFT_LOP_B 2 kW MICDET_B Microphone LEFT_LOM_B LEFT_LOP_B LEFT_LOM_B To Codec Block A 0.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 OVERVIEW The TLV320AIC34 is a highly flexible, low-power, four-channel audio codec with extensive feature integration, intended for applications in smart phones, portable computing, communication, and entertainment applications. Available in a 6-mm × 6-mm, 87-ball BGA, the device integrates a host of features to reduce cost, board space, and power consumption in space-constrained, battery-powered, portable applications.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 I2C CONTROL MODE The TLV320AIC34 supports the I2C control protocol using 7-bit addressing and capable of both standard and fast modes. For I2C fast mode, note that the minimum timing for each of tHD-STA, tSU-STA, and tSU-STO is 0.9 µs, as seen in Figure 16. The TLV320AIC34 uses two I2C addresses, with the A channels controlled through one device address, and the B channels controlled using a different device address.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communication is taking place, the bus is active. Only master devices can start a communication. They do this by causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock line is LOW.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues an ACKNOWLEDGE, the slave takes over control of the SDA bus and transmits for the next 8 clocks the data of the next incremental register. Note that incremental read/write operation does not continue past a page boundary.
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TLV320AIC34 SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 www.ti.com The data busses of the TLV320AIC34 can be configured for left- or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 RIGHT-JUSTIFIED MODE In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock. 1/fs WCLK_x BCLK_x Right Channel Left Channel DIN_x/ DOUT_x 0 n 2 n–1 n–2 MSB 1 0 n n–1 n–2 2 1 0 LSB T0149-03 Figure 20.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 I2S MODE In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock. 1/fs WCLK_x BCLK_x 1 Clock Before MSB Right Channel Left Channel DIN_x/ DOUT_x n n–1 n–2 2 1 MSB 0 n 2 n–1 n–2 1 0 n LSB T0151-03 2 Figure 22.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 TDM DATA TRANSFER Time-division multiplexed data transfer can be realized in any of the previously mentioned transfer modes if the 256-clock bit clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 AUDIO DATA CONVERTERS The TLV320AIC34 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. As described earlier, the A and B partitions of the device can operate at entirely asynchronous sampling rates at the same time.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 MCLK_x BCLK_x GPIO2_x PLL_CLKIN CLKDIV_CLKIN CLKDIV_IN Q = 2, 3,….., 16, 17 PLL_IN (K ´ R) / P 2/Q CLKDIV_OUT K = J.D J = 1, 2, 3, ...., 62, 63 D = 0000, 0001, ...., 9998, 9999 R = 1, 2, 3, 4, ...., 15, 16 P = 1, 2, ...., 7, 8 PLL_OUT 1/8 PLLDIV_OUT CLKMUX_OUT CODEC_CLKIN CODEC_CLK = 256 ´ fS(ref) CLKOUT_IN M = 1, 2, 4, 8 N = 2, 3, ...
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK_x can be as high as 50 MHz, and fS(ref) should fall within 39 kHz to 53 kHz. When the PLL is enabled, fS(ref) = (PLLCLK_IN × K × R) / (2048 × P), where P = 1, 2, 3,…, 8 R = 1, 2, …, 16 K = J.D J = 1, 2, 3, …, 63 D = 0000, 0001, 0002, 0003, …, 9998, 9999 PLLCLK_IN can be MCLK_x or BCLK_x, selected by page 0, register 102, bits D5–D4.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 The following table lists several example cases of typical MCLK rates and how to program the PLL to achieve fS(ref) = 44.1 kHz or 48 kHz. fS(ref) = 44.1 kHz MCLK (MHz) P R J D ACHIEVED fS(ref) % ERROR 2.8224 1 1 32 0 44100.00 0.0000 5.6448 1 1 16 0 44100.00 0.0000 12.0 1 1 7 5264 44100.00 0.0000 13.0 1 1 6 9474 44099.71 –0.0007 16.0 1 1 5 6448 44100.00 0.0000 19.2 1 1 4 7040 44100.00 0.
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TLV320AIC34 SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 www.ti.com STEREO AUDIO ADC The partition of the TLV320AIC34 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode.
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TLV320AIC34 www.ti.com BCLK_x WCLK_x DIN_x DOUT_x SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 AGC DINR DINL DOUTL DOUTR Digital Audio Data Serial Interface DAC Powered Down Record Path SW-D2 Left-Channel Analog Inputs + PGA 0 dB–59.5 dB, 0.5-dB Steps Effects ADC Volume Control DAC L SW-D1 DAC Powered Down Record Path AGC SW-D4 Right-Channel Analog Inputs + PGA 0 dB–59.5 dB, 0.5-dB Steps Effects ADC SW-D3 Volume Control DAC R B0173-02 Figure 26.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It can be varied from 7 ms to 1,408 ms. The extended left-channel attack time can be programmed by writing to page 0, register 103, and the right channel is programmed by writing to page 0, register 105. Decay time determines how quickly the PGA gain is increased when the input signal is too low.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Input Signal Target Level Output Signal AGC Gain Decay Time Attack Time Figure 27. Typical Operation of the AGC Algorithm During Speech Recording Note that the time constants here are correct when the ADC is not in double-rate audio mode. The time constants are achieved using the fS(ref) value programmed in the control registers.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 DIGITAL AUDIO PROCESSING FOR PLAYBACK The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-D effects processing. The de-emphasis function is implemented by a programmable digital filter block with fully programmable coefficients (see page 1, registers 21–26 for left channel, page 1, registers 47–52 for right channel).
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Table 5.
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TLV320AIC34 SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 www.ti.com DELTA-SIGMA AUDIO DAC The stereo audio DAC in each partition incorporates a third-order multibit delta-sigma modulator followed by an analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping techniques. The analog reconstruction filter design consists of a six-tap analog FIR filter followed by a continuous-time RC filter.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Table 6. Analog Output Common-Mode Recommended Settings CM SETTING RECOMMENDED AVDD, DRVDD RECOMMENDED DVDD 1.35 V 2.7 V–3.6 V 1.65 V–1.95 V 1.5 V 3 V–3.6 V 1.65 V–1.95 V 1.65 V 3.3 V–3.6 V 1.8 V–1.95 V 1.8 V 3.6 V 1.95 V AUDIO DAC POWER CONTROL The stereo DAC can be fully powered up or down, and in addition, the analog circuitry in each DAC channel can be powered up or down independently.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Three fully-differential analog inputs can similarly be mixed into each partition's right-ADC PGA as well, consisting of LINE1RP_x, LINE1RM_x, LINE2RP_x, LINE2RM_x, LINE1LP_x, and LINE1LM_x. Note that it is not necessary to mix all three fully differential signals if this is not desired—unnecessary inputs can simply be muted using the input level control registers.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY In addition to the input bypass path described previously, the TLV320AIC34 also includes the ability to route the ADC PGA output signals past the ADC, for mixing with other analog signals and then direct connection to the output drivers of the same partition. These bypass functions are described in more detail in the sections on output mixing and output driver configurations.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 LINE2LP_x SW-L2 LINE2LP_x SW-L1 SW-L0 SW-L3 LINE1LP_x LEFT_LOP_x LEFT_LOM_x SW-L4 LINE1LP_x LINE1LM_x LINE1LM_x LINE2LM_x SW-L5 SW-R2 LINE1RP_x LINE1RM_x LINE1RP_x SW-R1 SW-R0 SW-R3 LINE2RP_x LINE1RM_x LINE2RP_x LINE2RM_x RIGHT_LOP_x RIGHT_LOM_x SW-R4 SW-R5 LINE2RM_x B0174-03 Figure 32.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 DIGITAL MICROPHONE CONNECTIVITY The TLV320AIC34 includes support for connection of digital microphones to the device by routing the digital signal directly into the ADC digital decimation filter, where it is filtered, downsampled, and provided to the host processor over the audio data serial bus.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 LINE2LP_x LINE2LM_x LINE2RP_x LINE2RM_x PGA_LP_x PGA_LM_x PGA_RP_x PGA_RM_x 0 dB to –78 dB 0 dB to –78 dB 0 dB to –78 dB + 0 dB to –78 dB DAC_L1 0 dB to –78 dB DAC_R1 0 dB to –78 dB B0158-03 Figure 34. Detail of the Volume Control and Mixing Function Shown in Figure 33 The DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered by register control based on the requirements of the system.
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TLV320AIC34 SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 • www.ti.com Combinations of the foregoing The output-stage architecture of each partition leading to the high-power output drivers is shown in Figure 35, with the volume control and mixing blocks being effectively identical to those shown in Figure 34. Note that each of these drivers has an output level control block like those included with the line output drivers, allowing gain adjustment up to 9 dB on the output signal.
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TLV320AIC34 SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 www.ti.com The high-power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions. The user should first program the type of output configuration being used in page 0, register 14, to allow the device to select the optimal power-up scheme to avoid output artifacts.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 MICBIAS_x g Stereo s AVDD s MICDET_x To Detection Block MIC3L_x or MIC3R_x Cellular g s m HPLOUT_x Stereo + Cellular g s m s HPROUT_x m = mic s = ear speaker g = ground/vcm HPRCOM_x To Detection Block HPLCOM_x VCM B0243-01 Figure 36.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 An output configuration for the case of the outputs driving fully differential stereo headphones is shown in Figure 38. In this mode, there is a requirement on the jack side that either HPLCOM_x or HPLOUT_x be shorted to ground if the plug is removed. This requirement can be implemented using a spring terminal in a jack.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 1: BIT READ/ WRITE RESET VALUE D7 W 0 D6–D0 W 000 0000 Software Reset Register DESCRIPTION Software Reset Bit 0 : Don’t care 1 : Self-clearing software reset Reserved. Do not write to these bits. Page 0 / Register 2: Codec Sample Rate Select Register BIT READ/ WRITE RESET VALUE D7–D4 R/W 0000 ADC Sample Rate Select 0000: ADC fS = fS(ref)/1 0001: ADC fS = fS(ref)/1.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 4: BIT READ/ WRITE RESET VALUE D7–D2 R/W 0000 01 D1–D0 R/W 00 DESCRIPTION PLL J Value 0000 00: Reserved. Do not write this sequence to these register bits. 0000 01: J = 1 0000 10: J = 2 0000 11: J = 3 … 1111 10: J = 62 1111 11: J = 63 Reserved. Write only zeros to these bits.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 8: Audio Serial Data Interface Control Register A BIT READ/ WRITE RESET VALUE D7 R/W 0 Bit Clock Directional Control 0: BCLK_x (or GPIO2_x if programmed as BCLK_x) is an input (slave mode). 1: BCLK_x (or GPIO2_x if programmed as BCLK_x) is an output (master mode). D6 R/W 0 Word Clock Directional Control 0: WCLK_x (or GPIO1_x if programmed as WCLK_x) is an input (slave mode).
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 10: BIT READ/ WRITE RESET VALUE D7–D0 R/W 0000 0000 Audio Serial Data Interface Control Register C DESCRIPTION Audio Serial Data Word Offset Control This register determines where valid data is placed or expected in each frame, by controlling the offset from the beginning of the frame where valid data begins. The offset is measured from the rising edge of the word clock when in DSP mode.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 12: Audio Codec Digital Filter Control Register BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 Left-ADC High-Pass Filter Control 00: Left-ADC high-pass filter disabled 01: Left-ADC high-pass filter –3-dB frequency = 0.0045 × ADC fS 10: Left-ADC high-pass filter –3-dB frequency = 0.0125 × ADC fS 11: Left-ADC high-pass filter –3-dB frequency = 0.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 14: Headset / Button Press Detection Register B BIT READ/ WRITE RESET VALUE D7 R/W 0 Driver Capacitive Coupling 0: Programs high-power outputs for capless driver configuration 1: Programs high-power outputs for ac-coupled driver configuration D6 (1) R/W 0 Stereo Output Driver Configuration A Note: Do not set bits D6 and D3 both high at the same time.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 17: MIC3L_x and MIC3R_x to Left-ADC Control Register BIT READ/ WRITE RESET VALUE D7–D4 R/W 1111 MIC3L_x Input Level Control for Left-ADC PGA Mix Setting the input level control to one of the following gains automatically connects MIC3L_x to the left-ADC PGA mix. 0000: Input level control gain = 0 dB 0001: Input level control gain = –1.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 19: LINE1LP_x and LINE1LP_x and LINE1LM_xM_x to Left-ADC Control Register BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D3 R/W 1111 D2 R/W 0 Left-ADC Channel Power Control 0: Left-ADC channel is powered down. 1: Left-ADC channel is powered up.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 21: LINE1RP_x and LINE1RM_x to Left-ADC Control Register BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D3 R/W 1111 LINE1R Input Level Control for Left-ADC PGA Mix Setting the input level control to one of the following gains automatically connects LINE1R to the left-ADC PGA mix. 0000: Input level control gain = 0 dB 0001: Input level control gain = –1.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 23: LINE2RP_x and LINE2RM_x to Right-ADC Control Register BIT READ/ WRITE RESET VALUE D7 R/W 0 LINE2R Single-Ended vs Fully Differential Control If LINE2R is selected to both left- and right-ADC channels, both connections must use the same configuration (single-ended or fully differential mode). 0: LINE2R is configured in single-ended mode. 1: LINE2R is configured in fully differential mode.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 25: MICBIAS_x Control Register BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 MICBIAS_x Level Control 00: MICBIAS_x output is powered down. 01: MICBIAS_x output is powered to 2 V. 10: MICBIAS_x output is powered to 2.5 V. 11: MICBIAS_x output is connected to AVDD. D5–D4 R/W 00 Digital Microphone Control 00: If digital MIC is enabled, both left and right digital MICs are available.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 28: BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 D5–D1 R/W 00 000 D0 R/W 0 DESCRIPTION Noise Gate Hysteresis Level Control 00: Hysteresis = 1 dB 01: Hysteresis = 2 dB 10: Hysteresis = 3 dB 11: Hysteresis is disabled.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 31: BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 D5–D1 R/W 00 000 D0 R/W 0 Right-AGC Control Register C DESCRIPTION Noise Gate Hysteresis Level Control 00: Hysteresis = 1 dB 01: Hysteresis = 2 dB 10: Hysteresis = 3 dB 11: Hysteresis is disabled.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 34: Left-AGC Noise Gate Debounce Register BIT READ/ WRITE RESET VALUE D7–D3 R/W 0000 0 Left-AGC Noise Detection Debounce Control These times (1) are not accurate when double-rate audio mode is enabled. 0000 0: Debounce = 0 ms 0000 1: Debounce = 0.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 36: ADC Flag Register BIT READ/ WRITE RESET VALUE D7 R 0 Left-ADC PGA Status 0: Applied gain and programmed gain are not the same. 1: Applied gain = programmed gain D6 R 0 Left-ADC Power Status 0: Left ADC is in a power-down state. 1: Left ADC is in a power-up state. D5 R 0 Left-AGC Signal Detection Status 0: Signal power is greater than noise threshold. 1: Signal power is less than noise threshold.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 38: BIT READ/ WRITE High-Power Output Driver Control Register RESET VALUE DESCRIPTION D7–D6 R 00 Reserved. Write only zeros to these register bits.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 41: DAC Output Switching Control Register BIT READ/ WRITE RESET VALUE D7–D6 R/W 00 Left-DAC Output Switching Control 00: Left-DAC output selects DAC_L1 path. 01: Left-DAC output selects DAC_L3 path to left line output driver. 10: Left-DAC output selects DAC_L2 path to left high-power output drivers. 11: Reserved. Do not write this sequence to these register bits.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 44: BIT READ/ WRITE RESET VALUE D7 R/W 1 D6–D0 R/W 000 0000 70 Right-DAC Digital Volume Control Register DESCRIPTION Right-DAC Digital Mute 0: The right-DAC channel is not muted. 1: The right-DAC channel is muted. Right-DAC Digital Volume Control Setting 000 0000: Gain = 0 dB 000 0001: Gain = –0.5 dB 000 0010: Gain = –1 dB … 111 1101: Gain = –62.5 dB 111 1110: Gain = –63 dB 111 1111: Gain = –63.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Output Stage Volume Controls A basic analog volume control with range from 0 dB to –78 dB and mute is replicated multiple times in the output stage network, connected to each of the analog signals that route to the output stage. In addition, to enable completely independent mixing operations to be performed for each output driver, each analog signal coming into the output stage may have up to seven separate volume controls.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 46: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 PGA_LP_x and PGA_LM_x to HPLOUT_x Volume Control Register DESCRIPTION PGA_LP_x and PGA_LM_x Output Routing Control 0: PGA_LP_x and PGA_LM_x is not routed to HPLOUT_x. 1: PGA_LP_x and PGA_LM_x is routed to HPLOUT_x. PGA_LP_x and PGA_LM_x to HPLOUT_x Analog Volume Control For 7-bit register setting versus analog gain values, see Table 7.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 51: HPLOUT_x Output Level Control Register BIT READ/ WRITE RESET VALUE D7–D4 R/W 0000 D3 R/W 0 HPLOUT_x Mute 0: HPLOUT_x is muted. 1: HPLOUT_x is not muted. D2 R/W 1 HPLOUT_x Power Down Drive Control 0: HPLOUT_x is weakly driven to a common mode when powered down. 1: HPLOUT_x is high-impedance when powered down.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 55: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 DESCRIPTION LINE2RP_x and LINE2RM_x Output Routing Control 0: LINE2RP_x and LINE2RM_x is not routed to HPLCOM_x. 1: LINE2RP_x and LINE2RM_x is routed to HPLCOM_x. LINE2RP_x and LINE2RM_x to HPLCOM_x Analog Volume Control For 7-bit register setting versus analog gain values, see Table 7.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 59: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 DESCRIPTION LINE2LP_x and LINE2LM_x Output Routing Control 0: LINE2LP_x and LINE2LM_x is not routed to HPROUT_x. 1: LINE2LP_x and LINE2LM_x is routed to HPROUT_x. LINE2LP_x and LINE2LM_x to HPROUT_x Analog Volume Control For 7-bit register setting versus analog gain values, see Table 7.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 65: HPROUT_x Output Level Control Register BIT READ/ WRITE RESET VALUE D7–D4 R/W 0000 D3 R/W 0 HPROUT_x Mute 0: HPROUT_x is muted. 1: HPROUT_x is not muted. D2 R/W 1 HPROUT_x Power-Down Drive Control 0: HPROUT_x is weakly driven to a common mode when powered down. 1: HPROUT_x is high-impedance when powered down.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 69: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 DESCRIPTION LINE2RP_x and LINE2RM_x Output Routing Control 0: LINE2RP_x and LINE2RM_x is not routed to HPRCOM_x. 1: LINE2RP_x and LINE2RM_x is routed to HPRCOM_x. LINE2RP_x and LINE2RM_x to HPRCOM_x Analog Volume Control For 7-bit register setting versus analog gain values, see Table 7.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 73: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 Page 0 / Register 74: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 LINE2LP_x and LINE2LM_x to MONO_LOP_x and MONO_LOM_x Volume Control Register DESCRIPTION LINE2LP_x and LINE2LM_x Output Routing Control 0: LINE2LP_x and LINE2LM_x is not routed to MONO_LOP_x and MONO_LOM_x.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 78: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 DAC_R1 to MONO_LOP_x and MONO_LOM_x Volume Control Register DESCRIPTION DAC_R1 Output Routing Control 0: DAC_R1 is not routed to MONO_LOP_x and MONO_LOM_x. 1: DAC_R1 is routed to MONO_LOP_x and MONO_LOM_x. DAC_R1 to MONO_LOP_x and MONO_LOM_x Analog Volume Control For 7-bit register setting versus analog gain values, see Table 7.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 82: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 Page 0 / Register 83: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 Page 0 / Register 84: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 DESCRIPTION DAC_L1 Output Routing Control 0: DAC_L1 is not routed to LEFT_LOP_x and LEFT_LOM_x. 1: DAC_L1 is routed to LEFT_LOP_x and LEFT_LOM_x.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 86: LEFT_LOP_x and LEFT_LOM_x Output Level Control Register BIT READ/ WRITE RESET VALUE D7–D4 R/W 0000 D3 R/W 0 LEFT_LOP_x and LEFT_LOM_x Mute 0: LEFT_LOP_x and LEFT_LOM_x is muted. 1: LEFT_LOP_x and LEFT_LOM_x is not muted. D2 R 0 Reserved. Do not write to this register bit.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 90: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 Page 0 / Register 91: BIT READ/ WRITE RESET VALUE D7 R/W 0 D6–D0 R/W 000 0000 LINE2RP_x and LINE2RM_x to RIGHT_LOP_x and RIGHT_LOM_x Volume Control Register DESCRIPTION LINE2RP_x and LINE2RM_x Output Routing Control 0: LINE2RP_x and LINE2RM_x is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 94: Module Power-Status Register BIT READ/ WRITE RESET VALUE D7 R 0 Left-DAC Power Status 0:Left DAC is not fully powered up. 1: Left DAC is fully powered up. D6 R 0 Right-DAC Power Status 0: Right DAC is not fully powered up. 1: Right DAC is fully powered up. D5 R 0 MONO_LOP_x and MONO_LOM_x Power Status 0: MONO_LOP_x and MONO_LOM_x output driver is powered down.
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TLV320AIC34 www.ti.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 98: GPIO1_x Control Register BIT READ/ WRITE RESET VALUE D7–D4 R/W 0000 D3 R/W 0 GPIO1_x Clock Mux Output Control 0: GPIO1_x clock mux output = PLL output 1: GPIO1_x clock mux output = clock divider mux output D2 R/W 0 GPIO1_x Interrupt Duration Control 0: GPIO1_x interrupt occurs as a single active-high pulse of typical 2-ms duration.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 99: GPIO2_x Control Register BIT READ/ WRITE RESET VALUE D7–D4 R/W 0000 D3 R/W 0 GPIO2_x General-Purpose Output Value 0: GPIO2_x_x outputs a logic-low level. 1: GPIO2_x outputs a logic-high level. D2 R 0 GPIO2_x General-Purpose Input Value 0: A logic-low level is input to GPIO2_x. 1: A logic-high level is input to GPIO2_x.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 101: Codec A, I2C Address Select BIT READ/ WRITE RESET VALUE D7 R 0 Reserved D6 R 0 Codec A I2C Address ADDR_A Terminal Status 0: When ADDR_A is in a reset condition, then the I2C address is 001 1000. 1: When ADDR_A is in a reset condition, then the I2C address is 001 1010.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 104: Left-AGC New Programmable Decay Time Register (1) BIT READ/ WRITE RESET VALUE D7 R/W 0 Decay Time Register Selection 0: Decay time for the left AGC is generated from register 26. 1: Decay time for the left AGC is generated from this register.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 106: Right-AGC New Programmable Decay Time Register (1) BIT READ/ WRITE RESET VALUE D7 R/W 0 Decay Time Register Selection 0: Decay time for the right AGC is generated from register 29. 1: Decay time for the right AGC is generated from this register.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Page 0 / Register 108: (1) Passive Analog Signal Bypass Selection During Power Down Register (1) BIT READ/ WRITE RESET VALUE D7 R/W 0 LINE2RM_x Path Selection 0: Normal signal path 1: Signal is routed by a switch to RIGHT_LOM_x. D6 R/W 0 LINE2RP_x Path Selection 0: Normal signal path 1: Signal is routed by a switch to RIGHT_LOP_x.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 The remaining page-1 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320AIC34. Reserved registers should not be written to. The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter.
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TLV320AIC34 www.ti.com SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007 Table 8.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 21-Jan-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV320AIC34IZASR Package Package Pins Type Drawing NFBGA ZAS 87 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.3 B0 (mm) K0 (mm) P1 (mm) 6.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC34IZASR NFBGA ZAS 87 2500 336.6 336.6 31.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.