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Audio Serial Bus Interface

LINE 2LP

PGA

+59.5dB

0.5dB

Steps

Left

Channel

ADC

HPCOM

HPLOUT

Left

Channel

DAC

AGC

Bias/

Reference

HPROUT

RIGHT _LOP

LEFT _LOP

MIC 3R/LINE 2RM

LINE 2RP /LINE 2LM

LINE 1RP

MIC 3L/LINE 1RM

MICDET /LINE1LM

LINE 1LP

Feedthrough Line Paths to Class AB Line Amplifiers,

Passive Switches to Line Outputs,

and Class-D Speaker Amplifiers

SPOP

Right

Channel

ADC

Right

Channel

DAC

PGA

+59.5dB

0.5dB

Steps

AGC

SPOM

Audio CLK

Gen

GPIO 1

MCLK

SWINP

SWINM

I2C Serial

Control Bus

SWOUTP

SWOUTM

Analog

Signal

Input

MIX/MUX,

Switching,

and/or

Attenuation

Digital

Audio

Filtering,

Volume

Control,

Effects,

and

Processing

Output

Amplifiers

MIX/MUX,

Switching,

and

Gain/Atten

AVDD_ADC

AVSS_ADC

DIN

DOUT

DVDD

IOVDD

DVSS

BCLK

WCLK

DRVDD

DRVSS

AVDD_DAC

AVSS_DAC

MICBIAS

RESET

SCL

SDA

SPVSS

SPVDD

QFN

Only

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

TLV320AIC3107

SLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014

TLV320AIC3107 Low-Power Stereo Codec With Integrated Mono Class-D Speaker

Amplifier

1 Features • Programmable PLL for Flexible Clock Generation

• I

C™ Control Bus

• Stereo CODEC With Integrated Mono Class-D

Amplifier

• Audio Serial Data Bus Supports I

S, Left/Right-

Justified, DSP, and TDM Modes

• High Performance Audio DAC

• Extensive Modular Power Control

– 97-dBA Signal-to-Noise Ratio (Single Ended)

• Power Supplies:

– 16/20/24/32-Bit Data

– Speaker Amp: 2.7 V – 5.5 V

– Supports Sample Rates From 8 kHz to 96 kHz

– Analog: 2.7 V – 3.6 V.

– 3D/Bass/Treble/EQ/De-Emphasis Effects

– Digital Core: 1.525 V – 1.95 V

– Flexible Power Saving Modes and

Performance are Available – Digital I/O: 1.1 V – 3.6 V

• High Performance Audio ADC • Packages: 5-mm × 5-mm 40-QFN, 0.4-mm Pitch

3.563-mm × 3.376-mm 42-DSBGA, 0.5 mm Pitch

– 92-dBA Signal-to-Noise Ratio

(Product Preview)

– Supports Rates From 8 kHz to 96 kHz

– Digital Signal Processing and Noise Filtering

2 Applications

Available During Record

• Cellular Handsets

• Seven Audio Input Pins

• Digital Cameras

– Programmable as 6 Single-Ended or 3 Fully

• Portable Media Players

Differential Inputs

• General Portable Audio Equipment

– Capability for Floating Input Configurations

• Multiple Audio Output Drivers

3 Description

– Mono Fully Differential or Stereo Single-Ended

The TLV320AIC3107 is a low power stereo audio

Headphone Drivers

codec with stereo headphone amplifier, and mono

– Single-Ended Stereo Line Outputs

class-D speaker driver, as well as multiple inputs and

outputs programmable in single-ended or

• Mono 1 W Class-D BTL 8Ω Speaker Driver

fully differential configurations.

• Low Power Consumption: 15-mW Stereo 48-kHz

Playback With 3.3-V Analog Supply

Device Information

(1)

• Ultra-Low Power Mode with Passive Analog

PART NUMBER PACKAGE BODY SIZE (MAX)

Bypass

WQFN (40) 5.15 mm × 5.15 mm

TLV320AIC3107

• Programmable Input/Output Analog Gains

DSBGA (42) 3.563 mm × 3.376 mm

• Automatic Gain Control (AGC) for Record

(1) For all available packages, see the orderable addendum at

• Programmable Microphone Bias Level

the end of the datasheet.

4 Simplified Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

DATA.

Summary of content (100 pages)

PAGE 1
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 TLV320AIC3107 Low-Power Stereo Codec With Integrated Mono Class-D Speaker Amplifier 1 Features • 1 • • • • • • • • • • • • • Stereo CODEC With Integrated Mono Class-D Amplifier High Performance Audio DAC – 97-dBA Signal-to-Noise Ratio (Single Ended) – 16/20/24/32-Bit Data – Supports Sample Rates From 8 kHz to 96 kHz – 3D/Bass/Treble/EQ/De-Emphasis
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Block Diagram ..................................... Revision History..................................................... Description (Continued) .....................
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 6 Description (Continued) Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 15 mW from a 3.3-V analog supply, making it ideal for portable battery-powered audio and telephony applications.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.
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TLV320AIC3107 www.ti.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) TJ Max (2) MIN MAX UNIT AVDD_DAC to AVSS_DAC, DRVDD to DRVSS, AVSS_ADC –0.3 3.9 V SPVDD to SPVSS –0.3 6.0 V AVDD to DRVSS –0.3 3.9 V IOVDD to DVSS –0.3 3.9 V DVDD to DVSS –0.3 2.5 V AVDD_DAC to DRVDD –0.1 0.1 V Digital input voltage to DVSS –0.3 IOVDD + 0.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 8.4 Thermal Information TLV320AIC3107 THERMAL METRIC (1) RSB YZF 40 PINS 42 PINS 30.7 49.5 RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 16 0.1 RθJB Junction-to-board thermal resistance 4.6 7.1 ψJT Junction-to-top characterization parameter 0.2 0.8 ψJB Junction-to-board characterization parameter 4.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com 8.6 Electrical Characteristics At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5 V, IOVDD = 3.3 V, DVDD = 1.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Electrical Characteristics (continued) At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5 V, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 2.3 2.5 MAX UNIT MICROPHONE BIAS Programmable setting = 2.0 Bias voltage Programmable setting = 2.5 Programmable setting = DRVDD Current sourcing Programmable setting = 2.5V 2 2.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5 V, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SPEAKER AMPLIFIER OUTPUT, LOAD = 8 Ω Full-scale output voltage 1 kHz, 0dB full-scale input signal, Output volume control for left line output = 0 dB, for classD = 0 dB Output common mode setting = 1.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Electrical Characteristics (continued) At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5 V, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER CONSUMPTION, DRVDD, AVDD_DAC = 3.3 V, SPVDD = 5V, DVDD = 1.8 V, IOVDD = 3.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Audio Data Serial Interface Timing Requirements(1)(2) (continued) IOVDD = 1.1 V MIN IOVDD = 3.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 WCLK td(WS) td(WS) BCLK td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-01 Figure 2. DSP Timing in Master Mode WCLK tS(WS) th(WS) tH(BCLK) BCLK td(DO-WS) tL(BCLK) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-02 2 Figure 3.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com WCLK tS(WS) tS(WS) th(WS) th(WS) tL(BCLK) BCLK tH(BCLK) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-02 Figure 4.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 8.8 Typical Characteristics 45 0 2.7 VDD_CM 1.35_LDAC 40 3.6 VDD_CM 1.8_LDAC -20 SNR - Signal-To-Noise - dB THD - Total Harmonic Distortion - dB -10 3.3 VDD_CM1.65_LDAC 2.7 VDD_CM 1.35_RDAC -30 -40 3.3 VDD_CM 1.65_RDAC -50 -60 -70 35 30 25 20 15 10 -80 LINEIR Routed to RADC in Differential Mode, 48 KSPS, Normal Supply and Temperature, Input Signal at -65 dB 5 3.6 VDD_CM 1.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) 0 0 Load = 10 kW, FS = 48 kHz, fs = 64 kHz, 2048 Samples, AVDD = DRVDD = 3.3 V, -40 -60 Load = 10 kW, FS = 48 kHz, fs = 64 kHz, 2048 Samples, AVDD = DRVDD = 3.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 9 Parameter Measurement Information All parameters are measured according to the conditions described in the Specifications section. 10 Detailed Description 10.1 Overview The TLV320AIC3107 is a highly flexible, low power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com 10.3 Feature Description 10.3.1 Hardware Reset The TLV320AIC3107 requires a hardware reset after power-up for proper operation. After all power supplies are at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not performed, the TLV320AIC3107 may not respond properly to register reads/writes. 10.3.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Feature Description (continued) 1/fs WCLK BCLK Left Channel SDIN/ SDOUT 0 n−1 n−2 n−3 MSB Right Channel 2 1 0 n−1 n−2 n−3 2 1 0 LSB Figure 14. Right Justified Serial Bus Mode Operation 10.3.2.2 Left Justified Mode In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) 10.3.2.4 DSP Mode In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock. 1/fs WCLK BCLK Right Channel Left Channel SDIN/SDOUT n–1 n–2 n–3 n–4 LSB MSB 2 1 0 n–1 n–2 n–3 LSB MSB 2 1 0 n–1 LSB T0152-01 Figure 17.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Feature Description (continued) DSP Mode word clock bit clock data in/out N-1 N-2 1 Left Channel Data offset 0 N-1 N-2 1 0 Right Channel Data Left Justified Mode word clock bit clock data in/out N-1 offset N-2 1 Left Channel Data 0 N-1 offset N-2 1 0 Right Channel Data Figure 18. DSP Mode and Left Justified Modes, Showing the Effect of a Programmed Data Word Offset 10.3.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) MCLK BCLK CLKDIV_CLKIN PLL_CLKIN CLKDIV_IN Q=2,3,…..,16,17 PLL_IN K = J.D J = 1,2,3,…..,62,63 D= 0000,0001,….,9998,9999 R= 1,2,3,4,….,15,16 P= 1,2,….,7,8 K*R/P 2/Q PLL_OUT CLKDIV_OUT 1/8 PLLDIV_OUT CODEC_CLKIN CLKMUX _OUT CODEC_CLK=256*Fsref CLKOUT_IN M =1,2,4,8 N = 2,3,……,16,17 2/(N*M) CLKOUT CODEC DAC_FS GPIO1 ADC_FS WCLK = Fsref/ Ndac GPIO1 = Fsref/ Nadc Ndac=1,1.5,2,…..,5.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Feature Description (continued) where • • • • • • P = 1, 2, 3,…, 8 R = 1, 2, …, 16 K = J.D J = 1, 2, 3, …, 63 D = 0000, 0001, 0002, 0003, …, 9998, 9999 PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5-D4 (2) P, R, J, and D are register programmable.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) Table 1. Audio Clock Generation (continued) Fsref = 44.1 kHz 3.072 1 1 32 0 48000.00 0.0000 4.096 1 1 24 0 48000.00 0.0000 6.144 1 1 16 0 48000.00 0.0000 8.192 1 1 12 0 48000.00 0.0000 12.0 1 1 8 1920 48000.00 0.0000 13.0 1 1 7 5618 47999.71 –0.0006 16.0 1 1 6 1440 48000.00 0.0000 19.2 1 1 5 1200 48000.00 0.0000 19.68 1 1 4 9951 47999.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part after the ADC power down register is written to ensure the soft-stepping to mute has completed.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Table 2. AGC Decay Time Restriction NADC RATIO MAXIMUM DECAY TIME (seconds) 1.0 4.0 1.5 5.6 2.0 8.0 2.5 9.6 3.0 11.2 3.5 11.2 4.0 16.0 4.5 16.0 5.0 19.2 5.5 22.4 6.0 22.4 10.3.3.2.2.4 Noise Gate Threshold Noise Gate Threshold determines the level below which if the input speech average value falls, AGC considers it as a silence and hence brings down the gain to 0 dB in steps of 0.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Note that the time constants here are correct when the ADC is not in double-rate audio mode. The time constants are achieved using the Fsref value programmed in the control registers. However, if the Fsref is set in the registers to, for example, 48 kHz, but the actual audio clock or PLL programming actually results in a different Fsref in practice, then the time constants would not be correct.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com The N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed. The structure of the filtering when configured for independent channel processing is shown below in Figure 21, with LB1 corresponding to the first left-channel biquad filter using coefficients N0, N1, N2, D1, and D2. LB2 similarly corresponds to the second left-channel biquad filter using coefficients N3, N4, N5, D4, and D5.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 + + + L + + – LB2 To Left Channel Atten LB1 R + – + To Right Channel RB2 B0155-01 Figure 22. Architecture of the Digital Audio Processing When 3-D Effects are Enabled It is recommended that the digital effects filters should be disabled while the filter coefficients are being modified.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be important if the host wishes to mute the DAC before making a significant change, such as changing sample rates.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 10.3.3.3.7 Audio DAC Power Control The stereo DAC can be fully powered up or down, and in addition, the analog circuitry in each DAC channel can be powered up or down independently. This provides power savings when only a mono playback stream is needed. 10.3.4 Audio Analog Inputs LINE1LP 0dB to -18dB in 0.5dB Steps LINE2LP 0dB, -6dB, or -12dB LINE1RP 0dB to -18dB in 0.5dB Steps MIC3L/LINE 1RM MIC3L 0dB to -18dB in 0.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com LINE1RP 0dB to -18dB in 0.5dB Steps LINE2RP/LINE2LM 0dB, -6dB, or -12dB LINE1LP 0dB to -18dB in 0.5dB Steps MIC3L/LINE 1RM MIC3L 0dB to -18dB in 0.5dB Steps MIC3R/LINE2RM MIC3R Right ADC 0dB to -18dB in 0.5dB Steps LINE1RM PDWN 0dB to -18dB in 0.5dB Steps VCM For LINE1R Single-Ended 0dB to -18dB in 0.5dB Steps LINE2RM 0dB, -6dB, or -12dB VCM For LINE2R Single-Ended 0dB to -18dB in 0.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 The LINE2L/R signals refer to the signals that travel through the analog input bypass path to the output stage. The PGA_L/R signals refer to the outputs of the ADC PGA stages that are similarly passed around the ADC to the output stage.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com The DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered by register control based on the requirements of the system. If mixing of the DAC audio with other signals is not required, and the DAC output is only needed at the stereo line outputs, then it is recommended to use the routing through path DAC_L3/R3 to the stereo line outputs.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 LINE2L LINE2R PGA_L PGA_R DAC_L1 DAC_R1 VOLUME CONTROLS, MIXING Volume 0dB to +9dB, mute HPLOUT DAC_L2 LINE2L LINE2R PGA_L PGA_R DAC_L1 DAC_R1 VOLUME CONTROLS, MIXING VCM Volume 0dB to +9dB, mute HPCOM DAC_R2 LINE2L LINE2R PGA_L PGA_R DAC_L1 DAC_R1 VOLUME CONTROLS, MIXING Volume 0dB to +9dB, mute HPROUT Figure 27.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com 10.3.7 Input Impedance and VCM Control The TLV320AIC3107 includes several programmable settings to control analog input pins, particularly when they are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a 3state condition, such that the input impedance seen looking into the device is extremely high.
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TLV320AIC3107 www.ti.com 2. 3. 4. 5. 6. SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 0x0D 0x0D 0x08 0x5C 0x08 0x5D 0x08 0x5C 0x00 0x00 Also available is an analog bypass switch to allow a signal (0.35V to 2.8V) to be input at SWINP and SWINM and output at SWOUTP and SWOUTM. In a typical application, SWOUTP and SWOUTM are connected to SPOP and SPOM respectively so as to provide an alternate method of driving the 8-Ω speaker.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com 10.3.12 Jack and Headset Detection The TLV320AIC3107 includes extensive capability to monitor a headphone, microphone, or headset jack, determine if a plug has been inserted into the jack, and then determine what type of headset/headphone is wired to the plug.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 An output configuration for the case of the outputs driving fully differential stereo headphones is shown in Figure 31. In this mode there is a requirement on the jack side that either HPCOM or HPLOUT get shorted to ground if the plug is removed, which can be implemented using a spring terminal in a jack.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Device Functional Modes (continued) 10.4.1.3 Passive Analog Bypass During Powerdown Programming the TLV320AIC3107 to Passive Analog bypass occurs by configuring the output stage switches for pass through. This is done by opening switches SW-L0, SW-L3, SW-R0, and closing either SW-L1 or SW-L2 and SW-R1 or SW-R2. See Figure 32 Passive Analog Bypass Mode Configuration. Programming this mode is done by writing to Page 0, Register 108.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Device Functional Modes (continued) 10.4.2 Digital Audio Processing For Record Path BCLK WCLK DIN DOUT In applications where record only is selected, and DAC is powered down, the playback path signal processing blocks can be used in the ADC record path. These filtering blocks can support high pass, low pass, band pass or notch filtering.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Programming (continued) SDA tHD-STA ³ 0.9 ms SCL tSU-STA ³ 0.9 ms tSU-STO ³ 0.9 ms tHD-STA ³ 0.9 ms S Sr P S Figure 34. I2C Fast-Mode Timing Requirements I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Programming (continued) A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address it, it will receive a not−acknowledge because no device is present at that address to pull the line LOW. When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Programming (continued) For example, at device reset, the active page defaults to page 0, and thus all register read/write operations for addresses 1 to 127 access registers in page 0. If registers on page 1 must be accessed, the user must write the 8-bit sequence 0x01 to register 0, the page control register, to change the active page from page 0 to page 1.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 8. Page 0 / Register 2: BIT D7-D4 READ/ WRITE R/W RESET VALUE 0000 D3-D0 R/W 0000 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D3 R/W 0010 D2–D0 R/W 000 Codec Sample Rate Select Register DESCRIPTION ADC Sample Rate Select 0000: ADC Fs = Fsref/1 0001: ADC Fs = Fsref/1.5 0010: ADC Fs = Fsref/2 0011: ADC Fs = Fsref/2.5 0100: ADC Fs = Fsref/3 0101: ADC Fs = Fsref/3.5 0110: ADC Fs = Fsref/4 0111: ADC Fs = Fsref/4.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 10.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 14. Page 0 / Register 8: BIT D7 READ/ WRITE R/W D6 R/W D5 R/W D4 R/W D3 D2 R/W R/W D1-D0 R/W Table 15.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 16. Page 0 / Register 10: BIT D7–D0 READ/ WRITE R/W RESET VALUE 00000000 D7 D6 D5 D4 D3–D0 48 READ/ WRITE R R R R R/W RESET VALUE 0 0 0 0 0001 Audio Serial Data Interface Control Register C DESCRIPTION Audio Serial Data Word Offset Control This register determines where valid data is placed or expected in each frame, by controlling the offset from beginning of the frame where valid data begins.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 18. Page 0 / Register 12: BIT D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D4 R/W 00 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 DESCRIPTION Left ADC Highpass Filter Control 00: Left ADC highpass filter disabled 01: Left ADC highpass filter –3 dB frequency = 0.0045 × ADC Fs 10: Left ADC highpass filter –3 dB frequency = 0.0125 × ADC Fs 11: Left ADC highpass filter –3 dB frequency = 0.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 20.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 23. Page 0 / Register 17: BIT D7-D4 READ/ WRITE R/W RESET VALUE 1111 D3-D0 R/W 1111 BIT D7–D4 READ/ WRITE R/W RESET VALUE 1111 D3–D0 R/W 1111 MIC3L/R to Left ADC Control Register DESCRIPTION MIC3L Input Level Control for Left ADC PGA Mix Setting the input level control to a gain below automatically connects MIC3L to the left ADC PGA mix 0000: Input level control gain = 0.0 dB 0001: Input level control gain = –1.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 25.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 27. Page 0 / Register 21: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D3 R/W 1111 D2–D0 R 000 DESCRIPTION LINE1R Single-Ended vs Fully Differential Control If LINE1R is selected to both left and right ADC channels, both connections must use the same configuration (single-ended or fully differential mode).
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 29. Page 0 / Register 23: BIT D7 READ/ WRITE R/W D6–D3 R/W D2 R/W D1–D0 R LINE2R to Right ADC Control Register RESET DESCRIPTION VALUE 0 LINE2R Single-Ended vs Fully Differential Control If LINE2R is selected to both left and right ADC channels, both connections must use the same configuration (single-ended or fully differential mode).
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 32. Page 0 / Register 26: BIT (1) D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 R/W 000 D3–D2 R/W 00 D1–D0 R/W 00 Left AGC Control Register A DESCRIPTION Left AGC Enable 0: Left AGC is disabled 1: Left AGC is enabled Left AGC Target Level 000: Left AGC target level = –5.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 35. Page 0 / Register 29: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D4 R/W 000 D3–D2 R/W 00 D1–D0 R/W 00 BIT D7–D1 READ/ WRITE R/W RESET VALUE 1111111 D0 R/W 0 Right AGC Enable 0: Right AGC is disabled 1: Right AGC is enabled Right AGC Target Level 000: Right AGC target level = –5.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 38. Page 0 / Register 32: BIT D7–D0 READ/ WRITE R RESET VALUE 00000000 DESCRIPTION Left Channel Gain Applied by AGC Algorithm 11101000: Gain = –12.0 dB 11101001: Gain = –11.5 dB 11101010: Gain = –11.0 dB … 00000000: Gain = 0.0 dB 00000001: Gain = +0.5 dB … 01110110: Gain = +59.0 dB 01110111: Gain = +59.5 dB Table 39.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 41. Page 0 / Register 35: BIT (1) D7–D3 READ/ WRITE R/W RESET VALUE 00000 D2–D0 R/W 000 www.ti.com Right AGC Noise Gate Debounce Register DESCRIPTION Right AGC Noise Detection Debounce Control These times (1) will not be accurate when double rate audio mode is enabled. 00000: Debounce = 0-msec 00001: Debounce = 0.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 43.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 47.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 50. Page 0 / Register 44: BIT D7 READ/ WRITE R/W RESET VALUE 1 D6–D0 R/W 0000000 Right DAC Digital Volume Control Register DESCRIPTION Right DAC Digital Mute 0: The right DAC channel is not muted 1: The right DAC channel is muted Right DAC Digital Volume Control Setting 0000000: Gain = 0.0 dB 0000001: Gain = –0.5 dB 0000010: Gain = –1.0 dB … 1111101: Gain = –62.5 dB 1111110: Gain = –63.0 dB 1111111: Gain = –63.5 dB 10.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Table 51. Output Stage Volume Control Settings and Gains (continued) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) 27 -13.5 57 -28.6 87 28 -14.0 58 -29.1 88 29 -14.5 59 -29.6 89 -44.8 Table 52.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 57. Page 0 / Register 50: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D0 R/W 0000000 BIT D7-D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 R/W 1 D1 R 1 D0 R/W 0 DESCRIPTION DAC_R1 Output Routing Control 0: DAC_R1 is not routed to HPLOUT 1: DAC_R1 is routed to HPLOUT DAC_R1 to HPLOUT Analog Volume Control For 7-bit register setting versus analog gain values, see Table 51 Table 58.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 62.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 67. Page 0 / Register 60: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D0 R/W 0000000 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D0 R/W 0000000 DESCRIPTION PGA_L Output Routing Control 0: PGA_L is not routed to HPROUT 1: PGA_L is routed to HPROUT PGA_L to HPROUT Analog Volume Control For 7-bit register setting versus analog gain values, see Table 51 Table 68.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 72. Page 0 / Register 65: BIT D7-D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 R/W 1 D1 R 1 D0 R/W 0 BIT READ/ WRITE R RESET VALUE 00000000 www.ti.com HPROUT Output Level Control Register DESCRIPTION HPROUT Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ...
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 79. Page 0 / Register 72: BIT D7–D 0 READ/ WRITE R RESET VALUE 00000000 Reserved. Do not write to this register. Table 80. Page 0 / Register 73: BIT D7-D6 READ/ WRITE R/W RESET VALUE 00 D5-D4 R/W 00 D3 W 0 D2 W 0 D1 W 0 D0 R/W 0 Class-D and Bypass Switch Control Register DESCRIPTION Left Class-D amplifier gain. 00: Left Class-D amplifier gain = 0.0 dB 01: Left Class-D amplifier gain = 6.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Table 83.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 88. Page 0 / Register 81: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D0 R/W 0000000 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D0 R/W 0000000 DESCRIPTION PGA_L Output Routing Control 0: PGA_L is not routed to LEFT_LOP 1: PGA_L is routed to LEFT_LOP PGA_L to LEFT_LOP Analog Volume Control For 7-bit register setting versus analog gain values, see Table 51 Table 89.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 93. Page 0 / Register 86: BIT D7-D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 D1 R R 0 1 D0 R 0 D7 READ/ WRITE R/W RESET VALUE 0 D6-D0 R/W 0000000 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D0 R/W 0000000 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D0 R/W 0000000 LEFT_LOP Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ...
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 98. Page 0 / Register 91: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D0 R/W 0000000 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D0 R/W 0000000 DESCRIPTION PGA_R Output Routing Control 0: PGA_R is not routed to RIGHT_LOP 1: PGA_R is routed to RIGHT_LOP PGA_R to RIGHT_LOP Analog Volume Control For 7-bit register setting versus analog gain values, see Table 51 Table 99.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Table 101. Page 0 / Register 94: BIT D7 READ/ WRITE R RESET VALUE 0 D6 R 0 D5 D4 R R 0 0 D3 R 0 D2 R 0 D1 R 0 D0 R 0 DESCRIPTION Left DAC Power Status 0: Left DAC not fully powered up 1: Left DAC fully powered up Right DAC Power Status 0: Right DAC not fully powered up 1: Right DAC fully powered up Reserved. Do not write to this register bit.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 103.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 105. Page 0 / Register 98: BIT D7-D4 READ/ WRITE R/W RESET VALUE 0000 D3 R/W 0 D2 R/W 0 D1 R 0 D0 R/W 0 74 www.ti.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 106. Page 0 / Register 99: BIT D7–D0 READ/ WRITE R RESET VALUE 00000000 READ/ WRITE R RESET VALUE 00000000 Reserved. Do not write to this register. Table 107. Page 0 / Register 100: BIT D7–D0 D7–D1 D0 READ/ WRITE R R/W RESET VALUE 0 0 Reserved. Do not write to this register. CODEC CLKIN Source Selection Register DESCRIPTION Reserved. Do not write to these register bits.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 111. Page 0 / Register 104: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D5 R/W 00 D4-D2 R/W 000 D1-D0 R/W 00 (1) Left AGC Programmable Decay Time Register (1) DESCRIPTION Decay Time Register Selection 0: Decay time for the Left AGC is generated from Register 26. 1: Decay time for the Left AGC is generated from this Register.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 113. Page 0 / Register 106: BIT D7 READ/ WRITE R/W RESET VALUE 0 D6-D5 R/W 00 D4-D2 R/W 000 D1-D0 R/W 00 (1) Right AGC New Programmable Decay Time Register (1) DESCRIPTION Decay Time Register Selection 0: Decay time for the Right AGC is generated from Register 29. 1: Decay time for the Right AGC is generated from this Register.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 115. Page 0 / Register 108: BIT (1) D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 0 D5 D4 R/W R/W 0 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 www.ti.com Passive Analog Signal Bypass Selection During Powerdown Register (1) DESCRIPTION Reserved. Write only zero to this register bit. LINE2RP Path Selection 0: Normal Signal Path 1: Signal is routed by a switch to RIGHT_LOP Reserved. Write only zero to this register bit.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 119. Page 1 / Register 1: BIT D7-D0 (1) READ/ WRITE R/W RESET VALUE 01101011 Left Channel Audio Effects Filter N0 Coefficient MSB Register (1) DESCRIPTION Left Channel Audio Effects Filter N0 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from –32768 to +32767.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 127. Page 1 / Register 9: BIT D7-D0 READ/ WRITE R/W RESET VALUE 10010110 READ/ WRITE D7-D0 R/W Left Channel Audio Effects Filter N4 Coefficient MSB Register DESCRIPTION Left Channel Audio Effects Filter N4 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from –32768 to +32767.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 134. Page 1 / Register 17: BIT D7-D0 READ/ WRITE R/W RESET VALUE 01111101 DESCRIPTION Left Channel Audio Effects Filter D4 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from –32768 to +32767. Table 135.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 142. Page 1 / Register 25: BIT D7-D0 READ/ WRITE R/W RESET VALUE 01010011 D7-D0 READ/ WRITE R/W RESET VALUE 01111110 Left Channel De-emphasis Filter D1 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from –32768 to +32767.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 150. Page 1 / Register 33: BIT D7-D0 READ/ WRITE R/W RESET VALUE 01101011 DESCRIPTION Right Channel Audio Effects Filter N3 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from –32768 to +32767. Table 151.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 158. Page 1 / Register 41: BIT D7-D0 READ/ WRITE R/W RESET VALUE 10000100 D7-D0 READ/ WRITE R/W RESET VALUE 11101110 Right Channel Audio Effects Filter D2 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from –32768 to +32767.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 166. Page 1 / Register 49: BIT D7-D0 READ/ WRITE R/W RESET VALUE 11110011 DESCRIPTION Right Channel De-emphasis Filter N1 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from –32768 to +32767. Table 167.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 174. Page 1 / Register 66: BIT D7-D0 READ/ WRITE R/W RESET VALUE 01010101 D7-D0 READ/ WRITE R/W RESET VALUE 11110011 Left Channel ADC High Pass Filter N0 Coefficient LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from -32768 to +32767.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Table 182. Page 1 / Register 74: BIT D7-D0 READ/ WRITE R/W RESET VALUE 00101101 DESCRIPTION Right Channel ADC High Pass Filter N1 Coefficient LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from -32768 to +32767. Table 183.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com 11 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 11.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 Typical Application (continued) 11.2.1 Design Requirements For this design example, use the parameters shown in Table 186. Table 186. Design Parameters PARAMETER VALUE Supply Voltage (AVDD, DRVDD) 3.3 V Supply Voltage (DVDD, IOVDD) 1.8 V Analog High-Power Output Driver Load 16 Ω Analog Fully Differential Line Output Driver Load 10 kΩ Class D Audio Amplifier Load 18 Ω 11.2.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com 12 Power Supply Recommendations The TLV320AIC3107 has been designed to be extremely tolerant of power supply sequencing. However, in some rare instances, unexpected conditions can be attributed to power supply sequencing. The following sequence will provide the most robust operation. IOVDD should be powered up first. The analog supplies, which include AVDD and DRVDD, should be powered up second.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 13.2 Layout Example Figure 41.
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TLV320AIC3107 SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 www.ti.com Layout Example (continued) Figure 42.
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TLV320AIC3107 www.ti.com SLOS545D – NOVEMBER 2008 – REVISED DECEMBER 2014 14 Device and Documentation Support 14.1 Trademarks I2C is a trademark of Philips Electronics. All other trademarks are the property of their respective owners. 14.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 14.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Oct-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC3107IRSBR WQFN RSB 40 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3107IRSBT WQFN RSB 40 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3107IRSBR WQFN RSB 40 3000 367.0 367.0 35.0 TLV320AIC3107IRSBT WQFN RSB 40 250 210.0 185.0 35.
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