Datasheet

DA(6) DA(0) RA(7) RA(0)
Start
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
SDA
SCL
DA(6) DA(0)
7-bit Device Address
(M)
Read
(M)
Slave
Ack
(S)
D(7) D(0)
8-bit Register Data
(S)
Stop
(M)
Master
No Ack
(M)
Repeat
Start
(M)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
DA(6) DA(0) RA(7) RA(0) D(7) D(0)
Start
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
8-bit Register Data
(M)
Stop
(M)
Slave
Ack
(S)
SDA
SCL
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
TLV320AIC3107
www.ti.com SLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014
Programming (continued)
A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it, it will receive a not−acknowledge because no device
is present at that address to pull the line LOW.
When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master may also issue another START condition. When a
START condition is issued while the bus is active, it is called a repeated START condition.
The TLV320AIC3107 also responds to and acknowledges a General Call, which consists of the master issuing a
command with a slave address byte of 00H.
Figure 35. I
2
C Write
Figure 36. I
2
C Read
In the case of an I
2
C register write, if the master does not issue a STOP condition, then the device enters auto-
increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.
Similarly, in the case of an I
2
C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues an ACKNOWLEDGE, the slave takes over control of SDA bus and transmit for the
next 8 clocks the data of the next incremental register.
10.5.1.1 I
2
C Bus Debug in a Glitched System
Occasionally, some systems may encounter noise or glitches on the I
2
C bus. In the unlikely event that this
affects bus performance, then it can be useful to use the I
2
C Debug register. This feature terminates the I
2
C bus
error allowing this I
2
C device and system to resume communications. The I
2
C bus error detector is enabled by
default. The TLV320AIC3107 I
2
C error detector status can be read from Page 0, Register 107, bit D0. If desired,
the detector can be disabled by writing to Page 0, Register 107, bit D2.
10.5.1.2 Register Map Structure
The register map of the TLV320AIC3107 actually consists of two pages of registers, with each page containing
128 registers. The register at address zero on each page is used as a page-control register, and writing to this
register determines the active page for the device. All subsequent read/write operations access the page that is
active at the time, unless a register write is performed to change the active page. The active page defaults to
page 0 on device reset.
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