SDI Audio IP Cores User Guide Last updated for Altera Complete Design Suite: 14.0 UG-SDI-AUD Subscribe 2014.06.30 Send Feedback 101 Innovation Drive San Jose, CA 95134 www.altera.
TOC-2 SDI Audio IP Cores User Guide Contents SDI Audio IP Overview.......................................................................................1-1 SDI Audio IP Getting Started.............................................................................2-1 Installing and Licensing IP Cores..............................................................................................................2-1 OpenCore Plus IP Evaluation......................................................................
SDI Audio IP Cores User Guide TOC-3 SDI Audio Embed Registers.......................................................................................................................5-1 SDI Audio Extract Registers.......................................................................................................................5-4 SDI Clocked Audio Input Registers..........................................................................................................
1 SDI Audio IP Overview 2014.06.30 UG-SDI-AUD Subscribe Send Feedback ® ® The Altera SDI Audio MegaCore functions ease the development of video and image processing designs. For some instances, you combine the audio and video into one digital signal, and at other times you process the audio and video signals separately. ® The SDI Audio IP cores are part of the MegaCore IP Library, which is distributed with the Quartus II software and downloadable from the Altera website at www.altera.com.
1-2 SDI Audio IP Overview UG-SDI-AUD 2014.06.30 Related Information • Serial Digital Interface (SDI) IP Core User Guide For information about SDI IP core. • SDI II IP Core User Guide For information about SDI II IP core.
SDI Audio IP Getting Started 2 2014.06.30 UG-SDI-AUD Send Feedback Subscribe Installing and Licensing IP Cores The Quartus II software includes the Altera IP Library. The library provides many useful IP core functions for production use without additional license. You can fully evaluate any licensed Altera IP core in simulation and in hardware until you are satisfied with its functionality and performance.
2-2 IP Catalog and Parameter Editor UG-SDI-AUD 2014.06.30 • Program a device with your IP core and verify your design in hardware OpenCore Plus evaluation supports the following two operation modes: • Untethered—run the design containing the licensed IP for a limited time. • Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a connection between your board and the host computer.
UG-SDI-AUD 2014.06.30 Specifying IP Core Parameters and Options 2-3 Figure 2-2: Quartus II IP Catalog Search and filter IP for your target device Double-click to customize, right-click for information ™ Note: The IP Catalog and parameter editor replace the MegaWizard Plug-In Manager in the Quartus II software. The Quartus II software may generate messages that refer to the MegaWizard Plug-In Manager. Substitute "IP Catalog and parameter editor" for "MegaWizard Plug-In Manager" in these messages.
2-4 Simulating Altera IP Cores in other EDA Tools UG-SDI-AUD 2014.06.30 • Specify options for processing the IP core files in other EDA tools. 4. Click Finish or Generate to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .qip or .qsys IP variation file and HDL files for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example design for hardware testing. 5.
3 SDI Audio IP Functional Description 2014.06.30 UG-SDI-AUD Subscribe Send Feedback The following sections describe the block diagrams and components for the SDI Audio IP cores. • • • • Audio Embed IP core Audio Extract IP core Clocked Audio Input IP core Clocked Audio Output IP core SDI Audio Embed IP Core The SDI Audio Embed Audio IP core embeds audio into the SD-, HD-, and 3G-SDI video standards.
3-2 UG-SDI-AUD 2014.06.30 SDI Audio Embed Parameters Figure 3-1: SDI Audio Embed IP Core Block Diagram Avalon-ST Audio to Audio Embed with Avalon Only FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO SD/HD/3G-SDI SD/HD/3G-SDI Audio Embedder Packet Creation Packet Distribution Channel Status RAM SD/HD Audio Embedder Avalon-MM Register Interface Audio Embed or Audio Embed with Avalon The SDI Audio Embed IP core embeds up to 16 channels or 8 channel pairs.
UG-SDI-AUD 2014.06.30 SDI Audio Embed Parameters 3-3 Table 3-1: SDI Audio Embed Parameters Parameter Value Number of supported audio groups 1, 2, 3, 4 Async Audio Interface On or Off Description Specifies the maximum number of audio groups supported. Each audio group consists of 4 audio channels (2 channel pairs) . You must specify all the four channels to the same sample frequencies. Turn on to enable the Asynchronous input. In this mode, the audio clock provides higher than 64* sample rate.
3-4 UG-SDI-AUD 2014.06.30 SDI Audio Extract IP Core Parameter Value Include AvalonMM control interface Description On or Off Turn on to include the Avalon-MM control interface. When you turn on this parameter, the register interface signals appear at the top level. Otherwise, the direct control interface signals appear at the top level.
UG-SDI-AUD 2014.06.30 SDI Audio Extract Parameters 3-5 • A register interface block that provides support for an Avalon-MM control bus The clock recovery block recreates a 64 × sample rate clock, which you can use to clock the audio output logic. As the component recreates this clock from a 200-MHz reference clock, the created clock may have a higher jitter than is desirable. A digital PLL synchronizes this created clock to a 24-kHz reference source.
3-6 UG-SDI-AUD 2014.06.30 SDI Clocked Audio Input IP Core Parameter Include clock Value Description On or Turn on to enable the logic to recover both a sample rate clock and a 64 × Off sample rate clock. With HD-SDI inputs, the core generates the output by using the embedded clock phase information. With SD-SDI inputs, the core generates this output by using the counters running on the 27-MHz video clock. This generation limits the SD-SDI embedded audio to being synchronous to the video.
UG-SDI-AUD 2014.06.30 SDI Clocked Audio Output IP Core 3-7 SDI Clocked Audio Output IP Core The SDI Clocked Audio Output IP core accepts clocked Avalon-ST audio and converts to audio in modified AES formats. SDI Audio Clocked Audio Output Parameters The following table lists the parameters for the SDI Clocked Audio Output IP cores. Table 3-4: SDI Clocked Audio Output Parameters Parameter FIFO size Value 3–10 Description Defines the internal FIFO depth. For example, a value of 3 means 2³ = 8.
3-8 UG-SDI-AUD 2014.06.30 Avalon-ST Audio Interface Avalon-ST Audio Interface To allow the standard components inside Qsys to interconnect, you must define the Avalon-ST audio interface. The Avalon-ST audio interface must carry audio to and from physical AES3 interfaces; which means to support the AES3 outputs, the interface must transport the extra V, U, and C bits. You may create the P bit. Each audio block consists of 192 frames, and each frame has channels 1 and 2.
UG-SDI-AUD 2014.06.30 3-9 Avalon-ST Audio Interface audio data size is configurable at compile time and matches the audio data sample size. Including the aux, the audio data word would be 24 bits. In Avalon-ST audio, the data is packed as 24 bit symbols, typically with 1 symbol per beat [23:0]. The core transmits the audio control data as a packet after the audio data to meet the latency requirements. The packet type identifier defines the packet type.
3-10 UG-SDI-AUD 2014.06.30 Instantiating the SDI Audio IP Cores This figure shows an example of two audio channels, where the channel signal indicates either channel 1 or channel 2. Each channel has a start of packet and an end of packet signal, which allows the channel interleaving and de-interleaving.
UG-SDI-AUD 2014.06.30 Guidelines 3-11 5. Click Finish. 6. In the IP Catalog (Tools > IP Catalog), locate and double-click the variant audio_embed_avalon_top.v file. The SDI Audio Embed parameter editor appears. 7. In the SDI Audio Embed parameter editor, click Finish to regenerate the variant audio_embed_avalon_top.v file and produce the simulation model. 8. Repeat steps 6 to 9 for the remaining variant files in the megacore_build directory. 9.
SDI Audio IP Interface Signals 4 2014.06.30 UG-SDI-AUD Subscribe Send Feedback SDI Audio Embed Signals The following tables list the signals for the SDI Audio Embed IP cores. This table lists the general input and output signals. Table 4-1: SDI Audio Embed General Input and Output Signals Signal Width Direction Description reset [0:0] Input This signal resets the system.
4-2 UG-SDI-AUD 2014.06.30 SDI Audio Embed Signals Table 4-2: SDI Audio Embed Video Input and Output Signals Signal vid_clk Width Direction [0:0] Input Description The video clock that is typically 27 MHz for SD-SDI, 74.25 MHz or 74.17 MHz for HD-SDI, or 148.5 MHz or 148.35 MHz for 3GSDI standards. You can use higher clock rates with the vid_ datavalid signal. Set exclusive clock group to aud_clk and vid_clk to prevent unstable or flickering image.
UG-SDI-AUD 2014.06.30 SDI Audio Embed Signals 4-3 This table lists the audio input signals. Table 4-3: SDI Audio Embed Audio Input Signals N is the number of audio group. Signal aud_clk Width Direction [2N–1:0] Input Description Set this clock to 3.072 MHz that is synchronous to the extracted audio. In asynchronous mode, set this to any frequency above 3.072 MHz. Altera recommends that you set this clock to 50 MHz.
4-4 UG-SDI-AUD 2014.06.30 SDI Audio Embed Signals Table 4-5: SDI Audio Embed Register Interface Signals Signal Width Direction Description reg_clk [0:0] Input Clock for the Avalon-MM register interface. reg_reset [0:0] Input Reset for the Avalon-MM register interface. reg_base_addr [5:0] Input Reset for the Avalon-MM register interface. reg_burst_count [5:0] Input Transfer size in bytes. reg_waitrequest [0:0] Output Wait request. reg_write [7:0] Input Write request.
UG-SDI-AUD 2014.06.30 SDI Audio Extract Signals Signal Width Direction 4-5 Description sine_freq_ch4 [7:0] Input This signal does the same function as the sine channel 4 frequency register. csram_addr [5:0] Input Channel status RAM address. csram_we [0:0] Input Drive this signal high for a single cycle of reg_clk signal to load the value of the csram_data port into the channel status RAM at the address on the csram_addr port.
4-6 UG-SDI-AUD 2014.06.30 SDI Audio Extract Signals Table 4-8: SDI Audio Extract Video Input Signals Signal Width Direction Description vid_clk [0:0] Input The video clock that is typically 27 MHz for SD-SDI, 74.25 MHz or 74.17 MHz for HD-SDI, or 148.5 MHz or 148.35 MHz for 3GSDI standards. You can use higher clock rates with the vid_ datavalid signal. vid_std [1:0] Input Indicates the received video standard. Applicable for 3G-SDI, dual standard, and triple standard modes only.
UG-SDI-AUD 2014.06.30 SDI Audio Extract Signals Signal Width Direction 4-7 Description aud_ws_in [0:0] Input Some audio receivers provide a word select output to align the serial outputs of several audio extract cores. In these circumstances, assert this signal to control the output timing of the audio extract externally, otherwise set it to 0. This signal must be a repeating cycle of high for 32 aud_clk cycles followed by low for 32 aud_clk cycles.
4-8 UG-SDI-AUD 2014.06.30 SDI Audio Clocked Input Signals Table 4-11: SDI Audio Extract Direct Control Interface Signals Signal Width Direction Description reg_clk [0:0] Input Clock for the direct control interface. audio_control [7:0] Input This signal does the same function as the audio control register. audio_presence [7:0] Input This signal does the same function as the audio presence register.
UG-SDI-AUD 2014.06.30 SDI Audio Clocked Output Signals Signal Width Direction 4-9 Description aes_ws [0:0] Input Audio word select. aes_data [0:0] Input Audio data input in internal AES format. This table lists the Avalon-ST audio signals when you instantiate the SDI Audio Clocked Input IP core in Qsys. Table 4-13: SDI Audio Clocked Input Avalon-ST Audio Signals Signal Width Direction Description aud_clk [0:0] Input Clocked audio clock.
4-10 UG-SDI-AUD 2014.06.30 SDI Audio IP Register Interface Signals This table lists the input and output signals. Table 4-15: SDI Audio Clocked Output Input and Output Signals Signal Width Direction Description aes_clk [0:0] Input Audio input clock. aes_de [0:0] Output Audio data enable. aes_ws [0:0] Output Audio word select. aes_data [0:0] Output Audio data input in internal AES format.
UG-SDI-AUD 2014.06.30 SDI Audio IP Register Interface Signals Signal Width Direction Description reg_base_addr [5:0] Input Reset for the Avalon-MM register interface. reg_burst_count [5:0] Input Transfer size in bytes. reg_waitrequest [0:0] Output Wait request. reg_write [7:0] Input Write request. reg_writedata [0:0] Input Data to be written to target. reg_read [0:0] Input Read request. reg_readdatavalid [0:0] Output Requested read data valid after read latency.
SDI Audio IP Registers 5 2014.06.30 UG-SDI-AUD Subscribe Send Feedback SDI Audio Embed Registers The following tables list the registers for the SDI Audio Embed IP core.
5-2 UG-SDI-AUD 2014.06.30 SDI Audio Embed Registers Table 5-2: SDI Audio Embed Registers Bit Name Access Description Audio Control Register 7:0 Audio group enable RW Enables the embedding of each audio group. When working with HD-SDI or 3G-SDI video, this register also enables the embedding of the audio control packet when one or more audio groups are enabled.
UG-SDI-AUD 2014.06.30 SDI Audio Embed Registers 5-3 Video Status Register 7:0 Active channel RO Reports the detected video input standard. • Bits[7:5] = Picture structure code. Defined values for picture structure code are: • • • • • • • 001b = 486 or 576 line SD-SDI 100b = 720 line HD-SDI 101b = 1080 line HD-SDI 010b = 1080 line 3G-SDI 011b = 1080 line 3GA-SDI 110b = 720 line 3GA-SDI 111b = 720 line 3GB-SDI • Bit[4] = 0b—Interlace or segmented frame, 1b—Progressive. • Bits[3:0] = Frame rate code.
5-4 UG-SDI-AUD 2014.06.30 SDI Audio Extract Registers Strip Control Register 3:0 Strip enable RW Enables the removal of both ACP and ADP (and any SD-SDI EDP) for each of the four audio groups. 7:4 Unused — Reserved for future use. Strip Status Register 3:0 Data packet present RO Reports which audio data groups are detected in the SDI stream. 3:0 When in 3G-SDI Level B mode, this register reports the presence of audio on Link A (Link B should be a duplicate).
UG-SDI-AUD 2014.06.30 SDI Audio Extract Registers 5-5 Table 5-3: SDI Audio Extract Register Map Bytes Offset Name 00h Audio Control Register 01h Audio Presence Register 02h Audio Status Register 03h SD EDP Presence Register 04h Error Status Register 05h Reserved 06h FIFO Status Register 07h Clock Status Register 08h-09h Reserved 10h-3Fh Channel Status RAM (0×00), (0×01), ...
5-6 UG-SDI-AUD 2014.06.30 SDI Audio Extract Registers Audio Presence Register 3:0 Data packet present RW When you specify the Channel Status RAM parameter to 2, this field selects the channel pair for the RAM written to by registers 10h to 3Fh. If you specify the Channel Status RAM parameter to 0 or 1, ignore this signal. Reports which audio data groups are detected in the SDI stream.
UG-SDI-AUD 2014.06.30 SDI Audio Extract Registers 5-7 SD EDP Presence Register 3:0 EDP Present RO Reports which audio extended data groups are detected in the SD-SDI stream. 7:4 Unused — Reserved for future use. Error Status Register 3:0 Error counter RW Counts up to 15 errors since last reset. Write 1b to any bit of this field to reset the entire counter to zero. 4 Ancillary CS fail RW Indicates that an error has been detected in the ancillary packet checksum.
5-8 UG-SDI-AUD 2014.06.30 SDI Clocked Audio Input Registers Clock Status Register 7 74.17-MHz video clock RO To create a 48-kHz signal synchronous to the video clock, you must detect whether a 1 or 1/1.001 video clock rate is used. If you detect a 1/1.001 video clock rate, this field returns high. Channel Status RAM 7:0 Channel status data WO Read accesses within the address range 10h to 3Fh to the channel status RAM.
UG-SDI-AUD 2014.06.30 SDI Clocked Audio Output Registers 5-9 SDI Clocked Audio Output Registers The following tables list the registers for the SDI Clocked Audio Output IP core.
SDI Audio IP Design Example 6 2014.06.30 UG-SDI-AUD Send Feedback Subscribe Altera provides a design example with the SDI Audio Embed and Extract IP cores. This design example includes the SDI Audio IP cores and instances of the SDI IP cores. This section discusses the requirements and related procedures to demonstrate the SDI Audio example design with the Stratix IV GX Audio Video Development Kit. Components of Design Example This figure shows a high-level block diagram of the design example.
6-2 SDI Transmitter P0 UG-SDI-AUD 2014.06.30 SDI Transmitter P0 The triple-standard SDI transmitter that outputs a 3G-SDI (2.970 Gbps), HD-SDI (1.485 Mbps), or SD-SDI (270 Mbps) data stream. This transmitter gets the parallel data source from the SDI Audio Embed IP core. The SDI Audio Embed component embeds the internally generated audio in AES format into the internally generated video. The transmitter transmits the serial signal through a BNC cable to the receiver of the SDI duplex instance.
UG-SDI-AUD 2014.06.30 Transceiver Dynamic Reconfiguration Control Logic 6-3 Transceiver Dynamic Reconfiguration Control Logic The transceiver dynamic reconfiguration control logic block handles the reconfiguration of the receiver in the SDI duplex.
6-4 UG-SDI-AUD 2014.06.30 Running the Design Example This table lists the function of each user-defined dual in-line package (DIP) switch settings. Table 6-2: Function of Each DIP Switch DIP Switch Description 8 Resets the system. 7 Resets the Audio Extract IP core status registers. 6–3 Unused. 2–1 Configure the internally-generated video standards for both SDI transmitters.
UG-SDI-AUD 2014.06.30 Transmit SD-SDI with Embedding of Audio Group 1 6-5 Transmit SD-SDI with Embedding of Audio Group 1 To transmit the SD-SDI video standard, follow these steps: 1. Set DIP switch[2:1] = 00 2. The demonstration runs and the LEDs indicate the following conditions: a. LED D16 blinks indicating the heartbeat of the receiver's recovered clock. b. LED D17 illuminates when the receiver is frame locked. c. LED D18 illuminates when the receiver is TRS locked. d.
6-6 UG-SDI-AUD 2014.06.30 Transmit 3G-SDI Level A with Embedding of Audio Group 1, 2 and 3 Figure 6-3: Condition of LEDs for Transmitting HDI-SDI Video Standard D6 D7 D8 D9 D10 D11 D12 D13 D16 D17 D18 D19 D20 D21 D22 D23 3. The external waveform monitor (WFM700) displays the following observation: a. Colorbar video pattern b. Video format detected is 1080i 60.00 c. Embedded audio standard detected is SMPTE299M d.
UG-SDI-AUD 2014.06.30 Transmit 3G-SDI Level B with Embedding of Audio Group 1, 2, 3 and 4 6-7 d. e. f. g. LED D17 illuminates when the receiver is frame locked. LED D18 illuminates when the receiver is TRS locked. LED D19 illuminates when the receiver is alignment locked. LEDs D23, D22, D21 and D20 illuminate when the data packet of audio groups 1, 2, 3 and 4 are detected in the incoming SDI stream. This figure shows the condition of the LEDs.
Additional Information 7 2014.06.30 UG-SDI-AUD Send Feedback Subscribe Additional information about the document and Altera. Document Revision History Date Version June 2014 Changes 2014.06.30 • Created a separate user guide for SDI Audio IP cores. • Removed the SDI Audio IP section from the SDI MegaCore function User Guide. • Added new registers for SDI Audio Embed IP core: SD EDP Control, Strip Control, and Strip Status.
7-2 How to Contact Altera UG-SDI-AUD 2014.06.30 Related Information • www.altera.com/support • www.altera.com/training • www.altera.
