Specifications

ManualsBrandsAuto Page ManualsAutomobile AlarmCPX-3600

August 2010 Doc ID 13829 Rev 1 1/243

ST72321xx-Auto

8-bit MCU for automotive with 32/60 Kbyte Flash/ROM,

ADC, 5 timers, SPI, SCI, I2C interface

Features

Memories

■ 32 to 60 Kbyte dual voltage High Density Flash

(HDFlash) or ROM ROM with readout

protection capability. In-application

programming and in-circuit programming for

HDFlash devices

■ 1 to 2 Kbyte RAM

■ HDFlash endurance: 100 cycles, data retention

20 years

Clock, reset and supply management

■ Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability

■ Clock sources: crystal/ceramic resonator

oscillators, internal RC oscillator and bypass

for external clock

■ PLL for 2x frequency multiplication

■ 4 power saving modes: Halt, Active Halt, Wait

and Slow

Interrupt management

■ Nested interrupt controller

■ 14 interrupt vectors plus TRAP and RESET

■ Top Level Interrupt (TLI) pin on 64-pin devices

■ 15 external interrupt lines (on 4 vectors)

1 analog peripheral

■ 10-bit ADC with up to 16 input ports

Up to 48 I/O ports

■ 48//32 multifunctional bidirectional I/O lines

■ 34//22 alternate function lines

■ 16//12 high sink outputs

5 timers

■ Main clock controller with Real-time base,

Beep and Clock-out capabilities

■ Configurable watchdog timer

■ Two 16-bit timers with 2 input captures, 2

output compares, external clock input on 1

timer, PWM and pulse generator modes

■ 8-bit PWM auto-reload timer with 2 input

captures, 4 PWM outputs, output compare and

time base interrupt, external clock with event

detector

3 communications interfaces

■ SPI synchronous serial interface

■ SCI asynchronous serial interface

■ I

C multimaster interface

Instruction set

■ 8-bit data manipulation

■ 63 basic instructions

■ 17 main addressing modes

■ 8x8 unsigned multiply instruction

Development tools

■ Full hardware/software development package,

ICT capability

Table 1. Device summary

Reference Part number

ST72321xx-Auto

ST72321AR6-Auto,

ST72321R6-Auto,

ST72321AR7-Auto,

ST72321J7-Auto, ST72321R7-Auto

ST72321AR9-Auto,

ST72321J9-Auto, ST72321R9-Auto

LQFP64

10 x 10

LQFP64

14 x 14

LQFP44

10 x 10

www.st.com

Summary of content (243 pages)

PAGE 1
ST72321xx-Auto 8-bit MCU for automotive with 32/60 Kbyte Flash/ROM, ADC, 5 timers, SPI, SCI, I2C interface Features Memories ■ 32 to 60 Kbyte dual voltage High Density Flash (HDFlash) or ROM ROM with readout protection capability.
PAGE 2
Contents ST72321xx-Auto Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 Package pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 Package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 Register and memory map . . . . . .
PAGE 3
ST72321xx-Auto 6.4 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.5 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.6 7 9 6.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.5.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5.3 External power-on RESET . . . . . . . . . . . . .
PAGE 4
Contents ST72321xx-Auto 9.2 10 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.3 I/O port implementation . .
PAGE 5
ST72321xx-Auto 12.3 13 Contents 12.2.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.2.2 Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.2.3 Counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.2.4 Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.2.
PAGE 6
Contents ST72321xx-Auto 13.7.4 Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.7.5 Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.7.6 Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 117 13.7.7 Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 117 13.7.8 Output compare 2 high register (OC2HR) . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
ST72321xx-Auto 15 16 Contents Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . 135 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 15.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 15.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 15.4 Functional description . . . . . . . . .
PAGE 8
Contents 17 18 ST72321xx-Auto 16.7.2 I2C status register 1 (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 16.7.3 I2C status register 2 (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 16.7.4 I2C clock control register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.7.5 I2C data register (DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.7.6 I2C own address register (OAR1) . . . . . .
PAGE 9
ST72321xx-Auto 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 Contents 19.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 10
Contents ST72321xx-Auto 19.9.2 ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 19.10 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 19.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 211 19.11.1 SPI (serial peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 19.11.2 I2C - inter IC control interface . . . . . . . . . . . . .
PAGE 11
ST72321xx-Auto Contents 22.1.7 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 22.1.8 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 22.1.9 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 240 22.1.10 I2C multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 22.1.11 Readout protection with LVD . . . . . . . . . . . . . . .
PAGE 12
List of tables ST72321xx-Auto List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47.
PAGE 13
ST72321xx-Auto Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97.
PAGE 14
List of tables Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145.
PAGE 15
ST72321xx-Auto List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
PAGE 16
List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93.
PAGE 17
ST72321xx-Auto Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. List of figures ADC error classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 64-pin (14x14) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 64-pin (10x10) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 18
Description 1 ST72321xx-Auto Description The ST72321xx-Auto Flash and ROM devices are members of the ST7 microcontroller family designed for mid-range automotive applications running from 3.8 to 5.5V. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code.
PAGE 19
ST72321xx-Auto Description Figure 1.
PAGE 20
Package pinout and pin description ST72321xx-Auto Package pinout and pin description 2.1 Package pinout Figure 2.
PAGE 21
ST72321xx-Auto PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP / ICCSEL PA7 (HS) / SCLI PA6 (HS) / SDAI PA5 (HS) PA4 (HS) 44-pin LQFP package pinout RDI / PE1 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 ARTCLK / (HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 ei0 ei2 4 30 5 29 ei3 6 28 7 27 8 26 9 25 ei1 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 VSS_1 VDD_1 PA3 (HS) PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA P
PAGE 22
Package pinout and pin description 2.2 ST72321xx-Auto Pin description In the device pin description table, the RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Refer to Section 9: I/O ports on page 70 for more details on the software configuration of the I/O ports. Table 3. Device pin description Level Input Output float wpu OD PP Main function (after reset) LQFP44 Port LQFP64 Type Pin No.
PAGE 23
ST72321xx-Auto Table 3.
PAGE 24
Package pinout and pin description Device pin description (continued) Port PP OD Output ana int wpu Input float Input Pin name Type Level LQFP44 LQFP64 Pin No. Output Table 3.
PAGE 25
ST72321xx-Auto Device pin description (continued) Port PE2 (Flash device) 63 - - PP OD ana int Output PE3 I/O CT X X Alternate function X X Port E2 Caution: In ROM devices, no weak pull-up present on this port. In LQFP44 this pin is not connected to an internal pull-up like other unbonded pins. It is recommended to configure it as output push-pull to avoid added current consumption.
PAGE 26
Register and memory map 3 ST72321xx-Auto Register and memory map As shown in Figure 4, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of RAM and up to 60 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors.
PAGE 27
ST72321xx-Auto Table 4.
PAGE 28
Register and memory map Table 4.
PAGE 29
ST72321xx-Auto Flash program memory 4 Flash program memory 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
PAGE 30
Flash program memory Figure 5. ST72321xx-Auto Memory map and sector address 4K 8K 10K 16K 24K 32K 48K 60K 1000h 3FFFh FLASH MEMORY SIZE 7FFFh 9FFFh SECTOR 2 BFFFh D7FFh 2 Kbytes DFFFh 4.3.1 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes EFFFh 4 Kbytes SECTOR 1 FFFFh 4 Kbytes SECTOR 0 Readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory.
PAGE 31
ST72321xx-Auto Figure 6. Flash program memory Typical ICC interface PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note 4) 9 7 5 3 1 10 8 6 4 2 APPLICATION RESET SOURCE See Note 2 10k ICCDATA ICCCLK ST7 RESET See Note 1 ICCSEL/VPP OSC1 CL1 OSC2 VDD CL2 VSS APPLICATION POWER SUPPLY APPLICATION I/O 1.
PAGE 32
Flash program memory 4.6 ST72321xx-Auto IAP (in-application programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (such as user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored).
PAGE 33
ST72321xx-Auto Central processing unit (CPU) 5 Central processing unit (CPU) 5.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation. 5.2 5.
PAGE 34
Central processing unit (CPU) 5.3.1 ST72321xx-Auto Accumulator (A) The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations. 5.3.2 Index registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation (the Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.
PAGE 35
ST72321xx-Auto Central processing unit (CPU) Table 7. Arithmetic management bits (continued) Bit Name 1 0 Function Z Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. C Carry/borrow This bit is set and cleared by hardware and software.
PAGE 36
Central processing unit (CPU) ST72321xx-Auto The stack pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
PAGE 37
ST72321xx-Auto Supply, reset and clock management 6 Supply, reset and clock management 6.1 Introduction The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 9. For more details, refer to the dedicated parametric section. 6.
PAGE 38
Supply, reset and clock management 6.3 ST72321xx-Auto Phase locked loop If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2. Caution: The PLL is not recommended for applications where timing accuracy is required (see Section 19.5.5: PLL characteristics on page 198). Figure 10.
PAGE 39
ST72321xx-Auto Supply, reset and clock management Crystal/ceramic oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of four oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 21.1.1: Flash configuration on page 223 for more details on the frequency ranges).
PAGE 40
Supply, reset and clock management ST72321xx-Auto 6.5 Reset sequence manager (RSM) 6.5.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 11: ● External RESET source pulse ● Internal LVD RESET (low voltage detection) ● Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
PAGE 41
ST72321xx-Auto Supply, reset and clock management Figure 12. RESET sequence phases RESET INTERNAL RESET 256 or 4096 CLOCK CYCLES ACTIVE PHASE 6.5.2 FETCH VECTOR Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Section 19.
PAGE 42
Supply, reset and clock management 6.5.5 ST72321xx-Auto Internal watchdog RESET The RESET sequence generated by an internal Watchdog counter overflow is shown in Figure 13. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 13. RESET sequences VDD VIT+(LVD) VIT-(LVD) LVD RESET RUN SHORT EXT. RESET RUN Active Phase tw(RSTL)out th(RSTL)in LONG EXT.
PAGE 43
ST72321xx-Auto 6.6 Supply, reset and clock management System integrity management (SI) The System Integrity Management block contains the Low Voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. 6.6.1 Low voltage detector (LVD) The low voltage detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.
PAGE 44
Supply, reset and clock management ST72321xx-Auto Figure 14. Low voltage detector versus reset VDD Vhys VIT+ VIT- RESET 6.6.2 Auxiliary voltage detector (AVD) The auxiliary voltage detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply or the external EVD pin voltage level (VEVD).
PAGE 45
ST72321xx-Auto Supply, reset and clock management Figure 15. Using the AVD to monitor VDD (AVDS bit = 0) VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset) Vhyst VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD) trv AVDF bit 0 1 RESET VALUE VOLTAGE RISE TIME 1 0 AVD INTERRUPT REQUEST IF AVDIE bit = 1 INTERRUPT PROCESS INTERRUPT PROCESS LVD RESET Monitoring a voltage on the EVD pin This mode is selected by setting the AVDS bit in the SICSR register.
PAGE 46
Supply, reset and clock management ST72321xx-Auto Figure 16. Using the voltage detector to monitor the EVD pin (AVDS bit = 1) VEVD Vhyst VIT+(EVD) VIT-(EVD) AVDF 0 1 0 AVD INTERRUPT REQUEST IF AVDIE = 1 INTERRUPT PROCESS 6.6.3 Low power modes Table 11. Effect of low power modes on SI Mode 6.6.4 INTERRUPT PROCESS Effect Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode. Halt The SICSR register is frozen.
PAGE 47
ST72321xx-Auto 6.6.5 Supply, reset and clock management System Integrity (SI) Control/Status register (SICSR) Reset value: 000x 000x (00h) SICSR 7 6 5 4 AVDS AVDIE AVDF LVDRF Reserved WDGRF RW RW RW RW - RW 2 1 0 SICSR description Table 13. Bit 3 Name Function AVDS Voltage Detection selection This bit is set and cleared by software. Voltage Detection is available only if the LVD is enabled by option byte.
PAGE 48
Supply, reset and clock management ST72321xx-Auto Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog); the LVDRF flag remains set to keep trace of the original failure. In this case, software can detect a watchdog reset but cannot detect an external reset. Caution: 48/243 When the LVD is not activated with the associated option byte, the WDGRF flag cannot be used in the application.
PAGE 49
ST72321xx-Auto Interrupts 7 Interrupts 7.
PAGE 50
Interrupts ST72321xx-Auto Table 15. Interrupt software priority levels Interrupt software priority Level I1 I0 Low 1 0 Level 1 0 1 Level 2 0 0 1 1 Level 0 (main) High Level 3 (= interrupt disable) Figure 17.
PAGE 51
ST72321xx-Auto Interrupts When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. 2 TLI, RESET and TRAP can be considered as having the highest software priority in the decision process.
PAGE 52
Interrupts ST72321xx-Auto flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be serviced) will therefore be lost if the clear sequence is executed. 7.
PAGE 53
ST72321xx-Auto Interrupts HARDWARE PRIORITY TRAP IT0 IT1 IT1 IT2 IT2 IT3 I0 I1 3 1 1 3 1 1 2 0 0 1 0 1 3 1 1 3 1 1 USED STACK = 20 BYTES SOFTWARE PRIORITY LEVEL IT0 TRAP IT3 IT4 IT1 IT2 Figure 20. Nested interrupt management RIM IT4 IT4 MAIN MAIN 11 / 10 3/0 10 7.5 Interrupt register description 7.5.1 CPU CC register interrupt bits CPU CC Reset value: 111x 1010 (xAh) 7 6 5 4 3 2 1 0 1 1 I1 H I0 N Z C RW RW RW RW RW RW Table 16.
PAGE 54
Interrupts ST72321xx-Auto Table 17. Interrupt software priority levels Interrupt software priority Level I1 I0 Low 1 0 Level 1 0 1 Level 2 0 0 1 1 Level 0 (main) Level 3 (= interrupt disable(1)) High 1. TLI, TRAP and RESET events can interrupt a level 3 program. 7.5.2 Interrupt software priority registers (ISPRx) These four registers are read/write, with the exception of bits 7:4 of ISPR3, which are read only.
PAGE 55
ST72321xx-Auto Interrupts The TLI, RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered.
PAGE 56
Interrupts Table 20. No. ST72321xx-Auto Interrupt mapping Source block RESET Description Register label Priority order Reset Exit from Halt (1) Address vector yes FFFEh-FFFFh no FFFCh-FFFDh yes FFFAh-FFFBh yes FFF8h-FFF9h yes FFF6h-FFF7h yes FFF4h-FFF5h N/A TRAP 0 1 TLI Software interrupt External top level interrupt EICR MCC/RTC Main clock controller time base interrupt MCCSR 2 ei0 External interrupt port A3..0 3 ei1 External interrupt port F2..
PAGE 57
ST72321xx-Auto Interrupts 7.6 External interrupts 7.6.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 21). This control allows to have up to four fully independent external interrupt source sensitivities.
PAGE 58
Interrupts ST72321xx-Auto Figure 21. External interrupt control bits PORT A [3:0] INTERRUPTS PAOR.3 PADDR.3 EICR IS20 IS21 SENSITIVITY PA3 CONTROL IPA BIT PORT F [2:0] INTERRUPTS IS21 SENSITIVITY PF2 CONTROL PORT B [3:0] INTERRUPTS PBOR.3 PBDDR.3 IS10 SENSITIVITY IPB BIT PB7 58/243 ei1 INTERRUPT SOURCE IS11 CONTROL PBOR.7 PBDDR.7 PF2 PF1 PF0 EICR PB3 PORT B [7:4] INTERRUPTS ei0 INTERRUPT SOURCE EICR IS20 PFOR.2 PFDDR.
PAGE 59
ST72321xx-Auto 7.6.2 Interrupts External interrupt control register (EICR) EICR Reset value: 0000 0000 (00h) 7 6 7:6 5 4:3 2 1 0 4 3 2 1 0 IS1[1:0] IPB IS2[1:0] IPA TLIS TLIE RW RW RW RW RW RW Table 21. Bit 5 EICR register description Name Function IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: - ei2 (port B3..0) (see Table 22) - ei3 (port B7..
PAGE 60
Interrupts ST72321xx-Auto Table 22. Interrupt sensitivity - ei2 (port B3..0) External interrupt sensitivity IS11 IS10 IPB bit = 0 IPB bit = 1 0 0 Falling edge and low level Rising edge and high level 0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only 1 1 Table 23. Rising and falling edge Interrupt sensitivity - ei3 (port B7..
PAGE 61
ST72321xx-Auto Table 26. Interrupts Nested interrupts register map and reset values Address (Hex.
PAGE 62
Power saving modes ST72321xx-Auto 8 Power saving modes 8.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 22): Slow, Wait (Slow Wait), Active Halt and Halt. After a RESET the normal operating mode is selected by default (Run mode).
PAGE 63
ST72321xx-Auto Power saving modes Figure 23. Slow mode clock transitions fOSC2/2 fOSC2/4 fOSC2 fCPU MCCSR fOSC2 00 CP1:0 01 SMS NORMAL RUN MODE NEW SLOW REQUEST FREQUENCY REQUEST 8.3 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced to ‘10’, to enable all interrupts.
PAGE 64
Power saving modes ST72321xx-Auto Figure 24. Wait mode flowchart WFI INSTRUCTION OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON OFF 10 N RESET Y N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON 10 256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON ON XX(1) FETCH RESET VECTOR OR SERVICE INTERRUPT 1. Before servicing an interrupt, the CC register is pushed on the stack.
PAGE 65
ST72321xx-Auto 8.4 Power saving modes Active Halt and Halt modes Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register) as shown in Table 27. Table 27. 8.4.
PAGE 66
Power saving modes ST72321xx-Auto Figure 25. Active Halt timing overview RUN ACTIVE HALT 256 OR 4096 CPU CYCLE DELAY(1) HALT INSTRUCTION [MCCSR.OIE = 1] RESET OR INTERRUPT RUN FETCH VECTOR 1. This delay occurs only if the MCU exits Active Halt mode by means of a RESET. Figure 26. Active Halt mode flowchart HALT INSTRUCTION (MCCSR.
PAGE 67
ST72321xx-Auto 8.4.2 Power saving modes Halt mode The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 11: Main clock controller with real-time clock and beeper (MCC/RTC) on page 82 for more details on the MCCSR register). The MCU can exit Halt mode on reception of either a specific interrupt (see Section Table 20.
PAGE 68
Power saving modes ST72321xx-Auto Figure 28. Halt mode flowchart HALT INSTRUCTION (MCCSR.OIE = 0) ENABLE WDGHALT (1) WATCHDOG 0 DISABLE 1 WATCHDOG RESET OSCILLATOR PERIPHERALS (2) CPU I[1:0] BITS OFF OFF OFF 10 N RESET Y N INTERRUPT (3) Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON XX (4) 256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON ON XX (4) FETCH RESET VECTOR OR SERVICE INTERRUPT 1. WDGHALT is an option bit. See Section 21.1.
PAGE 69
ST72321xx-Auto Power saving modes Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, re-initialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.
PAGE 70
I/O ports ST72321xx-Auto 9 I/O ports 9.1 Introduction The I/O ports offer different functional modes: ● transfer of data through digital inputs and outputs and for specific pins: ● external interrupt generation ● alternate signal input/output for the on-chip peripherals. An I/O port contains up to eight pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.
PAGE 71
ST72321xx-Auto I/O ports Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed.
PAGE 72
I/O ports ST72321xx-Auto Figure 29. I/O port general block diagram ALTERNATE OUTPUT REGISTER ACCESS 1 VDD 0 P-BUFFER (see table below) ALTERNATE ENABLE PULL-UP (see table below) DR VDD DDR PULL-UP CONDITION DATA BUS OR PAD If implemented OR SEL N-BUFFER DIODES (see table below) DDR SEL DR SEL ANALOG INPUT CMOS SCHMITT TRIGGER 1 0 ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE (eix) Table 29.
PAGE 73
ST72321xx-Auto Table 30.
PAGE 74
I/O ports Caution: ST72321xx-Auto The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
PAGE 75
ST72321xx-Auto I/O ports Table 31.
PAGE 76
I/O ports ST72321xx-Auto Table 34. I/O port register map and reset values (continued) Address (Hex.
PAGE 77
ST72321xx-Auto Watchdog timer (WDG) 10 Watchdog timer (WDG) 10.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared. 10.2 10.
PAGE 78
Watchdog timer (WDG) ST72321xx-Auto Figure 31. Watchdog block diagram RESET fOSC2 MCC/RTC WATCHDOG CONTROL REGISTER (WDGCR) DIV 64 WDGA T6 T5 T4 T3 T2 T1 T0 6-BIT DOWNCOUNTER (CNT) 12-BIT MCC RTC COUNTER MSB 11 10.4 WDG PRESCALER LSB 65 0 DIV 4 TB[1:0] bits (MCCSR Register) How to program the watchdog timeout Figure 32 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds.
PAGE 79
ST72321xx-Auto Watchdog timer (WDG) Figure 33. Exact timeout duration (tmin and tmax) WHERE: tmin0 = (LSB + 128) x 64 x tOSC2 tmax0 = 16384 x tOSC2 tOSC2 = 125ns if fOSC2= 8 MHz CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register TB1 bit TB0 bit (MCCSR reg.) 0 0 1 1 (MCCSR reg.
PAGE 80
Watchdog timer (WDG) 10.5 ST72321xx-Auto Low power modes Table 35. Effect of low power modes on WDG Mode Effect Slow No effect on Watchdog Wait No effect on Watchdog OIE bit in MCCSR register WDGHALT bit in Option Byte 0 0 No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset.
PAGE 81
ST72321xx-Auto Watchdog timer (WDG) 10.9 Register description 10.9.1 Control register (WDGCR) WDGCR 7 Reset value: 0111 1111 (7Fh) 6 5 4 3 WDGA T[6:0] RW RW Table 36. Bit 2 1 0 WDGCR register description Name Function 7 Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. WDGA 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte.
PAGE 82
Main clock controller with real-time clock and beeper (MCC/RTC) ST72321xx-Auto 11 Main clock controller with real-time clock and beeper (MCC/RTC) 11.1 Introduction The Main Clock Controller consists of three different functions: ● a programmable CPU clock prescaler ● a clock-out signal to supply external devices ● a real-time clock timer with interrupt capability Each function can be used independently and simultaneously. 11.
PAGE 83
ST72321xx-Auto Main clock controller with real-time clock and beeper (MCC/RTC) Figure 34. Main clock controller (MCC/RTC) block diagram BC1 BC0 MCCBCR BEEP BEEP SIGNAL SELECTION MCO 12-BIT MCC RTC COUNTER DIV 64 MCO CP1 CP0 SMS TB1 TB0 OIE TO WATCHDOG TIMER OIF MCCSR fOSC2 MCC/RTC INTERRUPT DIV 2, 4, 8, 16 1 CPU CLOCK TO CPU AND PERIPHERALS fCPU 0 11.6 Low power modes Table 38. Effect of low power modes on MCC/RTC Mode Effect No effect on MCC/RTC peripheral.
PAGE 84
Main clock controller with real-time clock and beeper (MCC/RTC) 11.8 Main clock controller registers 11.8.1 MCC control/status register (MCCSR) ST72321xx-Auto MCCSR 7 6 4 3 2 1 0 CP[1:0] SMS TB[1:0] OIE OIF RW RW RW RW RW RW Bit 7 6:5 4 3:2 84/243 5 MCO Table 40. 1 Reset value: 0000 0000 (00h) Name MCO MCCSR register description Function Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software.
PAGE 85
ST72321xx-Auto Main clock controller with real-time clock and beeper (MCC/RTC) Table 40. Bit 0 MCCSR register description (continued) Name Function OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0).
PAGE 86
Main clock controller with real-time clock and beeper (MCC/RTC) Table 44. ST72321xx-Auto Main clock controller register map and reset values Address (Hex.
PAGE 87
ST72321xx-Auto PWM auto-reload timer (ART) 12 PWM auto-reload timer (ART) 12.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit autoreload counter with compare/capture capabilities and of a 7-bit prescaler clock source.
PAGE 88
PWM auto-reload timer (ART) ST72321xx-Auto 12.2 Functional description 12.2.1 Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (ARTCAR). When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected). 12.2.
PAGE 89
ST72321xx-Auto PWM auto-reload timer (ART) Figure 36. Output compare control fCOUNTER ARTARR = FDh COUNTER FDh FEh FFh OCRx PWMDCRx FDh FEh FFh FDh FEh FFh FEh FDh FEh FDh PWMx 12.2.5 Independent PWM signal generation This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during Halt mode.
PAGE 90
PWM auto-reload timer (ART) ST72321xx-Auto Figure 37. PWM auto-reload timer function COUNTER 255 DUTY CYCLE REGISTER (PWMDCRx) AUTO-RELOAD REGISTER (ARTARR) PWMx OUTPUT 000 t WITH OEx=1 AND OPx=0 WITH OEx=1 AND OPx=1 Figure 38. PWM signal from 0% to 100% duty cycle fCOUNTER ARTARR = FDh COUNTER FDh FEh FFh FDh FEh FFh FDh FEh PWMx OUTPUT WITH OEx=1 AND OPx=0 OCRx=FCh OCRx=FDh OCRx=FEh OCRx=FFh t 12.2.
PAGE 91
ST72321xx-Auto PWM auto-reload timer (ART) Figure 39. External event detector example (3 counts) fEXT = fCOUNTER ARTARR = FDh COUNTER FDh FEh FFh FDh FEh FFh FDh OVF ARTCSR READ INTERRUPT IF OIE = 1 ARTCSR READ INTERRUPT IF OIE = 1 t 12.2.8 Input capture function This mode allows the measurement of external signal pulse widths through ARTICRx registers. Each input capture can generate an interrupt independently on a selected input signal transition.
PAGE 92
PWM auto-reload timer (ART) 12.2.9 ST72321xx-Auto External interrupt capability This mode allows the input capture capabilities to be used as external interrupt sources. The interrupts are generated on the edge of the ARTICx signal. The edge sensitivity of the external interrupts is programmable (CSx bit of ARTICCSR register) and they are independently enabled through CIEx bits of the ARTICCSR register. After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.
PAGE 93
ST72321xx-Auto PWM auto-reload timer (ART) 12.3 ART registers 12.3.1 Control/status register (ARTCSR) ARTCSR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 EXCL CC[2:0] TCE FCRL OIE OVF RW RW RW RW RW RW Table 45. Bit 7 ARTCSR register description Name EXCL 6:4 CC[2:0] 3 2 1 0 Function External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler.
PAGE 94
PWM auto-reload timer (ART) Table 46. 12.3.2 ST72321xx-Auto Prescaler selection for ART (continued) fCOUNTER With fINPUT = 8 MHz CC2 CC1 CC0 fINPUT / 8 1 MHz 0 1 1 fINPUT / 16 500 kHz 1 0 0 fINPUT / 32 250 kHz 1 0 1 fINPUT / 64 125 kHz 1 1 0 fINPUT / 128 62.5 kHz 1 1 1 Counter access register (ARTCAR) ARTCAR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 CA[7:0] RW Table 47. Bit Name 7:0 12.3.
PAGE 95
ST72321xx-Auto PWM auto-reload timer (ART) Table 49. PWM frequency versus resolution fPWM ARTARR value 12.3.4 Resolution Min Max 0 8-bit ~0.244 kHz 31.25 kHz [ 0..127 ] > 7-bit ~0.244 kHz 62.5 kHz [ 128..191 ] > 6-bit ~0.488 kHz 125 kHz [ 192..223 ] > 5-bit ~0.977 kHz 250 kHz [ 224..239 ] > 4-bit ~1.953 kHz 500 kHz PWM control register (PWMCR) PWMCR Reset value: 0000 0000 (00h) 7 6 Table 50.
PAGE 96
PWM auto-reload timer (ART) 12.3.5 ST72321xx-Auto Duty cycle registers (PWMDCRx) PWMDCRx Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 DC[7:0] RW Table 52. PWMDCRx register description Bit Name 7:0 DC[7:0] Function Duty Cycle Data These bits are set and cleared by software. A PWMDCRx register is associated with the OCRx register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all channels and given by the ARTARR register).
PAGE 97
ST72321xx-Auto 12.3.7 PWM auto-reload timer (ART) Input capture registers (ARTICRx) ARTICRx Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 IC[7:0] RO Table 54. Bit 7:0 ARTICRx register description Name IC[7:0] Table 55. Function Input Capture Data These read only bits are set and cleared by hardware. An ARTICRx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event. PWM auto-reload timer register map and reset values Address (Hex.
PAGE 98
16-bit timer ST72321xx-Auto 13 16-bit timer 13.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.
PAGE 99
ST72321xx-Auto 16-bit timer 13.3 Functional description 13.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low.
PAGE 100
16-bit timer ST72321xx-Auto Figure 41.
PAGE 101
ST72321xx-Auto 16-bit timer 16-bit read sequence The 16-bit read sequence (from either the Counter Register or the Alternate Counter Register) is illustrated in Figure 42. Figure 42. 16-bit read sequence Beginning of the sequence At t0 Read MS Byte LS Byte is buffered Other instructions At t0 +Dt Read LS Byte Returns the buffered LS Byte value at t0 Sequence completed The user must read the MS Byte first; the LS Byte value is then buffered automatically.
PAGE 102
16-bit timer 13.3.2 ST72321xx-Auto External clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock.
PAGE 103
ST72321xx-Auto 13.3.3 16-bit timer Input capture In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see Figure 46). ICiR MS Byte LS Byte ICiHR ICiLR ICiR register is a read-only register.
PAGE 104
16-bit timer ST72321xx-Auto 5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. 6 Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. 7 This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1).
PAGE 105
ST72321xx-Auto 13.3.4 16-bit timer Output compare In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed.
PAGE 106
16-bit timer ST72321xx-Auto If the timer clock is an external clock, the formula is:  OCiR = t * fEXT Where: t = Output compare period (in seconds) fCPU = External timer clock frequency (in hertz) Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set 2.
PAGE 107
ST72321xx-Auto 16-bit timer Figure 48. Output compare block diagram 16-BIT FREE RUNNING COUNTER OC1E OC2E CC1 CC0 (Control Register 2) CR2 16-bit (Control Register 1) CR1 OUTPUT COMPARE CIRCUIT 16-bit OCIE FOLV2 FOLV1 OLVL2 OLVL1 16-bit Latch 1 Latch 2 OC1R Register OCF1 OCF2 OC2R Register 0 0 OCMP1 pin OCMP2 pin 0 (Status Register) SR Figure 49.
PAGE 108
16-bit timer 13.3.6 ST72321xx-Auto One Pulse mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure To use one pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (using the appropriate formula below according to the timer clock source used). 2.
PAGE 109
ST72321xx-Auto 16-bit timer The OC1R register value required for a specific timing application can be calculated using the following formula: t * fCPU - 5 OCiR value = PRESC Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 61: Timer clock selection) If the timer clock is an external clock the formula is: OCiR = t * fEXT - 5 Where: t = Pulse period (in seconds) fEXT = External clock frequenc
PAGE 110
16-bit timer ST72321xx-Auto Figure 53. Pulse width modulation mode timing example with 2 output compare functions 2ED0 2ED1 2ED2 COUNTER 34E2 FFFC FFFD FFFE OLVL2 OCMP1 compare2 OLVL1 compare1 34E2 FFFC OLVL2 compare2 Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1 Note: On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length. 13.3.
PAGE 111
ST72321xx-Auto 16-bit timer Figure 54. Pulse width modulation cycle flowchart When Counter = OC1R OCMP1 = OLVL1 When Counter = OC2R OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
PAGE 112
16-bit timer 13.4 ST72321xx-Auto Low power modes Table 56. Effect of low power modes on 16-bit timer Mode 13.5 Effect Wait No effect on 16-bit timer. Timer interrupts cause the device to exit from Wait mode. Halt 16-bit timer registers are frozen. In Halt mode, the counter stops counting until Halt mode is exited.
PAGE 113
ST72321xx-Auto 16-bit timer Table 58. Timer modes Timer resources Modes Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 Not recommended(1) One Pulse mode No Partially(2) No Not recommended(3) PWM mode No 1. See Note 4 in Section 13.3.6 One Pulse mode 2. See Note 5 in Section 13.3.6 One Pulse mode 3. See Note 4 in Section 13.3.7 Pulse width modulation mode 13.
PAGE 114
16-bit timer ST72321xx-Auto Table 59. Bit 13.7.2 CR1 register description (continued) Name Function 3 Forced Output Compare 1 This bit is set and cleared by software. FOLV1 0: No effect on the OCMP1 pin 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison 2 Output Level 2 This bit is copied to the OCMP2 pin whenever a successful comparison occurs with OLVL2 the OC2R register and OCxE is set in the CR2 register.
PAGE 115
ST72321xx-Auto 16-bit timer Table 60. Bit 5 4 CR2 register description (continued) Name Function OPM One Pulse Mode 0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register. PWM Pulse Width Modulation 0: PWM mode is not active.
PAGE 116
16-bit timer ST72321xx-Auto Table 62. Bit Name Function ICF1 Input Capture Flag 1 0: No input capture (reset value) 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. OCF1 Output Compare Flag 1 0: No match (reset value) 1: The content of the free running counter has matched the content of the OC1R register.
PAGE 117
ST72321xx-Auto 13.7.5 16-bit timer Input capture 1 low register (IC1LR) This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). IC1LR 7 Reset value: Undefined 6 5 4 3 2 1 MSB RO 13.7.6 0 LSB RO RO RO RO RO RO RO Output compare 1 high register (OC1HR) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
PAGE 118
16-bit timer 13.7.9 ST72321xx-Auto Output compare 2 low register (OC2LR) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OC2LR 7 Reset value: 0000 0000 (00h) 6 5 4 3 2 1 MSB RW 13.7.10 0 LSB RW RW RW RW RW RW RW Counter high register (CHR) This is an 8-bit register that contains the high part of the counter value. CHR Reset value: 1111 1111 (FFh) 7 6 5 4 3 2 1 MSB RO 13.7.
PAGE 119
ST72321xx-Auto 13.7.13 16-bit timer Alternate counter low register (ACLR) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register. ACLR 7 Reset value: 1111 1100 (FCh) 6 5 4 3 2 1 MSB RO 13.7.
PAGE 120
16-bit timer ST72321xx-Auto Table 63. Address (Hex.
PAGE 121
ST72321xx-Auto Serial peripheral interface (SPI) 14 Serial peripheral interface (SPI) 14.1 Introduction The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface cannot be a master in a multimaster system. 14.
PAGE 122
Serial peripheral interface (SPI) ST72321xx-Auto Figure 55. Serial peripheral interface block diagram Data/Address Bus SPIDR Read Interrupt request Read Buffer MOSI MISO SPICSR 0 7 8-bit Shift Register SPIF WCOL OVR MODF SOD bit 0 SOD SSM SSI Write SS SPI STATE CONTROL SCK 0 SPICR 7 SPIE 1 SPE 0 SPR2 MSTR CPOL CPHA SPR1 SPR0 MASTER CONTROL SERIAL CLOCK GENERATOR SS 14.3.
PAGE 123
ST72321xx-Auto Serial peripheral interface (SPI) Figure 56. Single master/single slave application SLAVE MASTER MSBit LSBit 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR MSBit MISO MISO MOSI MOSI SCK SCK SS +5V LSBit 8-BIT SHIFT REGISTER SS Not used if SS is managed by software 14.3.2 Slave select management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software.
PAGE 124
Serial peripheral interface (SPI) ST72321xx-Auto Figure 57. Generic SS timing diagram MOSI/MISO Byte 1 Byte 2 Byte 3 Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1) Figure 58. Hardware/Software slave select management SSM bit SSI bit SS external pin 14.3.3 1 SS internal 0 Master mode operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register).
PAGE 125
ST72321xx-Auto 14.3.4 Serial peripheral interface (SPI) Master mode transmit sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared.
PAGE 126
Serial peripheral interface (SPI) ST72321xx-Auto The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Overrun condition (OVR) on page 128). 14.4 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (see Figure 59).
PAGE 127
ST72321xx-Auto Serial peripheral interface (SPI) Figure 59.
PAGE 128
Serial peripheral interface (SPI) ST72321xx-Auto 14.5 Error flags 14.5.1 Master mode fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: ● The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. ● The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. ● The MSTR bit is reset, thus forcing the device into slave mode.
PAGE 129
ST72321xx-Auto Serial peripheral interface (SPI) Figure 60. Clearing the WCOL bit (Write Collision Flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step 2nd Step Read SPICSR Read SPIDR RESULT SPIF = 0 WCOL = 0 Clearing sequence before SPIF = 1 (during a data byte transfer) Read SPICSR 1st Step RESULT 2nd Step 14.5.4 Read SPIDR WCOL = 0 Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit.
PAGE 130
Serial peripheral interface (SPI) 14.6 ST72321xx-Auto Low power modes Table 64. Effect of low power modes on SPI Mode 14.6.1 Effect Wait No effect on SPI. SPI interrupt events cause the device to exit from Wait mode. Halt SPI registers are frozen. In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from Halt mode” capability.
PAGE 131
ST72321xx-Auto Serial peripheral interface (SPI) 14.8 SPI registers 14.8.1 Control register (SPICR) SPICR Reset value: 0000 xxxx (0xh) 7 6 5 4 3 2 SPIE SPE SPR2 MSTR CPOL CPHA SPR[1:0] RW RW RW RW RW RW RW Table 66. Bit 7 6 5 4 3 2 1 0 SPICR register description Name Function SPIE Serial Peripheral Interrupt Enable This bit is set and cleared by software.
PAGE 132
Serial peripheral interface (SPI) Table 66. Bit 1:0 SPICR register description (continued) Name Function Serial Clock Frequency These bits are set and cleared by software. Used with the SPR2 bit, they select SPR[1:0] the baud rate of the SPI serial clock SCK output by the SPI in master mode. Note: These 2 bits have no effect in slave mode. Table 67. 14.8.
PAGE 133
ST72321xx-Auto Serial peripheral interface (SPI) Table 68. Bit 4 Name Function Mode Fault flag This bit is set by hardware when the SS pin is pulled low in master mode (see Master mode fault (MODF) on page 128). An SPI interrupt can be generated if SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An MODF access to the SPICR register while MODF = 1 followed by a write to the SPICR register).
PAGE 134
Serial peripheral interface (SPI) Warning: ST72321xx-Auto A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Figure 55). Table 69. 134/243 SPI register map and reset values Address (Hex.
PAGE 135
ST72321xx-Auto Serial communications interface (SCI) 15 Serial communications interface (SCI) 15.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 15.
PAGE 136
Serial communications interface (SCI) 15.3 ST72321xx-Auto General description The interface is externally connected to another device by two pins (see Figure 63): ● TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level. ● RDI: Receive Data Input is the serial data input.
PAGE 137
ST72321xx-Auto Serial communications interface (SCI) Figure 62.
PAGE 138
Serial communications interface (SCI) 15.4 ST72321xx-Auto Functional description The block diagram of the Serial Control Interface, is shown in Figure 62. It contains six dedicated registers: ● 2 control registers (SCICR1 and SCICR2) ● a status register (SCISR) ● a baud rate register (SCIBRR) ● an extended prescaler receiver register (SCIERPR) ● an extended prescaler transmitter register (SCIETPR) Refer to the register descriptions in Section 15.7 for the definitions of each bit. 15.4.
PAGE 139
ST72321xx-Auto 15.4.2 Serial communications interface (SCI) Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. Character transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin.
PAGE 140
Serial communications interface (SCI) ST72321xx-Auto bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost.
PAGE 141
ST72321xx-Auto Serial communications interface (SCI) When an overrun error occurs: ● The OR bit is set. ● The RDR content is not lost. ● The shift register is overwritten. ● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation. Noise error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.
PAGE 142
Serial communications interface (SCI) ST72321xx-Auto Figure 64.
PAGE 143
ST72321xx-Auto Serial communications interface (SCI) Conventional baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: fCPU fCPU Rx = Tx = (16*PR)*RR (16*PR)*TR with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register.
PAGE 144
Serial communications interface (SCI) ST72321xx-Auto A receiver wakes up by Idle Line detection when the Receive line has recognized an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes up by Address Mark detection when it received a ‘1’ as the most significant bit of a word, thus indicating that the message is an address.
PAGE 145
ST72321xx-Auto Serial communications interface (SCI) Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%.
PAGE 146
Serial communications interface (SCI) ST72321xx-Auto Figure 65. Bit sampling in reception mode RDI LINE sampled values Sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6/16 7/16 7/16 One bit time 15.5 Low power modes Table 71. Effect of low power modes on SCI Mode 15.6 Effect Wait No effect on SCI. SCI interrupts cause the device to exit from Wait mode. Halt SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
PAGE 147
ST72321xx-Auto Serial communications interface (SCI) Table 72. SCI interrupt control/wake-up capability Interrupt event Idle Line Detected Parity Error 15.7 SCI registers 15.7.1 Status register (SCISR) Event flag Enable control bit Exit from Wait Exit from Halt IDLE ILIE Yes No PE PIE Yes No SCISR Reset value: 1100 0000 (C0h) 7 6 5 4 3 2 1 0 TDRE TC RDRF IDLE OR NF FE PE RO RO RO RO RO RO RO RO Table 73.
PAGE 148
Serial communications interface (SCI) Table 73. Bit 4 3 2 1 0 148/243 ST72321xx-Auto SCISR register description (continued) Name Function IDLE Idle line detect This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).
PAGE 149
ST72321xx-Auto 15.7.2 Serial communications interface (SCI) Control register 1 (SCICR1) SCICR1 Reset value: X000 0000 (x0h) 7 6 5 4 3 2 1 0 R8 T8 SCID M WAKE PCE PS PIE RW RW RW RW RW RW RW RW Table 74. SCICR1 register description Bit Name 7 R8 Receive data bit 8 This bit is used to store the 9th bit of the received word when M = 1. 6 T8 Transmit data bit 8 This bit is used to store the 9th bit of the transmitted word when M = 1.
PAGE 150
Serial communications interface (SCI) Table 74. Bit SCICR1 register description (continued) Name Function PIE Parity interrupt enable This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled 0 15.7.
PAGE 151
ST72321xx-Auto Serial communications interface (SCI) Table 75. SCICR2 register description (continued) Bit Name 2 15.7.4 RE Function Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit 1 Receiver wake-up This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized.
PAGE 152
Serial communications interface (SCI) Table 76. Bit ST72321xx-Auto SCIBRR register description Name Function First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges.
PAGE 153
ST72321xx-Auto Serial communications interface (SCI) Table 77. Bit SCIERPR register description Name Function 8-bit Extended Receive Prescaler Register The extended baud rate generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider 7:0 ERPR[7:0] (see Figure 64) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset. 15.7.
PAGE 154
Serial communications interface (SCI) Table 80. ST72321xx-Auto SCI register map and reset values Address (Hex.
PAGE 155
ST72321xx-Auto I2C bus interface (I2C) 16 I2C bus interface (I2C) 16.1 Introduction The I2C bus interface serves as an interface between the microcontroller and the serial I2C bus. It provides both multimaster and slave functions, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports fast I2C mode (400 kHz). 16.2 16.2.1 16.2.2 Main features ● Parallel-bus/I2C protocol converter ● Multimaster capability ● 7-bit/10-bit addressing ● SMBus V1.
PAGE 156
I2C bus interface (I2C) 16.3 ST72321xx-Auto General description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a fast I2C bus. This selection is made by software. 16.3.
PAGE 157
ST72321xx-Auto 16.3.3 I2C bus interface (I2C) SDA/SCL line control Transmitter mode The interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register. Receiver mode The interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. The SCL frequency (fSCL) is controlled by a programmable clock divider which depends on the I2C bus mode.
PAGE 158
I2C bus interface (I2C) 16.4 ST72321xx-Auto Functional description Refer to the CR, SR1 and SR2 registers in Section 16.7 for the bit definitions. By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2 register. 16.4.
PAGE 159
ST72321xx-Auto I2C bus interface (I2C) Closing slave communication After the last data byte is transferred, a Stop Condition is generated by the master. The interface detects this condition and sets: ● EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 register (see Figure 68: Transfer sequencing EV4). Error cases Note: ● BERR: Detection of a Stop or a Start condition during a byte transfer.
PAGE 160
I2C bus interface (I2C) ST72321xx-Auto Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. ● In 7-bit addressing mode, one address byte is sent. ● In 10-bit addressing mode, sending the first byte including the header sequence causes the following event: – The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
PAGE 161
ST72321xx-Auto I2C bus interface (I2C) Error cases ● Note: BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if ITE is set.
PAGE 162
I2C bus interface (I2C) ST72321xx-Auto Figure 68. Transfer sequencing 7-bit Slave receiver: S Address A Data1 A Data2 EV1 A EV2 EV2 DataN ..... A P EV2 EV4 7-bit Slave transmitter: S Address A Data1 A Data2 EV1 EV3 A EV3 ..... EV3 DataN NA P EV3-1 EV4 7-bit Master receiver: S Address A EV5 Data1 A Data2 EV6 A EV7 ..... EV7 DataN NA P EV7 7-bit Master transmitter: S Address A EV5 Data1 A EV6 EV8 Data2 A EV8 EV8 DataN .....
PAGE 163
ST72321xx-Auto 16.5 I2C bus interface (I2C) Low power modes Effect of low power modes on I2C Table 81. Mode Effect 2 16.6 Wait No effect on I C interface. I2C interrupts cause the device to exit from Wait mode. Halt I2C registers are frozen. In Halt mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt mode” capability. Interrupts Figure 69.
PAGE 164
I2C bus interface (I2C) ST72321xx-Auto 16.7 Register description 16.7.1 I2C control register (CR) CR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 0 Reserved PE ENGC START ACK STOP ITE - RW RW RW RW RW RW Table 83. Bit Name 7:6 - 5 164/243 PE CR register description Function Reserved. Forced to 0 by hardware. Peripheral enable This bit is set and cleared by software.
PAGE 165
ST72321xx-Auto I2C bus interface (I2C) Table 83. Bit 1 Name Function STOP Generation of a Stop condition This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE = 0). In Master mode 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent.
PAGE 166
I2C bus interface (I2C) Table 84. Bit SR1 register description (continued) Function 6 10-bit addressing in Master mode This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR ADD10 register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE = 0). 0: No ADD10 event occurred.
PAGE 167
ST72321xx-Auto I2C bus interface (I2C) Table 84. Bit 1 0 16.7.3 SR1 register description (continued) Name Function M/SL Master/Slave This bit is set by hardware as soon as the interface is in Master mode (writing START = 1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO = 1). It is also cleared when the interface is disabled (PE = 0).
PAGE 168
I2C bus interface (I2C) Table 85. Bit 16.7.4 ST72321xx-Auto SR2 register description (continued) Name Function 2 Arbitration lost This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE = 1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE = 0). After an ARLO event the interface switches back automatically to Slave mode (M/SL = 0). The SCL line is not held low while ARLO = 1.
PAGE 169
ST72321xx-Auto I2C bus interface (I2C) Table 86. Bit CCR register description (continued) Name Function 7-bit clock divider These bits select the speed of the bus (fSCL) depending on the I2C mode. They are 6:0 CC[6:0] not cleared when the interface is disabled (PE = 0). Refer to Section 19: Electrical characteristics for the table of values. Note: The programmed fSCL assumes no load on SCL and SDA lines. 16.7.
PAGE 170
I2C bus interface (I2C) Table 88. ST72321xx-Auto OAR1 register description Function Bit Name 7-bit addressing mode 10-bit addressing mode Interface address These bits define the I2C bus address 7:1 ADD[7:1] of the interface. They are not cleared when the interface is disabled (PE = 0). 0 ADD0 7:0 ADD[7:0] 16.7.7 Not applicable Address direction bit This bit is ‘don’t care’, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE = 0).
PAGE 171
ST72321xx-Auto Table 90. Address (Hex.
PAGE 172
10-bit A/D converter (ADC) ST72321xx-Auto 17 10-bit A/D converter (ADC) 17.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 10-bit data register.
PAGE 173
ST72321xx-Auto 17.3 10-bit A/D converter (ADC) Functional description The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than VAREF (high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication).
PAGE 174
10-bit A/D converter (ADC) 17.3.3 ST72321xx-Auto Changing the conversion channel The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel. 17.4 Low power modes Note: The A/D converter may be disabled by resetting the ADON bit.
PAGE 175
ST72321xx-Auto 10-bit A/D converter (ADC) Table 92. Bit ADCCSR register description (continued) Name Function A/D Converter on This bit is set and cleared by software. ADON 0: Disable ADC and stop conversion 1: Enable ADC and start conversion 5 4 - Reserved. Must be kept cleared Channel Selection These bits are set and cleared by software. They select the analog input to convert.
PAGE 176
10-bit A/D converter (ADC) 17.6.3 ST72321xx-Auto Data register (ADCDRL) ADCDRL Reset value: 0000 0000 (00h) 7 6 Table 94. 17.6.4 4 3 2 1 0 Reserved D[1:0] - RO ADCDRL register description Bit Name 7:2 - 1:0 D[1:0] Function Reserved. Forced by hardware to 0. LSB of Converted Analog Value ADC register map and reset values Table 95. Address (Hex.
PAGE 177
ST72321xx-Auto Instruction set 18 Instruction set 18.1 CPU addressing modes The CPU features 17 different addressing modes which can be classified in seven main groups as listed in the following table: Table 96.
PAGE 178
Instruction set Table 97. ST72321xx-Auto CPU addressing mode overview (continued) Syntax Destination Pointer address (Hex.) Pointer size (Hex.) Length (bytes) ld A,([$10.w],X) 0000..FFFF 00..FF word +2 Mode 18.1.1 Long Indirect Indexed Relative Direct jrne loop PC+/-127 Relative Indirect jrne [$10] PC+/-127 Bit Direct bset $10,#7 00..FF Bit Indirect bset [$10],#7 00..FF Bit Direct Relative btjt $10,#7,skip 00..FF Bit Indirect Relative btjt [$10],#7,skip 00..FF +1 00.
PAGE 179
ST72321xx-Auto 18.1.2 Instruction set Immediate Immediate instructions have 2 bytes. The first byte contains the opcode and the second byte contains the operand value. Table 99. Immediate instructions Instruction 18.1.3 Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations Direct In Direct instructions, the operands are referenced by their memory address.
PAGE 180
Instruction set 18.1.5 ST72321xx-Auto Indirect (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode.
PAGE 181
ST72321xx-Auto Instruction set Table 100. Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes (continued) Type Instruction Short instructions only Function CLR Clear INC, DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement BSET, BRES Bit Operations BTJT, BTJF Bit Test and Jump Operations SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations 18.1.
PAGE 182
Instruction set ST72321xx-Auto Table 102. Instruction groups (continued) Group Instructions Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP Conditional Branch JRxx Interruption management TRAP WFI HALT IRET SIM RIM SCF RCF Condition Code Flag modification 18.
PAGE 183
ST72321xx-Auto Instruction set Table 103. Instruction set overview Mnemo Description Function/Example Dst Src I1 H I0 N Z C ADC Add with Carry A=A+M+C A M H N Z C ADD Addition A=A+M A M H N Z C AND Logical And A=A.M A M N Z BCP Bit compare A, Memory tst (A .
PAGE 184
Instruction set ST72321xx-Auto Table 103.
PAGE 185
ST72321xx-Auto Electrical characteristics 19 Electrical characteristics 19.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 19.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25°C and TA = TAmax (given by the selected temperature range).
PAGE 186
Electrical characteristics 19.2 ST72321xx-Auto Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 19.2.1 Voltage characteristics Table 104. Voltage characteristics Symbol Ratings Maximum value VDD - VSS Supply voltage 6.
PAGE 187
ST72321xx-Auto 19.2.2 Electrical characteristics Current characteristics Table 105.
PAGE 188
Electrical characteristics ST72321xx-Auto 19.3 Operating conditions 19.3.1 General operating conditions Table 107. General operating conditions Symbol fCPU VDD Parameter Conditions Internal clock frequency Standard voltage range (except Flash Write/Erase) Operating voltage for Flash Write/Erase Min Max Unit 0 8 MHz 3.8 5.5 V VPP = 11.4 to 12.6V 4.5 A suffix version TA Ambient temperature range B suffix version C suffix version Note: 5.
PAGE 189
ST72321xx-Auto 19.3.2 Electrical characteristics Operating conditions with low voltage detector (LVD) Subject to general operating conditions for VDD, fCPU, and TA. Table 108. Operating conditions with low voltage detector (LVD) Symbol Parameter Conditions VD level = High in option byte Reset release threshold VIT+(LVD) (VDD rise) Reset generation threshold (VDD fall) Max 4.0(1) Unit 4.2 4.5 VD level = Med. in option byte 3.55 3.75 4.0(1) VD level = Low in option byte(2) 2.95(1) 3.15 3.
PAGE 190
Electrical characteristics 19.3.4 ST72321xx-Auto External voltage detector (EVD) thresholds Subject to general operating conditions for VDD, fCPU, and TA. Table 110. External voltage detector (EVD) thresholds Symbol Parameter Conditions VIT+(EVD) 10 AVDF flag toggle threshold (VDD rise(1) VIT-(EVD) 01 AVDF flag toggle threshold (VDD fall) (1) Vhys(EVD) EVD voltage threshold hysteresis Typ Max 1.15 1.26 1.35 1.1 1.2 1.3 Unit V VIT+(EVD)-VIT-(EVD) 1.
PAGE 191
ST72321xx-Auto 19.4 Electrical characteristics Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current values must be added (except for Halt mode, for which the clock is stopped). 19.4.1 Current consumption Table 111.
PAGE 192
Electrical characteristics ST72321xx-Auto Power consumption vs fCPU: Flash devices Figure 74. Typical IDD in Run mode 8MHz 4MHz 2MHz 1MHz 9 8 7 Idd (mA) 6 5 4 3 2 1 0 3.2 3.6 4 4.4 4.8 5.2 5.5 4.8 5.2 5.5 4.8 5.2 5.5 Vdd (V) Figure 75. Typical IDD in Slow mode 1.20 500kHz 250kHz 1.00 125kHz 62.5kHz Idd (mA) 0.80 0.60 0.40 0.20 0.00 3.2 3.6 4 4.4 Vdd (V) Figure 76. Typical IDD in Wait mode 8MHz 4MHz 2MHz 1MHz 6 5 Idd (mA) 4 3 2 1 0 3.2 3.6 4 4.
PAGE 193
ST72321xx-Auto Electrical characteristics Figure 77. Typical IDD in Slow Wait mode 500kHz 1.20 250kHz 125kHz 62.5kHz 1.00 Idd (mA) 0.80 0.60 0.40 0.20 0.00 3.2 3.6 4 4.4 4.8 5.2 5.5 Vdd (V) 19.4.2 Supply and clock managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current values must be added (except for Halt mode).
PAGE 194
Electrical characteristics 19.4.3 ST72321xx-Auto On-chip peripherals Measured on LQFP64 generic board TA = 25°C, fCPU = 4 MHz. Table 113. On-chip peripherals current consumption Symbol IDD(TIM) IDD(ART) Parameter 16-bit timer supply current(1) ART PWM supply current Typ Unit VDD  5.0V 50 µA VDD  5.0V 75 µA VDD  5.0V 400 µA VDD  5.0V 175 µA VDD  5.
PAGE 195
ST72321xx-Auto 19.5 Electrical characteristics Clock and timing characteristics Subject to general operating conditions for VDD, fCPU, and TA. 19.5.1 General timings Table 114. General timings Symbol Parameter tc(INST) Instruction cycle time tv(IT) Conditions fCPU = 8 MHz Interrupt reaction time(2) tv(IT) = tc(INST) + 10 fCPU = 8 MHz Min Typ(1) Max Unit 2 3 12 tCPU 250 375 1500 ns 10 22 tCPU 1.25 2.75 µs 1. Data based on typical application software. 2.
PAGE 196
Electrical characteristics 19.5.3 ST72321xx-Auto Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time.
PAGE 197
ST72321xx-Auto Electrical characteristics Table 117. OSCRANGE selection for typical resonators Typical ceramic resonators(1) Supplier Murata fOSC (MHz) Reference Recommended OSCRANGE option bit configuration 2 CSTCC2M00G56A-R0 MP mode(2) 4 CSTCR4M00G55B-R0 MS mode 8 CSTCE8M00G55A-R0 16 CSTCE16M0G53A-R0 HS mode 1. Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators, please consult www.murata.com. 2.
PAGE 198
Electrical characteristics 19.5.5 ST72321xx-Auto PLL characteristics Table 119. PLL characteristics Symbol Parameter Conditions fOSC PLL input frequency range  fCPU/fCPU Instantaneous PLL jitter(1) Min Typ 2 Max Unit 4 MHz fOSC = 4 MHz 1.0 2.5 fOSC = 2 MHz 2.5 4.0 % 1. Data based on characterization results The user must take the PLL jitter into account in the application (for example, in serial communication or sampling of high frequency signals).
PAGE 199
ST72321xx-Auto Electrical characteristics 19.6 Memory characteristics 19.6.1 RAM and hardware registers Table 120. RAM supply voltage Symbol VRM Parameter Conditions (1) Data retention mode Halt mode (or RESET) Min Typ Max Unit 1.6 V 1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under RESET) or in hardware registers (only in Halt mode). Not tested in production. 19.6.2 Flash memory Table 121.
PAGE 200
Electrical characteristics 19.7 ST72321xx-Auto EMC (electromagnetic compatibility) characteristics Susceptibilitytests are performed on a sample basis during product characterization. 19.7.1 Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling two LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
PAGE 201
ST72321xx-Auto Electrical characteristics . Table 122. EMS test results Symbol VFESD VFFTB 19.7.
PAGE 202
Electrical characteristics 19.7.3 ST72321xx-Auto Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.
PAGE 203
ST72321xx-Auto Electrical characteristics 19.8 I/O port pin characteristics 19.8.1 General characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Table 126.
PAGE 204
Electrical characteristics ST72321xx-Auto Figure 82. Unused I/O pins configured as input Figure 83. Typical IPU vs VDD with VIN = VSS 90 VDD Ta=1 40°C 80 ST7XXX Ta=9 5°C 70 10k 60 UNUSED I/O PORT 50 Ipu(uA) UNUSED I/O PORT 10k Ta=2 5°C Ta=-45 °C 40 30 ST7XXX 20 Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC robustness and lower cost. 19.8.2 10 0 2 2.5 3 3.5 4 4.5 Vdd(V) 5 5.
PAGE 205
ST72321xx-Auto Electrical characteristics Figure 84. Typical VOL at VDD = 5V (standard) Figure 85. Typical VOL at VDD = 5V (high-sink) 1 1.4 0.9 0.8 1 V ol(V ) at Vdd=5V V ol (V ) at Vdd=5V 1.2 0.8 0.6 Ta =14 0°C " 0.4 Ta =95 °C Ta =25 °C 0.2 Ta =-45 °C 0.7 0.6 0.5 0.4 Ta= 140 °C 0.3 Ta= 95 °C 0.2 Ta= 25 °C 0.1 Ta= -45°C 0 0 0 0.005 0.01 0.015 0 0.01 0.02 0.03 Iio(A) Iio(A) Figure 86. Typical VOH at VDD = 5V 5.5 Vdd-V oh (V ) at Vdd=5V 5 4.5 4 3.
PAGE 206
Electrical characteristics ST72321xx-Auto Figure 87. Typical VOL versus VDD (standard) 1 0.45 Ta= -4 5°C 0.9 Ta= 95°C Ta=2 5°C Ta=9 5°C 0.35 Ta= 140 °C 0.7 Vol(V) at Iio=2mA V ol(V ) at Iio=5m A 0.8 Ta=-4 5°C 0.4 Ta= 25°C 0.6 0.5 0.4 0.3 Ta=1 40°C 0.3 0.25 0.2 0.15 0.2 0.1 0.1 0.05 0 2 2.5 3 3.5 4 4.5 5 5.5 0 6 2 Vdd(V ) 2.5 3 3.5 4 4.5 5 5.5 6 Vdd(V) Figure 88. Typical VOL versus VDD (high-sink) 1 .6 0 .6 Ta = 140 °C 1 .4 0 .5 Ta =95 °C 1 .
PAGE 207
ST72321xx-Auto Electrical characteristics 19.9 Control pin characteristics 19.9.1 Asynchronous RESET pin Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Table 128. Asynchronous RESET pin characteristics Symbol Parameter Conditions Typ Max Unit 0.16xVD VIL Input low level voltage(1) VIH Input high level voltage(1) Vhys Schmitt trigger voltage hysteresis(2) VOL Output low level voltage(3) IIO Input current on RESET pin RON Min D 0.
PAGE 208
Electrical characteristics ST72321xx-Auto Figure 90. RESET pin protection when LVD is enabled VDD Required Optional (note 3) EXTERNAL RESET 1 RON INTERNAL RESET Filter 0.01µF Note: ST72XXX 1M PULSE GENERATOR WATCHDOG LVD RESET The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
PAGE 209
ST72321xx-Auto Electrical characteristics Figure 91. RESET pin protection when LVD is disabled VDD ST72XXX RON USER EXTERNAL RESET CIRCUIT INTERNAL RESET Filter 0.01µF PULSE GENERATOR WATCHDOG Required Note: The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
PAGE 210
Electrical characteristics ST72321xx-Auto Figure 92. Two typical applications with ICCSEL/VPP pin(1) ICCSEL/VPP VPP PROGRAMMING TOOL 10k ST72XXX ST72XXX 1. When ICC mode is not required by the application, the ICCSEL/VPP pin must be tied to VSS. 19.10 Timer peripheral characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to Section 19.
PAGE 211
ST72321xx-Auto Electrical characteristics 19.11 Communication interface characteristics 19.11.1 SPI (serial peripheral interface) Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Refer to Section 19.8: I/O port pin characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Table 132.
PAGE 212
Electrical characteristics ST72321xx-Auto Figure 93. SPI slave timing diagram with CPHA = 0(1) SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) MISO OUTPUT tv(SO) MSB OUT See note 2 tsu(SI) th(SO) BIT6 OUT See note 2 LSB OUT th(SI) MSB IN MOSI INPUT tdis(SO) tr(SCK) tf(SCK) LSB IN BIT1 IN 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2.
PAGE 213
ST72321xx-Auto Electrical characteristics Figure 95. SPI master timing diagram(1) SS INPUT tc(SCK) SCK INPUT CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 CPHA = 1 CPOL = 0 CPHA = 1 CPOL = 1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tr(SCK) tf(SCK) th(MI) MSB IN BIT6 IN tv(MO) MOSI OUTPUT See note 2 MSB OUT LSB IN th(MO) BIT6 OUT LSB OUT See note 2 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2.
PAGE 214
Electrical characteristics 19.11.2 ST72321xx-Auto I2C - inter IC control interface Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Refer to Section 19.8: I/O port pin characteristics for more details on the input/output alternate function characteristics (SDAI and SCLI). The ST7 I2C interface meets the requirements of the standard I2C communication protocol described in the following table. Table 133.
PAGE 215
ST72321xx-Auto Electrical characteristics Figure 96. Typical application with I2C BUS and timing diagram(1) VDD VDD 4.7k 4.7k I2C BUS 100 SDAI 100 SCLI ST72XXX REPEATED START START tsu(STA) tw(STO:STA) START SDA tf(SDA) tr(SDA) tsu(SDA) STOP th(SDA) SCK th(STA) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tsu(STO) 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
PAGE 216
Electrical characteristics 19.12 ST72321xx-Auto 10-bit ADC characteristics Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Table 135. 10-bit ADC characteristics Symbol fADC VAREF VAIN Parameter Conditions ADC clock frequency Analog reference voltage 0.7*VDD < VAREF < VDD Conversion voltage range(1) Ilkg Positive input leakage current for analog input Ilkg Negative input leakage current on robust analog pins(2) Min Typ Max Unit 0.4 2 MHz 3.
PAGE 217
ST72321xx-Auto Electrical characteristics Figure 97. RAIN maximum versus fADC with CAIN = 0pF(1) Figure 98. Recommended CAIN and RAIN values(1) 45 1000 Cain 10 nF 2 MHz 35 Cain 22 nF 100 30 1 MHz 25 20 15 10 Max. R AIN (Kohm) Max. R AIN (Kohm) 40 Cain 47 nF 10 1 5 0 0.1 0 10 30 70 0.01 0.1 CPARASITIC (pF) 1 10 fAIN(KHz) 1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3pF).
PAGE 218
Electrical characteristics 19.12.2 ST72321xx-Auto General PCB design guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. ● Use separate digital and analog planes. The analog ground plane should be connected to the digital ground plane via a single point on the PCB. ● Filter power to the analog power planes.
PAGE 219
ST72321xx-Auto 19.12.3 Electrical characteristics ADC accuracy Conditions: VDD = 5V(1) Table 136. ADC accuracy Parameter(1) Symbol Conditions Typ Max(2) |ET| Total unadjusted error 3 4 |EO| Offset error 2 3 |EG| Gain error 0.5 3 |ED| Differential linearity error 1 2 |EL| Integral linearity error CPU in run mode @ fADC 2 MHz Unit LSB 1.
PAGE 220
Package characteristics 20 ST72321xx-Auto Package characteristics Figure 102. 64-pin (14x14) low profile quad flat package outline A A2 D D1 A1 b e E1 E L L1 c  Table 137. 64-pin (14x14) low profile quad flat package mechanical data mm inches Dimension Min Typ A Min Typ 1.600 A1 0.050 A2 1.350 b 0.300 c 0.090 Max 0.0630 0.150 0.0020 0.0059 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.0146 0.0177 0.200 0.0035 0.0079 D 16.000 0.6299 D1 14.000 0.
PAGE 221
ST72321xx-Auto Package characteristics Figure 103. 64-pin (10x10) low profile quad flat package outline D D1 A A2 A1 b E1 E e L c L1  Table 138. 64-pin (10x10) low profile quad flat package mechanical data mm inches Dimension Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 Max 0.0630 0.150 0.0020 0.0059 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 0.0079 D 12.000 0.4724 D1 10.000 0.3937 E 12.000 0.
PAGE 222
Package characteristics 20.1 ST72321xx-Auto Thermal characteristics Table 139. Thermal characteristics Symbol RthJA PD TJmax Ratings Value Unit Package thermal resistance (junction to ambient) LQFP64 14x14 LQFP64 10x10 LQFP44 10x10 47 50 52 °C/W Power dissipation(1) 500 mW Maximum junction temperature(2) 150 °C 1. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.
PAGE 223
ST72321xx-Auto 21 Device configuration and ordering information Device configuration and ordering information Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (ROM/FASTROM). ST72321-Auto devices are ROM versions, ST72P321-Auto devices are Factory Advanced Service Technique ROM (FASTROM) versions: They are factory-programmed HDFlash devices.
PAGE 224
Device configuration and ordering information ST72321xx-Auto Table 141. Option byte 0 bit description Bit OPT7 WDG HALT OPT6 WDG SW OPT5 - OPT4:3 VD[1:0] OPT2 - OPT1 PKG0 OPT0 224/243 Name FMP_R Function Watchdog and Halt mode This option bit determines if a RESET is generated when entering Halt mode while the Watchdog is active.
PAGE 225
ST72321xx-Auto Device configuration and ordering information Table 142. Option byte 1 bit description Bit Name Function OPT7 PKG1 Package selection bit 1 This option bit, with the PKG0 bit, selects the package (see Table 143: Package selection (OPT7)). RSTC RESET clock cycle selection This option bit selects the number of CPU cycles applied during the RESET phase and when exiting Halt mode. For resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time.
PAGE 226
Device configuration and ordering information 21.1.2 ST72321xx-Auto Flash ordering information The following Figure 105 serves as a guide for ordering. Figure 105.
PAGE 227
ST72321xx-Auto 21.2 Device configuration and ordering information ROM device ordering information and transfer of customer code Customer code is made up of the ROM/FASTROM contents and the list of the selected options (if any). The ROM/FASTROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh.
PAGE 228
Device configuration and ordering information ST72321xx-Auto Figure 106. ST72P321xxx-Auto FastROM commercial product structure Example: ST72 P 321 T Product class ST72 microcontroller Family type P = FastROM Sub-family type 321= 321 sub-family Package type T = LQFP Temperature range A = -40 °C to 85 °C C = -40 °C to 125 °C Code name Defined by STMicroelectronics. Denotes ROM code, pinout and program memory size.
PAGE 229
ST72321xx-Auto Device configuration and ordering information Figure 107. ST72321xxx-Auto ROM commercial product structure Example: ST72 321 T A /xxx X S Product class ST72 microcontroller 321 = 321sub-family Package type T = LQFP Temperature range A = -40 °C to 85 °C C = -40 °C to 125 °C Code name Defined by STMicroelectronics. Denotes ROM code, pinout and program memory size.
PAGE 230
Device configuration and ordering information ST72321xx-Auto ST72321-Auto Microcontroller FASTROM/ROM Option List (Last update August 2007) Customer: Address: ................................. ................................. ................................. Contact: ................................. Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference/ROM Code* : . . . . . . . . . . . . . . . . . . . . . . . . *The ROM code name is assigned by STMicroelectronics.
PAGE 231
ST72321xx-Auto 21.3 Development tools 21.3.1 Introduction Device configuration and ordering information Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 21.3.
PAGE 232
Device configuration and ordering information ST72321xx-Auto Table 144. STMicroelectronics development tools Emulation Supported products ST7 DVP3 series Emulator ST72521M, ST72F521M Programming ST7 EMU3 series Connection kit ICC socket board Emulator Active probe and T.E.B.
PAGE 233
ST72321xx-Auto 21.4 Device configuration and ordering information ST7 application notes All relevant ST7 application notes can be found on www.st.com.
PAGE 234
Known limitations ST72321xx-Auto 22 Known limitations 22.1 All Flash and ROM devices 22.1.1 External RC option The external RC clock source option described in previous datasheet revisions is no longer supported and has been removed from this specification. 22.1.
PAGE 235
ST72321xx-Auto Known limitations To avoid this, a semaphore is set to ‘1’ before checking the level change. The semaphore is changed to level '0' inside the interrupt routine. When a level change is detected, the semaphore status is checked. If it is ‘1’, it means that the last interrupt has been missed. In this case, the interrupt routine is invoked with the call instruction. There is another possible case, that is, if PxOR or PxDDR are written to with global interrupts disabled (interrupt mask bit set).
PAGE 236
Known limitations ST72321xx-Auto ; check the semaphore status if edge is detected CP A,#01 jrne OUT call call_routine ; call the interrupt routine OUT:LD A,#00 LD sema,A .call_routine ; entry to call_routine PUSH A PUSH X PUSH CC .
PAGE 237
ST72321xx-Auto Known limitations ; check for falling edge cp A,#$02 jrne OUT TNZ Y jrne OUT LD A,#$01 LD sema,A ; set the semaphore to '1' if edge is detected RIM ; reset the interrupt mask LD A,sema ; check the semaphore status CP A,#$01 jrne OUT call call_routine ; call the interrupt routine RIM OUT: RIM JP while_loop .call_routine ; entry to call_routine PUSH A PUSH X PUSH CC .
PAGE 238
Known limitations 22.1.6 ST72321xx-Auto Clearing active interrupts outside interrupt routine When an active interrupt request occurs at the same time as the related flag is being cleared, an unwanted reset may occur. Note: Clearing the related interrupt mask will not generate an unwanted reset.
PAGE 239
ST72321xx-Auto 22.1.7 Known limitations SCI wrong break duration Description A single break character is sent by setting and resetting the SBK bit in the SCICR2 register. In some cases, the break character may have a longer duration than expected: ● 20 bits instead of 10 bits if M = 0 ● 22 bits instead of 11 bits if M = 1 In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin. This may lead to generating one break more than expected.
PAGE 240
Known limitations 22.1.9 ST72321xx-Auto TIMD set simultaneously with OC interrupt If the 16-bit timer is disabled at the same time the output compare event occurs, the output compare flag then gets locked and cannot be cleared before the timer is enabled again. Impact on the application If the output compare interrupt is enabled, then the output compare flag cannot be cleared in the timer interrupt routine. Consequently, the interrupt service routine is called repeatedly.
PAGE 241
ST72321xx-Auto Known limitations Consequently, the LVD function is not guaranteed in the current silicon revision. For complete security, an external reset circuit must be added. 22.3.2 LVD startup behavior When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state. However, in some devices, the reset state is released when VDD is approximately between 0.8V and 1.5V. As a consequence, the I/Os may toggle when VDD is within this window.
PAGE 242
Revision history 23 ST72321xx-Auto Revision history Table 146.
PAGE 243
ST72321xx-Auto Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.