Data Sheet

AES-CELLIOT-AVT9152MOD
DATASHEET
The information in this document is subject to change without notice P a g e | 13
Rev 0.7.2 Sep 2020
Preliminary
6. DESIGN GUIDELINES
Please take note of following guidelines when designing Host PCB:
 There should be no copper pattern at the area underneath Bluetooth SMD antenna, on all layers of PCB.
Orientate the Module with the “no-copper area” at one corner of Host PCB, so that Bluetooth signal radiated
from the SMD antenna is not blocked by adjacent components.
 There are some exposed test pads at bottom side of module, for internal testing purpose. Cover all patterns
and via holes with soldermask on Host PCB, on the layer that is immediately below the Module, to avoid
shorting with test pads above them.
 The pin LTE_ANT on Module’s edge connector is for connection to customer’s choice of LTE antenna. The
RF trace on Host PCB connecting to this pin should be of 50Ω impedance.
 If LTE antenna is not a 50Ω antenna, e.g. FPC or SMD antenna, place up to 4 segments of R-C matching
network between LTE_ANT and antenna. The matching components should be placed as close to antenna as
possible. Default values of R1, R2, R3 and R4 are 0Ω while C1, C2, C3 and C4 are not mounted. User can
optimize their values with antenna and casing in place.