Specifications

3000 series eurocard switchers.ib.rev21.doc Page 13 of 36 16/10/2007
Signal path:
AVS-3010 & AVS-3011: Analogue video.
Video path: (See diagrams 803614 & 804070 sheet 2)
The incoming video signal on each of inputs 1 - 5 is connected to two BNC connectors on the rear assembly to
provide a loop through capability. One of these terminals must be terminated in 75 Ω either via a termination plug
or via other equipment.
Inputs 1 - 5 are terminated in 10 KΩ in order to reduce noise from unused inputs.
Cascade input PL3 (SMA connector) is terminated in 75Ω.
The inputs are then supplied to a pair of 4 x 1 video switch matrix IC’s U 1 & U 2 which are configured to operate
as a single 8 x 1 matrix. The two unused inputs are terminated in 75Ω to reduce noise.
The matrix is addressed by data lines a 0, a 1, a 2 & /a 2 produced by the PLA logic controller. This allows selection
of either no output or output from one only of the four inputs to each of U 1 & U 2. Thus when U 2 is active no
output is selected from U 1 and vice versa.
The outputs of the two halves of the matrix are mixed and then proceed to the output via U 3 which acts as a buffer
amplifier with gain (RV 1) and frequency compensation (C 8).
The output BNC connector is fed via a series resistor R 10, which provides the correct 75 Ω output source
impedance.
It should be noted that the video signal is DC coupled throughout.
Sync path: (See diagrams 803614 & 804070 sheets 1 & 2.)
The video output signal of U 3 buffer amplifier is AC coupled to an integrated sync detector IC U4 which provides
a vertical output sync pulse from the video signal.
If no vertical pulse is detected within approximately 25 ms U 4 will generate a pseudo vertical pulse. Thus, a sync
pulse will be provided even when an input is selected which has no sync. As this default period is longer than the
normal interval between vertical pulses the true vertical sync will prevail whenever it is present.
The output of the sync detector is passed through two monostable s which provide an adjustable delay (RV 2) such
that the output sync, “localvert”, is positioned to initiate switching on line 9 of the video signal.
The “localvert” signal is passed to the PLA via link LK 4, which allows a choice of internal or external sync to the
switcher logic. The chosen sync is echoed to “vertout” which is available on the PL 5 remote connector for slaving
other switchers. See Configuration section for details.
AAS-3020 & AAS-3021: Analogue audio. (See diagrams 803754 & 804115 sheet 1.)
The audio signals for Left & Right channels are processed by identical circuits; the Left on the main PCB and the
Right on a sub-board mounted over the Left channel section of the main PCB.
Balanced inputs 1 - 5 are terminated with resistors R 1 to R 20 resulting in an input impedance greater than 10 KΩ.
The signal is then buffered by amplifiers U 1 to U 5 and switched by analogue switch matrix IC’s U 6 & U7.
The matrix is addressed by data lines A & B, and enable lines CE 1 & CE 2 produced by the PLA logic controller.
This allows selection of either no output or output from one only of the input pairs to each of U 6 & U 7. Thus when
U 6 is active no output is selected from U 7 and vice versa.
The outputs of U 6 & U 7 are coupled in a low impedance mixing bus, which is available via J 4 for expanded
operation. See configuration section for details.
The mixing bus for the +ve and -ve signals is then buffered by U 8 with gain adjustment set by RV 1.
The balanced output connector is fed via series resistors R 26 & R 27, which provide an approximate 22 Ω output
source impedance.
Note that the audio signal is DC coupled throughout.