S System Reference S1
System Reference Agilent 93000 SOC P–Series and C–Series Legal Notice ISO 9001 Certification This document contains proprietary information that is protected by copyright. All rights are reserved. Produced to ISO 9001 international quality system standard as part of our objective of continually increasing customer satisfaction through improved process control. Revision 3.
Preface Objectives of this Manual The manual provides information about the properties of the specific test system hardware of the Agilent 93000 SOC Series. Audience The manual is intended for engineers on the testfloor (test engineers, production engineers, manufacturing engineers).
Preface Safety Information The following general safety precautions must be observed during all phases of operation, service, and repair of this system. Failure to comply with these precautions or with specific warnings in this manual, violates safety standards and the intended use of the system. Agilent Technologies assumes no liability for the customer’s failure to comply with these requirements.
Table of Contents Table of Contents Preface 3 Objectives of this Manual Audience Scope of the Manual Safety Information Table of Contents 3 3 3 4 5 List Of Figures 11 1 System Overview 15 Revision History Changes from Revision 1.0 (Aug. 99) to Revision 1.1 (Oct. 99) Changes from Revision 1.1 (Oct. 99) to Revision 2.0 (Dec. 99) Changes from Revision 2.0 (Dec. 99) to Revision 2.1 (Apr. 00) Changes from Revision 2.1 (Apr. 00) to Revision 2.2 (Jun. 00) Changes from Revision Revision 2.2 (Jun.
Table of Contents The Workstation 2 System Startup 31 Switching the Tester On Switching Procedure Warning Lamps Running the System Software Shutting down Switching the Tester Off Emergency Off 3 Hardware Components Tester Electronics Components Inside a 128 Pins Module Parametric Measurement Units Pin PMU High-Precision PMU Master Clock System 4 Test Head Filling and DUT Board Considerations Overview of Test Heads Structure of Card Cages DUT Board Mechanical Considerations Overview of DUT Board Option
Table of Contents DUT Board of Wafer Prober Probe Card-Pogo Pad Assignment 5 DUT Board Performance Considerations Signal Traces Keep-out Areas Maintaining Signal Fidelity Crosstalk Signal Inhomogeneities Correctly Terminating Signal Lines Why use Impedance Matching Techniques? How Transmission Lines are Terminated Terminating Output Pins Terminating Bidirectional Pins Termination Checklist Reducing I/O Round-Trip Times DUT Board Design for Mixed-Signal Tests Guidelines Grounding and Signal Shielding Print
Table of Contents Current and Voltage Measurements with DPS High Current Power Supply (HCDPS) HCDPS General Description HCDPS Specifications HCDPS Decoupling Recommendations HCDPS Switching Voltages (Vbump) Ganging HCDPS Boards Disconnecting the HCDPS Routing HCDPS Lines Current and Voltage Measurement Firmware Commands for the HCDPS High Voltage Power Supply (HVDPS) HVDPS Specifications 7 Analog Modules 168 168 176 176 177 177 177 177 178 178 181 182 183 Waveform Generators AWG Overview Theory of Opera
Table of Contents Adjusting Synchronization Timing 249 Considering Trigger-to-Signal Delay, Trigger Line, and Signal Line 250 Synchronization Uncertainty 254 Master Trigger Function 260 Appendices A XICOR EEPROM Summary Index System Reference, January 2001 267 269 9
Table of Contents 10 System Reference, January 2001
List Of Figures List Of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 System Reference, January 2001 P- and C-Models of the Agilent 93000 SOC Series 18 The Agilent 93000 SOC Series Tester 19 Test Processor-per-pin Architecture
List Of Figures Figure 34 Position of Analog and Digital Pad Blocks within Groups 69 Figure 35 Group reservation of the digital dominant type 512 pin SOC series tester m71 Figure 36 Groupreservationofthedigital dominanttype1024pinSOCseriestester m73 Figure 37 Group reservation of the analog dominant type 512 pin SOC series tester m74 Figure 38 Groupreservationoftheanalogdominanttype1024pinSOCseriestester m76 Figure 39 Card Cage Filling Options from DUT board "view" 78 Figure 40 FillOrderofAnalogInstruments
List Of Figures Figure 60 Relation Between Load Capacitance and Voltage Ripple - Range 1 m 148 Figure 61 Relation Between Load Capacitance and Voltage Ripple - Range 2 149 Figure 62 Relation Between Load Capacitance and Voltage Ripple - Range 3 m 149 Figure 63 Relation Between Load Capacitance and Voltage Ripple - Range 4 m 150 Figure 64 Measurement Block Diagram 151 Figure 65 Load regulation in performance range 1 151 Figure 66 Load regulation in performance range 2 152 Figure 67 Load regulation in perfor
List Of Figures Figure 96 Figure 97 Figure 98 Figure 99 Figure 100 Figure 101 Figure 102 Figure 103 Figure 104 Figure 105 Figure 106 Figure 107 Figure 108 Figure 109 Figure 110 Figure 111 Figure 112 Figure 113 Figure 114 Figure 115 Figure 116 Figure 117 Figure 118 Figure 119 Figure 120 Figure 121 Figure 122 Figure 123 Figure 124 Figure 125 Figure 126 14 Example for Using Loop Back Route 213 Coherent Sampling 217 Sampler Block Diagram 219 DC Routes 221 Loop Back Routes 222 TIA Measurement Functions 226 Tr
1 1 System Overview This chapter provides you with information on: • “System Characterization” on page 18 • “Major Components” on page 23 System Reference, January 2001 15
1 System Overview Revision History Revision History Changes from Revision 1.0 (Aug. 99) to Revision 1.1 (Oct. 99) The Chapter 6 “Device PowerSupply” on page 135 has been revised completely. Changes from Revision 1.1 (Oct. 99) to Revision 2.0 (Dec. 99) The Chapter 7 “Analog Modules” on page 183 has been added completely. Changes from Revision 2.0 (Dec. 99) to Revision 2.1 (Apr. 00) The Chapter 4 “Test Head Filling and DUT Board Considerations” on page 57 has been revised completely.
Revision History 1 System Overview Changes from Revision 2.2 (Jun. 00) to Revision 3.0 (Feb 01) The Chapter 7 “Analog Modules” on page 183 has been revised for supporting the new analog module, General purpose TIA and for adding the parameter usages of TIA.
1 System Overview System Characterization System Characterization The Agilent 93000 SOC Series offers solutions for testing the entire range of most integrated Systems-on-a-Chip (SOC).
System Characterization 1 System Overview MACH-D Testing Systems-on-a-Chip (SOC devices) means having the capability and flexibility to effectively and comprehensively test all the functional components of an SOC. These functional areas include • Memory • Analog • Communications • High-speed busses • Digital complex Addressing all these tester applications with one platform means dealing with two challenges: 1. Offering at-speed testing for highest speed devices combined with accurate analog test. 2.
1 System Overview System Characterization Technical Highlights Test Processor-Per-Pin The technology required to address these challenges is a Architecture highly integrated Tester-on-a-Chip. The Test Processorper-pin architecture combines all functions of the digital tester in one chip. This provides the foundation for full, fast and effective testing of all components integrated into SOC devices. µProcessor Bus Up to 1024 pins Formatter Timing Gen.
System Characterization 1 System Overview Digital Cards Analog Cards DC/DC Converters (in testhead) A C/D C Converters (in support rack) Figure 4 SOC System Integration In order to achieve this high level of integration, all components are water-cooled. By keeping the junction temperature close to the stabilized water temperature, all components of the test system which are critical for accuracy operate under very narrow and well-defined conditions.
1 System Overview System Characterization • Maximum of 8 DPS boards (960 pins testhead) containing 4 DPS channels each • Maximum of 8 blocks of 16 utility lines • 6 general drive/receive edges on software level mapped to 8 hardware drive edges (4 of them have tristate capability) and 6 hardware receive edges • Analog modules for high performance mixed-signal testing – High Resolution AWG (Arbitrary Waveform Generator) – High Speed AWG – Ultra High Speed AWG – High Resolution Digitizer – High Speed Digitiz
Major Components 1 System Overview Major Components The Agilent 93000 SOC Series test system consists of • Testhead with DUT Interface (“The Testhead” on page 24) • Manipulator for positioning the testhead (“The Manipulator” on page 26) • Support Rack supplying the testhead with mains power, cooling water, and compressed air (“The Support Rack” on page 27) Emergency OFF M anipu lator 1024 pins DUT board ON/OFF Switches Su pport Rack DUT interface 1024 pin testhead containing all the pin electronics
1 System Overview Major Components Manipulator Space for extensions Cooling Unit Main Power Supply Space for Workstation High Speed Optical Link Entire Tester Electronics resides in Test Head 32 Slots (448 pin + analog) (as shown here) HP-UX Workstation Figure 6 or 64 Slots (960 pin + analog) SOC Series Model with 448 Pins Testhead The Testhead The testhead is the heart of the system. It comprises all tester electronics and additional analog modules.
Major Components 1 System Overview DUT Interface Figure 7 Agilent 93000 SOC Series Testhead For detailed information on the tester electronics, refer to “Tester Electronics” on page 38. For detailed information on the analog modules, refer to Chapter 7 “Analog Modules” on page 183. DUT Interface The device under test (DUT) is mounted on a DUT board which is connected to the I/O channels by the DUT interface.
1 System Overview Major Components Cooling The testhead is water cooled. It receives its supply of cooling water from the support rack which in turn is connected by two flexible hoses to the cooling unit (refer to “The Cooling System” on page 28). The Manipulator The general-purpose manipulator supports and positions the testhead. It provides 6 degrees of freedom for the precise and repeatable connection between the testhead and handlers or wafer probers.
Major Components 1 System Overview The Support Rack The support rack is attached to the manipulator. The support rack is the interface between the testhead and its primary supplies (mains power, cooling water, compressed air). The SOC Series can also have additional support racks (analog support racks) for installing additional analog instruments.
1 System Overview Major Components Primary Power Box The primary power box inside the support rack contains the connections to mains, the system’s line switch, the line breaker, and individual breakers for the switched outlets, non/switched outlets, the auxiliary power supply and AC/ DC converters. AC/DC Converters The AC/DC cardcage contains eight resp. four water and air cooled AC/DC converter boards which supply the testhead with 385 V DC. Each board supplies one cardcage.
Major Components 1 System Overview In order to adapt to various environments, Agilent Technologies offers two different kinds of cooling systems: • The liquid/liquid Cooling Unit E2760D • The liquid/air Chiller Unit E2759D For detailed information on operation and control of the Cooling Unit resp. the Chiller Unit, refer to the Cooling System Guide. The Workstation The HP-UX workstation is the interface between the user and the Agilent 93000 SOC Series test system.
1 System Overview Major Components During test program execution, upload and download are typically not necessary, since the test processors act independently from the workstation once the test program is started. Diagnostics On the workstation, a diagnostic program can be run to check the system periodically or to identify the source of a problem.
2 2 System Startup This chapter provides you with information on: • “Switching the Tester On” on page 32 • “Running the System Software” on page 34 • “Switching the Tester Off” on page 35 System Reference, January 2001 31
2 System Startup Switching the Tester On Switching the Tester On The ON/OFF Unit is integrated in the front panel of the support rack. It provides illuminated ON/OFF buttons, an Emergency OFF button and an additional warning lamp. Emergency OFF ON (green) Standby (red) Figure 12 ON/OFF Switches on Support Rack Front Panel Switching Procedure To switch on the Agilent 93000 SOC Series test system: 1 Be sure the line switch at the rear of the support rack is in the ON position.
Switching the Tester On 2 System Startup ON (green) Figure 13 ON Button Green flashing (slow): The system starts cooling and connects mains to AC/DC converters and switched power outlets. Green flashing (fast): The system starts DC/DC converters. Cooling is okay. Green steadily lit: The system is up.
2 System Startup Running the System Software Running the System Software To start the SmarTest software, at the HP workstation type the following command at the HP-UX prompt: hp93000 [-o] The -o option starts the software in offline mode (hardware not connected). The user interface windows appear on the screen. For detailed information on starting up SmarTest, refer to the Test Setup manual (Part No. E7050-91010).
Switching the Tester Off 2 System Startup Switching the Tester Off To switch off the Agilent 93000 SOC Series test system: 1 Press the Standby button on the front panel of the support rack. Standby (red) Figure 14 Standby Button 2 For maintenance purposes only: Put the line switch at the rear of the support rack into the OFF position.
2 System Startup Switching the Tester Off Emergency Off In case of emergency: Press the red Emergency OFF button on the support rack. This will shut down the test system and the cooling unit. The unswitched power outlets and the auxiliary power supply are still connected to mains.
3 3 Hardware Components This chapter provides you with information on: • “Tester Electronics” on page 38 • “Parametric Measurement Units” on page 45 • “Master Clock System” on page 49 System Reference, January 2001 37
3 Hardware Components Tester Electronics Tester Electronics The complete tester electronics for up to 512 DUT pins (512 pins testhead) or up to 1024 pins (1024 pins testhead) resides in the testhead of the SOC Series test system. The testhead is divided into cardcages. A 512 pins testhead consists of four 128 pins modules, a 1024 pins testhead consists of eight 128 pins modules. The cardcage of each module can be equipped with channel electronics, power supply, and control boards for up to 128 DUT pins.
Tester Electronics 3 Hardware Components 128 pins modu le Figure 16 Tester Electronics Inside a 512 Pins Testhead System Reference, January 2001 39
3 Hardware Components Tester Electronics Components Inside a 128 Pins Module Device Power Supply The device power supplies (DPS) reside inside the testhead, which results in short cable connections and therefore low inductance. This is especially important for devices with high power consumption and high data rates. One DPS Board can reside inside a 128 pins module. A DPS board contains 4 DPS channels. A power supply channel is connected to the DUT’s power supply pin (Vcc, see figure below).
Tester Electronics 3 Hardware Components Channel Boards 4 resp. 8 channels are grouped on one channel module.
3 Hardware Components Tester Electronics The figure below depicts the pin electronics on a channel board. Pogo Pin DC Rail (1 per 128 pin module) ISOL Relay Channel Boa rd DC Rail (on Channel Board) DC Relay AC Relay Pin PMU Relay Per Pin Electronics ... Per Pin Electronics 50 50 Programmable Clamp Receiver ve Active Load Pin PMU Driver Per Pin Electronics monitor ou pu t P/F Figure 19 DC/DC Boards 42 ...
Tester Electronics 3 Hardware Components Clock Board The Clock Board provides the following resources shared by the digital channels of a 128 pins module: The Master Clock Generator generates the system’s master clock. The master clock is the timing reference for all timings. The master clock pulse is generated by the clock board that has been configured as master (usually the clock board of the 128 pins module 1).
3 Hardware Components Tester Electronics Analog Modules For precision mixed-signal testing, Agilent 93000 can have the following analog modules. • High resolution AWG (1 MSample/s 18-bit AWG) • High speed AWG (128 MSample/s 12-bit AWG) • Ultra high speed AWG (2.
Parametric Measurement Units 3 Hardware Components Parametric Measurement Units The SOC Series is equipped with two types of Parametric Measurement Units (PMUs): • Pin PMU, associated with a board ADC per 16 pins • High-Precision PMU per 128 pins For additional information on the PMUs, refer to the Standard Test Function Reference. Pin PMU Each digital channel provides an independent unit for DC tests—the Pin PMU.
3 Hardware Components Parametric Measurement Units The figure below shows the settling time of the parallel Pin PMU measurements and the subsequent conversion times needed for the multiplexed analog value conversions performed by the Board ADC. Pin PMU Settling Time Pin PMU 1 Pin PMU 2 Pin PMU 3 ... ... ... ... ...
Parametric Measurement Units 3 Hardware Components High-Precision PMU For high-precision value measurements, the SOC Series provides one High-Precision PMU (HPPMU) per 128 pins module. Voltages can be forced and currents measured (voltage force mode), or currents can be forced and voltages measured (current force mode). The High Precision PMU can be connected to any digital channel of the 128 pins module.
3 Hardware Components Table 2 Table 3 48 Parametric Measurement Units HPPMU # Channel #s 11 11701–12416 12 10101–10816 21 10901–11616 22 22501–23216 HPPMU Connections, SOC 512 DUT I/F HPPMU # Channel #s 11 12501–13216 12 11701–12416 21 22501–23216 22 21701–22416 31 10101–10816 32 20101–20816 41 20901–21616 42 10901–11616 HPPMU Connections, SOC 1024 DUT I/F System Reference, January 2001
Master Clock System 3 Hardware Components Master Clock System The master clock is the timing reference for all timings, and the heart of the test system. The tester hardware such as the digital channel boards and analog modules use the master clock for operating the hardware. In the world of mixed signal testing, two different master clocks are often needed to make use of the best performance of arbitrary waveform generators and waveform digitizers (including the sampler) involved in testing the device.
3 Hardware Components Master Clock System In each clock domain, you can select a master clock source from the internal master clock generator on the clock board or AMC (Alternate Master Clock generator) described in the next paragraph. Alternate Master Clock The AMC (Alternate Master Clock generator) is an optional signal generator used as a master clock generator. It is installed in the support rack and is connected to the external clock input of the clock boards in the testhead.
Master Clock System 3 Hardware Components For the master clock generator on the clock board, Range: 2 - 5 ns (200 MHz - 500 MHz) Max. Resolution: 15 digits (approx. 1 µHz) Note that there are some restrictions about maximum resolution that can be programmed on the software for digital channels using fixed timing. You can avoid them if timing equations are used.
3 Hardware Components Master Clock System All master clock sources are phase-locked on the distributed 10 MHz reference from one of the following: • Digital clock domain’s AMC • Analog clock domain’s AMC (if no digital clock domain’s AMC is configured) • Clock board in cardcage #1 on the 512-pin testhead or #5 on the 1024-pin testhead (if no AMC is configured) The following figures show the master clock distribution on the 512-pin and 1024-pin testheads.
Master Clock System 3 Hardware Components Analog Clock Domain Digital Clock Domain's AMC Cardcage#4 Board Digital/Analog Digital/Analog Board Board Digital/Analog Board Digital/Analog Inter. MCLK Gen. . Clock Board AMC Clock Board Inter. MCLK Gen. Digital/Analog Board Clock Board Analog Clock Domain's AMC AMC Master clock sources of analog clock domain are available for analog modules only.
3 Hardware Components Master Clock System Analog Clock Domain Cardcage#2 Board Digital/Analog Board Digital/Analog Board Digital/Analog Digital/Analog Board Digital/Analog Board Digital/Analog Board Digital/Analog Board Digital/Analog Board Digital/Analog Board Digital/Analog Board Cardcage#4 Cardcage#8 Cardcage#5 Cardcage#1 Cardcage#7 Digital Board Cardcage#3 Digital Board Digital Board Digital Board Digital Board Digital Board Digital Board Digital Board Digital Board Digital
Master Clock System 3 Hardware Components Available Master Clock Available master clock sources for tester hardware are as Sources follows: All digital channel boards: • Digital clock domain – Internal master clock generator in cardcage #1 on the 512-pin testhead or #5 on the 1024-pin testhead – Digital clock domain’s AMC All analog modules: • Digital clock domain – Same master clock source used for the digital channel boards (one master clock used) • Analog clock domain – Internal master clock generator
3 Hardware Components 56 Master Clock System System Reference, January 2001
4 4 Test Head Filling and DUT Board Considerations This chapter covers the DUT board structure and how to equip the test head with digital boards and analog modules. The chapter is divided into the following four sections: • “Overview of Test Heads” on page 59. • “DUT Board Mechanical Considerations” on page 61 concerning the packaged parts DUT boards. • “Test System Configuration” on page 70 from the view of the packaged parts DUT boards.
4 Test Head Filling and DUT Board Considerations Web Address of the DUT Board Design Guide Together with the Drawings and the Agilent 93000 DUT Board Design Guide (www.ate.agilent.com/ste/members/ member_index.shtml) you should then be able to design your customized DUT board. In case you want it to be designed or/and manufactured for you contact an Agilent Representative for assistance.
Overview of Test Heads 4 Test Head Filling and DUT Board Considerations Overview of Test Heads The Agilent 93000 SOC Series comes with a 512 pin and a 1024 pin test head. The two versions of the tester together with a sketch of their test heads are shown in Figure 27. Figure 27 Card Cage Positions within Test Head (Topview from DUT Board m Side) above their Corresponding SOC Series Testers.
4 Test Head Filling and DUT Board Considerations Overview of Test Heads Structure of Card Cages Figure 28 illustrates the structure of a card cage. Figure 28 Input of a card cage A card cage has the following content: • CLOCK DIST refers to the clock signal distribution in each single cage run by a clock board receiving their clock signals from a distributing master clock situated in only one of the cages.
DUT Board Mechanical Considerations 4 Test Head Filling and DUT Board Considerations DUT Board Mechanical Considerations This section gives you an overview of the mechanical structure of the SOC series packaged parts DUT boards. NOTE: Starting from here up to the end of this chapter, DUT board is used synonymously to packaged parts DUT board. Figure 29 on page 61illustrates the placing of the packaged parts DUT board above the test head. Figure 29 Position of DUT board above the Test Head.
4 Test Head Filling and DUT Board Considerations DUT Board Mechanical Considerations Instead of • a packaged parts DUT board , where the devices under test are placed directly on the DUT board, • a wafer prober DUT board can be placed on top of the DUT interface followed by several further components as illustrated in Figure 45 on page 104. For an overview of wafer prober DUT boards see “Wafer Prober DUT Board and Probe Card” on page 104.
DUT Board Mechanical Considerations SOC DUT board 4 Test Head Filling and DUT Board Considerations SOC-style DUT board F330-style DUT board Figure 30 DUT board options depending on test head size In Figure 30 the 1024 pin version of the SOC series tester is situated in the center and a 512 pin version is situated to either side of the 1024 pin tester.
4 Test Head Filling and DUT Board Considerations DUT Board Mechanical Considerations Allocation on the 512 pin DUT Board See also drawing D-E6980-96540-1S14D In Figure 31you can see which of the card cages of the 512 pin test head match which of the groups on the 512 pin DUT board. NOTE that the numbers of the groups have nothing in common with the numbers of the card cages. Figure 31 1. Allocation of the 512 pin DUT board’s groups to the card cages of the 512 pin test head. 2.
DUT Board Mechanical Considerations 4 Test Head Filling and DUT Board Considerations Allocation on the 1024 pin DUT Board See also drawing In Figure 32 you can see which of the card cages of the D-E6980-96550-1S14D 1024 pin test head match which of the groups on the 1024 pin DUT board. NOTE that the numbers of the groups have nothing in common with the numbers of the card cages. Figure 32 1. Allocation of the 1024 pin DUT board’s groups to the card cages of the 1024 pin test head. 2.
4 Test Head Filling and DUT Board Considerations DUT Board Mechanical Considerations Possible 256 pin DUT boards for either the 512 pin test head or the 1024 pin test head See also drawing D-E6980-96530-1S34D Additionally to the 1024 pin and the 512 pin DUT board you can have a 256 pin DUT board. The advantage of the 256 pin DUT board is that it is smaller and therefore cost saving. NOTE: Normally a 256 pin DUT board is for engineering use.
DUT Board Mechanical Considerations 4 Test Head Filling and DUT Board Considerations Make sure that your 256 pin DUT board possibility is located in that area of the DUT interface where the pogo pins of your pair of groups come out. Warning: Locating the 256 pin DUT board on the pogo pin area of two different groups for which it was not designed you will have to reconfigure your pins and very likely will have to change your card cage filling which may be impossible because of your tester configuration.
4 Test Head Filling and DUT Board Considerations DUT Board Mechanical Considerations column is currently not in use for digital measurement. You can find the number of a column below and above the pair of blocks in Figure 33. Numbering of pads: To refer to one of the signal pads on a pad block, the number of the pair of pad blocks is followed by the number of the column which contains the pad. For example: The crossed pad (column No.
DUT Board Mechanical Considerations 4 Test Head Filling and DUT Board Considerations Testhead Cable Outlet Side Group Model for Groups 2, 6, 7, 8 (Depending on Configuration) A / S2 D / S1 A / S2 D / S1 A / S2 D / S1 A / S2 D / S1 A / S2 D / S1 A / S2 D / S1 A / S2 D / S1 A / S2 D / S1 Analog or Digital DUT Board Group Model for Groups 1, 3, 4, 5 D / S1 S2 D / S1 S2 D / S1 S2 D / S1 S2 D / S1 S2 D / S1 S2 D / S1 S2 D / S1 S2 Pair of Pad Blocks Digital Only Figure 34 Position of Analog and Digit
4 Test Head Filling and DUT Board Considerations Test System Configuration Test System Configuration There are two types of test heads for the SOC series tester. They are the so called digital dominant type and the so called analog dominant type. The digital dominant type supports more digital pins the analog dominant one supports more analog modules. The maximum number of digital pins and analog modules in each case is shown in Table 4 on page 70.
Test System Configuration 4 Test Head Filling and DUT Board Considerations Digital Dominant Configuration The first part of this section deals with the 512 pin SOC series tester as the second part with the 1024 pin SOC series tester: 1. The reservation of groups of the digital dominant type of the 512 pin SOC series tester is illustrated in Figure 35.
4 Test Head Filling and DUT Board Considerations Test System Configuration There is a filling algorithm for filling the test head with digital boards and analog modules: • Digital Filling: Group 1 ---> Group 2 ---> Group 3 ---> (Group 8) • Analog Filling: (Group 8) only The bracket indicates that group 8 can optionally be used for digital or analog testing. For this reason you can find it under both list items.
Test System Configuration 4 Test Head Filling and DUT Board Considerations Figure 36 Group reservation of the digital dominant type 1024 pin SOC series m tester The lightly shaded (yellow) groups in Figure 36 are the only ones that can contain analog modules. Optionally, you can have digital boards or analog modules in these three groups. NOTE that Analog Module’s specifications can only be guaranteed if these groups contain analog modules only.
4 Test Head Filling and DUT Board Considerations Test System Configuration This system configuration has a maximum analog and a maximum digital configuration: • Maximum Analog: 24 analog modules ---> 640 digital pins • Maximum Digital: no analog modules ---> 1024 digital pins Analog Dominant Configuration The first part of this section deals with the 512 pin SOC series tester as the second part deals with the 1024 pin SOC series tester: 1.
Test System Configuration 4 Test Head Filling and DUT Board Considerations The unshaded (white) groups in Figure 37 can contain analog modules only. The shaded (dark grey) groups can only contain digital boards.
4 Test Head Filling and DUT Board Considerations Test System Configuration 2. The reservation of groups of the analog dominant type of the 1024 pin SOC series tester is illustrated in Figure 38. Figure 38 Group reservation of the analog dominant type 1024 pin SOC series tester m As shown in Figure 38, the upper light groups on the DUT board is for analog modules -- the unshaded (white) groups for analog modules only the light shaded (yellow) groups optionally for analog modules or digital instead.
Test System Configuration 4 Test Head Filling and DUT Board Considerations There is a filling algorithm for filling the test head is to be filled with digital boards and analog modules: • Digital Filling: Group 1 ---> Group 3 ---> Group 4 ---> Group 5 ---> (Group 7) ---> (Group 6) • Analog Filling: Group 8 ---> Group 2 ---> (Group 6) ---> (Group 7) The brackets indicate those groups that can optionally be used for digital or analog testing.
4 Test Head Filling and DUT Board Considerations Test System Configuration Overview of Filling The card cage filling options are listed in Figure 38. Figure 39 Card Cage Filling Options from DUT board "view" In the top two squares in Figure 39, the filling options within the digital dominant type for the 512 pin and the 1024 pin SOC series tester are listed. In the bottom squares you can find the analog dominant filling options. The filling is of the following four kinds: A, D, a and d.
Test System Configuration 4 Test Head Filling and DUT Board Considerations single group will be supported. NOTE that only digitizers are possible in such an analog half group and that Analog Module’s specifications can not be guaranteed. The numbers on top of the squares in Figure 39 are those of the groups that are filled in that column. The numbers on the left hand side of the boxes indicate the maximum number of digital pins you can obtain for the filling mentioned in the same row.
4 Test Head Filling and DUT Board Considerations Test System Configuration List of Analog Instruments In Table 5, the analog instruments are listed according to source and measurement depending on their functionality. • Source analog instruments generate the analog INPUT signal which goes into the DUT. Such analog signal generators are so called AWGs (Arbitrary Wafeform Generators). • Measurement analog instruments measure the analog DUT OUTPUTs.
Test System Configuration 4 Test Head Filling and DUT Board Considerations Analog Fill Order The order of analog filling depends on the test head configuration. Therefore, the fill order for the digital dominant configuration is described in part one of this section while you can find that one for the analog dominant configuration in part two. 1. The fill order of the analog instruments (see Table 5) is illustrated in Figure 40 for the digital dominant configuration.
4 Test Head Filling and DUT Board Considerations Test System Configuration The fill order of the cages is marked above the brackets at the top of the group scheme in Figure 40. NOTE: This is the fill order to follow. The fill order mentioned in the drawing E6980-96550-1S3 is INVALID. The slot number of the slots, where an analog module has to go within the cage, is mentioned to the left of the half groups.
Test System Configuration 4 Test Head Filling and DUT Board Considerations Source 1st 2nd 3rd 4th Max group 8 slot 8 group 8 slot 7 group 7 slot 8 3 LF-AWG group 8 slot 6 group 7 slot 6 group 7 slot 7 3 VHF-AWG group 8 slot 5a group 8 slot 5b group 7 slot 5a group 7 slot 5b 2 UHF-AWG group 8 slot 4 group 6 slot 4 group 6 slot 8 group 7 slot 4 4 LF-DGTZ group 8 slot 3 group 6 slot 3 group 6 slot 7 group 7 slot 3 4 VHF-DGTZ group 8 slot 2 group 6 slot 2 group 6 slot 6 gr
4 Test Head Filling and DUT Board Considerations Test System Configuration Figure 41 Fill Order of Analog Instruments within the Analog Dominant Configuration m In Figure 41the eight lightly shaded (yellow) boxes are the half groups of the four groups which can support analog instrument within the 1024 pin analog dominant configuration. Thus, for this configuration the analog instruments can only be placed in those card cages corresponding to groups 2, 6, 7 and 8.
Test System Configuration 4 Test Head Filling and DUT Board Considerations optional TIAs on top ( marked “slot b” in the table in Table 7). This way you can obtain a maximum number (MAX) of 4 GP TIAs. Otherwise, you can have up to 2 HP TIAs but in this case only 2 GP TIAs. In the case of the sampling instruments, there are two samplers in a slot as the samplers are dual and thus two count numbers each are assigned in Figure 41.
4 Test Head Filling and DUT Board Considerations Test System Configuration DPS-Type Fill Order As illustrated in Figure 42 on page 86, on a 1024 pin SOC DUT board, there are eight blocks of DPS pogo pads and four DPS blocks on a 512 pin SOC DUT board. As you can see in the figure there is always one DPS pogo pad block per group (black areas).
Test System Configuration 4 Test Head Filling and DUT Board Considerations A DPS block each requires a DPS card in the affiliated card cage of groupe where the DPS block resides.
4 Test Head Filling and DUT Board Considerations Test System Configuration Digital Dominant DPS-Type Group 1 Group 2 Group 3 Group 4 Group 5 Group 6 Group 7 Group 8 GP DPS 1 2 3 4 5 7 6 8 2 3 1 LN DPS HC DPS 5 4 1 3 2 7 6 8 HV DPS 5 4 1 3 2 7 6 8 Table 9 DPS-Types Sub-Sequent Filling Allgorithm, Digital Dominant Configuration Analog Dominant DPS-Type Group 1 Group 2 Group 3 Group 4 Group 5 Group 6 Group 7 Group 8 GP DPS 1 2 3 4 5 7 6 8 3 4 1 LN
Test System Configuration 4 Test Head Filling and DUT Board Considerations Analog Pogo Pad Location The pogo pads for the AWGs the Digitizers and the TIAs are assigned in the following three parts. Here a list of some of the abreviations used in the following three tables: • DGND stands for digital ground. • AGND stands for analog ground. • FGND stands for floating ground, i.e. no connection to any ground. These ones are kept for future expansion. • A+/- (B+/-,C+...
4 Test Head Filling and DUT Board Considerations Test System Configuration (For deeper insight in the mode of operation of the analog modules see Chapter 7 “Analog Modules” on page 183). 1 The pogo pad assignment for the AWGs is illustrated in Table 11.
Test System Configuration 4 Test Head Filling and DUT Board Considerations 2 The pogo pin assignment for the Digitizers is illustrated in Table 12.
4 Test Head Filling and DUT Board Considerations Test System Configuration According to drawings 3 The pogo pin assignment for the TIAs is illustrated in D-E6980-96540-1S24D Table 13.
Test System Configuration 4 Test Head Filling and DUT Board Considerations DPS Pogo Pad Functional Assignment Explanation of parts of drawings D-E6980-96540-1S24D (512 pins) and D-E6980-96550-1S24D (1024 pins) The functional assignment of the DPS pogo pads for the GP DPS and the HV DPS differs from that of the LN DPS and as well from that of the HC DPS. Therefore, this section is divided into three parts according to their different functional assignments : 1. GP DPS and HV DPS 2. HC DPS 3.
4 Test Head Filling and DUT Board Considerations Test System Configuration GPDPS and HVDPS, Functional In Table 14 the functional assignment of the DPS pogo Assignment of Pogo Pads pads either for the GP DPS or the HV DPS is illustrated. Additionally, the layout of a GP DPS or HV DPS block is illustrated on the left of the table. In Table 14, a, b and c refer to the three columns of 17 DPS pads each.
Test System Configuration 4 Test Head Filling and DUT Board Considerations There are always three power pads ganged in one channel. The available maximum current per channel is: • 8 A for the GP DPS. • 1 A for the HV DPS. Not available on the wafer prober DUT board The trigger line TR+ is reserved for a measurement initiation in a future extension. VB+ is a so called voltage bump. VB+ is a hardware triggered switch which allows you to change the voltage to a different value.
4 Test Head Filling and DUT Board Considerations Test System Configuration therefore there are fewer pogo pads in the High Current DPS pogo pad blocks then for the other DPS-types (LN DPS, GP DPS and HV DPS). This has to be considered designing your DUT boards. Preliminary Pogo Pad In Table 16, the preliminary functional assignment of the Functional Assignment of future LN DPS is illustrated.
Test System Configuration 4 Test Head Filling and DUT Board Considerations Utility, EEPROM and HPMU According to drawings D-E6980-96540-1S24D (512 pins) and D-E6980-96550-1S24D (1024 pins) For utility pads on the probe card see Table 23 and Table 24 on page 112. The Read/Write utility lines allow you to control external devices such as relays, solenoids or indicators, depending on the application.
4 Test Head Filling and DUT Board Considerations Test System Configuration • DSC states when the DUT board is Disconnected and when it has been taken off the test head. DSC has to be routed to UGND. The utility block ground pins (UGND) are isolated from the system GND to avoid noise. The four pad functions which are surrounded by a box in Table 17 and Table 19, are connections for the High Precision Parametric Measurement Unit (HPMU). The functions are as follows:: • PDCF is for the DC Force.
Test System Configuration 4 Test Head Filling and DUT Board Considerations Utility block 1 Utility block 2, 3, 4 a b a b 1 URW00 UGND UW00 UGND 2 UGND URW01 UGND UW01 3 URW02 URW03 UW02 UW03 4 URW04 UP5V UW04 UP5V 5 UP5V URW05 UP5V UW05 6 URW06 UW07 UW06 UW07 7 UW08 UGND UW08 UGND 8 DSC UW09 DSC UW09 9 UW10 UGND UW10 UGND 10 UGND UW11 UGND UW11 11 UW12 UGND UW12 UGND 12 UGND UW13 UGND UW13 13 URW14 UGND UW14 UGND 14 UGND URW15 UGND
4 Test Head Filling and DUT Board Considerations Utility block 1 Test System Configuration Utility blocks 3, 5, Utility blocks 2, 4, 7 6, 8 Pin No.
Test System Configuration 4 Test Head Filling and DUT Board Considerations Testhead Cable Outlet Side 8 Utility 7 DPS 4 Utility 8 DPS 2 DPS 3 Utility 7 Utility 6 DPS Group 7 Group 8 Group 2 Group 6 Group 4 Group 3 Group 1 Group 5 5 Utility 4 DPS 1 Utility 3 DPS 1024 Pin DUT Board 2 Utility 1 DPS 6 Utility 5 DPS 512 Pin DUT Board Figure 43 Position and Numbering of Utility Blocks (see also drawings D-E6980-96540-1S34D (512 pins) and m D-E6980-96550-1S34D (1024 pins) EEPROM Via th
4 Test Head Filling and DUT Board Considerations Test System Configuration test head cable outlet side Possible Positions for the EEPROM EPROM 1024 Pin DUT Board Figure 44 EPROM EPROM EPROM Utility Block 1 512 Pin DUT Board Possible Positions for EEPROM on DUT Board - View from DUT Side Table 21 shows, which of the EEPROM pins connect to which pogo pad of utility block 1.
Test System Configuration 4 Test Head Filling and DUT Board Considerations Utility Block 1 EEPROM X24C04 Utility Pad Name Utility Pad Functional Assignment EEPROM Pin Functional Assignment EEPROM Pin Numbering 13a URW14 SCL 6 14b URW15 SDA 5 14a UGND A0 1 14a UGND A1 2 14a UGND A2 3 14a UGND VSS 4 14a UGND WPI 7 05a UP5V VCC 8 Table 21 Functional Assignment of EEPROM Pins and Assignment of EEPROM Pins to Utility Pads of Utility Block 1 System Reference, January 2001
4 Test Head Filling and DUT Board Considerations Wafer Prober DUT Board and Probe Card Wafer Prober DUT Board and Probe Card In Figure 45 on page 104, the position of the wafer prober DUT board and the probe card above the test head is illustrated. You will find an overview of the wafer prober DUT board in “DUT Board of Wafer Prober” on page 105 . In section “Probe Card-Pogo Pad Assignment” on page 107 you are given an overview of the pogo pad assignment from probe card view.
Wafer Prober DUT Board and Probe Card 4 Test Head Filling and DUT Board Considerations DUT Board of Wafer Prober See also drawings D-E7018-96504-1S12B (512 pins) and D-E7018-96501-1S12B (1024 pins) For the SOC pogo tower there are two wafer prober DUT boards: 1. a 512 pin wafer prober DUT board. 2. a 1024 pin wafer prober DUT board. In Figure 45 on page 104, you are given a schematic drawing of an 1024 pin wafer prober DUT board.
4 Test Head Filling and DUT Board Considerations Wafer Prober DUT Board and Probe Card test head cable outlet side Area to optionally place additional components Area to optionally place additional components EPROM Figure 46 EPROM EPROM EPROM Schematic Drawing of Wafer Prober DUT Board Layout - View from DUT Side m As the circular area is limited in space and for ground reasons, as far as the signal lines are concerned, you have to decide either for digital only or analog only signal lines withi
Wafer Prober DUT Board and Probe Card 4 Test Head Filling and DUT Board Considerations Probe Card-Pogo Pad Assignment See the same drawing as in In Figure 47 on page 107, you are given a schematic “DUT Board of Wafer Prober” drawing of a probe card. on page 105 227 229 225 115 111 231 230 232 228 226 UT4 217 116 Seg .3 4 130 129 1 1 2 132 131 2 UT1 118 117 120 4 3 3 4 Seg .5 4 110 215 216 4 3 UT7 2 2 1 1 3 4 33 2 Seg.
4 Test Head Filling and DUT Board Considerations DPS pogo pads Wafer Prober DUT Board and Probe Card The units next to the center of the probe card with the grey numbers are for the DPS pogo pads: Those four units next to the utility lines contain the ground and the power lines of the four DPS channels 1-4, while the four units next to the center of the probe card contain the gard lines, power and ground sense lines and the ground lines of channels 1-4.
Wafer Prober DUT Board and Probe Card 4 Test Head Filling and DUT Board Considerations input-output pogo pads on the The lightly shaded grey area of Figure 48 on page 108 probe card contains the pogo pads of the input -output signal lines (circles with numbers). The small white dots between the signal pads are the ground pads. The area consists of 8 units as indicated by the dashed lines. Each unit contains 16 of those signal lines.
4 Test Head Filling and DUT Board Considerations 17th signal lines on the probe card Wafer Prober DUT Board and Probe Card In Figure 33 on page 67, additionally, a 17th signal line is illustrated. Four of the eight 17th signal lines of a group each are also available on a probe card segment. They are placed in the smaller lightly shaded grey area on the left side of the white area. Table 22 shows the numbers of the pairs of pogo pad blocks the four 17th signal lines connect to within the groups.
Wafer Prober DUT Board and Probe Card 4 Test Head Filling and DUT Board Considerations Naming of Utility Pogo Pads on Probe Card Function of the Utility Pogo Pads U01 UG U02 URW00 UW00 UW00 UW00 U03 URW01 UW01 UW01 UW01 U04 URW02 UW02 UW02 UW02 U05 URW03 UW03 UW03 UW03 U06 URW04 UW04 UW04 UW04 U07 5V 5V 5V 5V U08 5V 5V 5V 5V U09 URW05 UW05 UW05 UW05 U10 URW06 UW06 UW06 UW06 U11 UW07 UW07 UW07 UW07 U12 UW08 UW08 UW08 UW08 U13 UG UG U14 UW09 UW09 UW09 UW09 U15 UW10
4 Test Head Filling and DUT Board Considerations Wafer Prober DUT Board and Probe Card Function of the Utility Pogo Pads Naming of Utility Pogo Pads on Probe Card U01 UG U02 URW00 URW00 UW00 URW00 UW00 URW00 UW00 URW00 U03 URW01 URW01 UW01 URW01 UW01 URW01 UW01 URW01 U04 URW02 URW02 UW02 URW02 UW02 URW02 UW02 URW02 U05 URW03 URW03 UW03 URW03 UW03 URW03 UW03 URW03 U06 URW04 URW04 UW04 URW04 UW04 URW04 UW04 URW04 U07 5V 5V 5V 5V 5V 5V 5V 5V U08 5V 5V 5V 5V 5V 5V 5V 5V U09 URW
Wafer Prober DUT Board and Probe Card 4 Test Head Filling and DUT Board Considerations The abbreviations of the utility pogo pad functions of Table 23 and Table 24 hve the following meaning: • ## is the numbering of the read and write or write only utility lines. Thus there are 15 utility lines per segment. This numbering is consistent with the numbering of the utility lines on the packaged parts DUT boards which is illustrated in Table 17 on page 99 and Table 19 on page 100.
4 Test Head Filling and DUT Board Considerations Wafer Prober DUT Board and Probe Card Table 25 assigns the number of the HPMU the four lines of a segment are connected to. Segment (Group) No. containing the PogPads 1 of Sense, Ground Sense, Force and Gard Line No.
5 5 DUT Board Performance Considerations This chapter provides you with information on: • “Signal Traces” on page 116 • “Maintaining Signal Fidelity” on page 118 • “Correctly Terminating Signal Lines” on page 120 • “Reducing I/O Round-Trip Times” on page 123 • “DUT Board Design for Mixed-Signal Tests” on page 124 System Reference, January 2001 115
5 DUT Board Performance Considerations Signal Traces Signal Traces Landing holes/vias are inside the landing pads. The via-inpad method provides better contact reliability than pogoon-surface methods. High-Frequency Testing Testing at high frequencies requires an impedancematched environment. The board should therefore be designed to match the tester impedance. For proper operation, the impedance specification of 50 Ω ±10% must be met.
Signal Traces 5 DUT Board Performance Considerations with higher pin count. Without these dummy pads, the pogo pins of the DUT interface may damage the unprotected DUT board over time. Typical pad size is 1.6 to 1.8 mm, hole diameter is 0.7 mm. Landing Holes We recommend to use pogo landing holes (plated through holes) instead of plane pads for better contact quality. A landing hole provides a 3-point signal contact, whereas a plane pad has a single contact point only.
5 DUT Board Performance Considerations Maintaining Signal Fidelity Maintaining Signal Fidelity Because the tester does not limit your choice of pin-tochannel allocation, you can design the DUT board layout so that you get the best possible signal fidelity at high frequencies. When you design a new DUT board for high-frequency test applications (or have one designed for you), you have to ensure that the board will transport the test signals to the DUT and back without appreciable loss of signal quality.
Maintaining Signal Fidelity 5 DUT Board Performance Considerations Signal Inhomogeneities Inhomogeneities cause reflections in the signal paths as well as signal deterioration due to attenuation and phase changes. Minimize signal inhomogeneities by: • avoiding runs of wire on the DUT board • avoiding vias on the board if possible. If the use of a via is unavoidable, make sure to specify a 50 Ohm equivalent via to the custom DUT board manufacturer. • avoiding stubs.
5 DUT Board Performance Considerations Correctly Terminating Signal Lines Correctly Terminating Signal Lines The guidelines below give you a simplified view for handling transmission lines. Why use Impedance Matching Techniques? At the high edge-transition speeds of the tester, traces and coaxial cables start to behave like transmission lines. If not properly terminated, every pulse transition that you send is reflected back down the line.
Correctly Terminating Signal Lines 5 DUT Board Performance Considerations Terminating Output Pins Output pins are not automatically provided with termination. If you believe that the outputs from a DUT are operating fast enough to cause transmission line effects, you can add a 50 Ω termination load. When you select termination for your DUT output, the load is provided by the driver-half of the IO channel. Setting Termination Voltage In general, if you use ECL-type levels, (usually –1.7 V low and –0.
5 DUT Board Performance Considerations Correctly Terminating Signal Lines Termination Checklist 50 Ohm Environment If you are operating in a standard 50 Ω environment, no extra action is needed as far as component layout on the DUT board is concerned. You define the termination in the Level setup. Active Load If you terminate the line with the help of the active load, no additional action is needed as far as component layout on the DUT board is concerned. You define the active load in the Level setup.
Reducing I/O Round-Trip Times 5 DUT Board Performance Considerations Reducing I/O Round-Trip Times For bidirectional pins, such as data bus pins, you have to consider the total I/O round-trip time of the signal from the I/O Board to the DUT pin and back. This is because at high vector rates the signal direction changes so often so that the signals being sent from the tester may collide with data being sent by the DUT.
5 DUT Board Performance Considerations DUT Board Design for Mixed-Signal Tests DUT Board Design for MixedSignal Tests The previous sections describes the information for the DUT board design focused on digital testing. This section provides information focused on mixed-signal testing. Analog signals can be easily disrupted by pulses (for example clocks and digital signals). To avoid this problem, both signal types must be physically separated.
DUT Board Design for Mixed-Signal Tests 5 DUT Board Performance Considerations • Problems will occur: Ensure that the DUT board can be easily changed and debugged. • Ensure that the required auxiliary components do not interfere with the IC handler or waver prober. If possible, consider mounting the components on the rear of the DUT board.
5 DUT Board Performance Considerations DUT Board Design for Mixed-Signal Tests Grounding and Signal Shielding Grounding Proper grounding is essential for precise measurements. Mixed-signal devices differentiate between digital and analog ground and often also between digital and analog supply voltage.
DUT Board Design for Mixed-Signal Tests 5 DUT Board Performance Considerations Matching the impedance of the signal source should be a matter of course. This avoids reflections and is essential for all high frequency analog signals. Low voltage ECL signals, too, should only be transported by impedance matching coaxial cables. The cable shield is normally connected to the respective analog or digital ground, except for DC signals to to from the PMU.
5 DUT Board Performance Considerations DUT Board Design for Mixed-Signal Tests • Bypass capacitors should include electrolytic and ceramic capacitors. Electrolytic capacitors (10 µF...100 µF) cover the low frequency range.They can be positioned anywhere on the DUT board. Ceramic capacitors (10 nF...100 nF) cover the high frequency range. They should be placed as close to the DUT pins as possible.
DUT Board Design for Mixed-Signal Tests 5 DUT Board Performance Considerations Printed Circuit Board To run the same application on multiple testers for production tests, the DUT board is developed as a printed circuit board (PCB). As the operation rate of a mixed-signal device increases, application engineers who develop test circuits need to be skilled not only in schematic design but also in printed circuit board design.
5 DUT Board Performance Considerations DUT Board Design for Mixed-Signal Tests where Er means the relative dielectric constant of the board material. The following figure shows the model of a strip line: w Ground Plane t b Strip Line h Ground Plane Characteristic Impedance: Zo = 60 Er Figure 52 NOTE ln 0.67 4* b 0.8*w + t Strip Line Model As shown in the above figures, the microstrip line and strip line consist of a set of a trace and ground or power plane(s).
DUT Board Design for Mixed-Signal Tests 5 DUT Board Performance Considerations Blunt Corners Sharp Corner Rounded Corner Signal Input Figure 53 Sharp Corner In the above example, if the signal frequency is very high, the sharp corner causes signal reflections. Use a blunt corner or rounded corner instead of the sharp corner. Stubs Figure 54 Branch (Stub) In the above example, if the signal frequency is very high, these stubs cause signal reflections at the points.
5 DUT Board Performance Considerations DUT Board Design for Mixed-Signal Tests l d Figure 55 Signal Lines To avoid the crosstalk in your test circuit, you must consider the following: • For traces that carry high frequency signals (such as clock), do not draw these traces in parallel. • (If possible) Use a coaxial cable to protect any sensitive signal from noise. • Increase the distance between traces. • Decrease the adjacent surfaces by bending the traces. • Use a guard line between traces.
DUT Board Design for Mixed-Signal Tests 5 DUT Board Performance Considerations Consider the following measures: • Change the position of components or cables. Separate input and output lines physically. • Use coaxial cables to protect sensitive signals. • Ensure that all ground connections are as short as possible. • Increase the digital and analog ground planes. • Add bypass capacitors. • Use guard lines to shield voltage force/sense lines.
5 DUT Board Performance Considerations 134 DUT Board Design for Mixed-Signal Tests System Reference, January 2001
6 6 Device PowerSupply This chapter provides you with information about the various Power Supplies available for the Agilent 93000 SOC Series Tester. There are three types: • “General Purpose Power Supply (GPDPS)” on page 136 • “High Current Power Supply (HCDPS)” on page 168 • “High Voltage Power Supply (HVDPS)” on page 181 The following sections describe these in detail.
6 Device PowerSupply General Purpose Power Supply (GPDPS) General Purpose Power Supply (GPDPS) This section provides you with information on: • “GPDPS General Description” on page 136 • “GPDPS Specifications.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply To best adapt DPS channels to the appropriate test requirements you can also select between 4 different performance ranges that switch the internal gain of the DPS control loop.
6 Device PowerSupply General Purpose Power Supply (GPDPS) Important features of the General Purpose Device Power Supplies are: • Each DPS channel has two DACs for voltage setting. A trigger input (Vbump input) lets you switch between these two DACs. • Each DPS channel is supplied with two current DACs one to set a positive current limit (clamp) and one to set the negative current limit. • Power up and hardware reset puts all four channels of a GPDPS board into HIZ mode.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply GPDPS Specifications. The following supply voltage/current range specifications apply for the General Purpose Device Power Supply: Mode Range Resolution Accuracy Comments Voltage force –7...+7 V –8...+8 V 1 mV 1 mV ±5 mV ±0.1% ±5 mV ±0.1% Imax = +8 A, –4 A Imax = ±4 A Voltage measure –8...+8 V 1 mV ±5 mV ±0.1% Current force (clamp) –4 A, +8 A 1 mA ±20 mA ±0.5% 16 samples Current measure –8...+8 A –0.3...+0.3 A –10...
6 Device PowerSupply General Purpose Power Supply (GPDPS) Supply Current Supply Voltage Figure 58 NOTE General Purpose Power Supply: Power Diagram Current measurement ranges and performance ranges are completely independent of each other. There is only a dependency with respect to the maximum achievable measurement accuracy. As mentioned above, this accuracy can only be achieved if the maximum capacitive load does not exceed 1µF.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply Setting up Performance Ranges To fully exploit the benefits of the GPDPS design, which includes highest measurement accuracy for IDDQ current measurements and excellent regulation of current variations, performance ranges for the Agilent 93000 SOC Series General Purpose Device Power Supply have been introduced. The subsequent sections explain the new concept in detail and lead you through the required setup steps.
6 Device PowerSupply General Purpose Power Supply (GPDPS) An essential component of the GPDPS is the load capacitor that needs to be added at the DPS pin. This load capacitor ensures that the GPDPS operation is stable under all load conditions. Its size depends on the performance range set. NOTE You must not operate the GPDPS without an adequate load capacitor. The GPDPS will only provide stable operation with an adequate blocking capacitor. The following performance ranges are available: Range Min.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply Why are Performance Ranges Useful? Performance Ranges guarantee the best trade-off between measurement accuracy in iddq measurements and the capability of the GPDPS to drive a specific current swing. In other words, performance ranges permit the characteristics of a GPDPS channel to be adjusted to suit a specific DUT. Current swings up to 8A can be regulated with a single GPDPS channel operating in performance range 4.
6 Device PowerSupply General Purpose Power Supply (GPDPS) 4. Find out the maximum voltage ripple your DUT can tolerate. Dimension the load capacitance (Cload) accordingly. “Dynamic Load Performance Considerations” on page 145 helps you to find an adequate load capacitance. 5. Set the performance range by opening the Pin Configuration Editor window and type in the appropriate value of the load capacitance (load C) in the Ser.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply – Load C 4µF to < 20µF selects the performance range 2 – Load C 20µF to < 100µF selects the performance range 3 – Load C ≥ 100µF selects the performance range 4 Note: It is also possible to set or change the performance range in your device setup with the firmware command PSCL: PSCL , () := 1, 2, 3, 4 Dynamic Load Performance Considerations The sense line monitors the DPS voltage level and the contro
6 Device PowerSupply General Purpose Power Supply (GPDPS) • load capacitance Basically, each performance range requires a minimum load capacitance to ensure stable operation. Further increasing the load capacitance increases the low pass filter effect and smooths the supply voltage from large voltage ripples if load conditions change. Alternatively, high load capacitances slow down dynamic performance and introduce current noise into GPDPS current measurements.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply The following table helps you to find the appropriate performance range and capacitive load: Range Min. Cload CDV<200mV Current swing CDV<200mV Current swing 1 100nF 100 nF 60 mA <4 µF 100 mA 2 4µF 4 µF 300 mA <20 µF 400 mA 3 20µF 20 µF 1.0A <100 µF 1.5 A 4 100µF 100 µF 3A 3000 µF 8A Range 1 max.
6 Device PowerSupply General Purpose Power Supply (GPDPS) range of 100mA to 400mA, performance range 3 typically for swings in the range of 400mA to 1.5A and performance range 4 typically for swings in the range of 1.5Ato 8A. The following figures show the relationships between the voltage supply ripple and the smoothing capacitance for various current swings in each performance range.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply Figure 61 Relation Between Load Capacitance and Voltage Ripple - Range 2 Figure 62 Relation Between Load Capacitance and Voltage Ripple - Range 3 m System Reference, January 2001 149
6 Device PowerSupply Figure 63 General Purpose Power Supply (GPDPS) Relation Between Load Capacitance and Voltage Ripple - Range 4 m Examples of Dynamic Load Performance To illustrate the GPDPS characteristics, examples of measurement plots are illustrated in the following figures. The measurement setup used is shown in Figure 64. One measurement for each performance range has been performed using a hand-wired loadboard.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply If you further increase the load capacitance, the initial voltage ripple will be reduced but voltage ringing may appear. See also the example “Measurement in Performance Range 2 with High Load Capacitance” on page 153. Scope DPS C R i i Figure 64 Measurement Block Diagram Measurement in Performance Range 1 [V] 20 mA –> 0 0 –> 20 mA U = 4.
6 Device PowerSupply General Purpose Power Supply (GPDPS) Measurement in Performance Range 2 [V] 200 mA –> 0 0 –> 200 mA U = 4.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply Measurement in Performance Range 4 [V] 8 A –> 0 0 –> 8 A U = 4.
6 Device PowerSupply General Purpose Power Supply (GPDPS) The effect of a high load capacitance in this performance range can clearly be seen: • the voltage ripple is reduced • ringing occurs • recovery of the DPS voltage level takes longer Decoupling Recommendations Powering noise-sensitive DUTs requires noise filtering on a load board level. For this purpose, installation of bypass capacitors is necessary.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply Noise Capacitance < 30 mVpp 100 nF (min.) < 20 mVpp 500 nF < 10 mVpp 1 µF (max.) Table 29 Bypass Capacitance to Filter Out GPDPS Related Noise For noise-sensitive applications, we recommend a capacitance of 1 µF. Larger values will reduce measurement accuracy. Switching DPS Voltages (Vbump) Switching of DPS voltages is, for example, needed in data retention tests.
6 Device PowerSupply General Purpose Power Supply (GPDPS) If the trigger signal goes from 0V to 5V, Vbump is triggered and the DPS switches to the second voltage. Because the voltage switching requires a small settling time, the DUT pins are disconnected (BREAK) during this period. This is illustrated in the Figure 70 below which also shows the trigger paths.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply Voltage Settling Times The voltage settling time is defined by an internal 1 kHz RC-low pass filter. This low pass filter is needed to limit overshoots during voltage steps. The plots shown below illustrate that voltage settling is easily predictable in most situations (Figure 71 on page 157). NOTE There is no significant difference in the voltage settling behaviour between: connect operation, reprogramming of voltage, or the Vbump function.
6 Device PowerSupply General Purpose Power Supply (GPDPS) [V] 0 –> 5 V Performance Range 1 Figure 72 [s] Voltage settling, load capacitance 100µF This plot illustrates what happens if the load capacitance is too high. Transient oscillations will occur. [V] 100 µF 3000 µF 5000 µF 0 –> 5 V, performance range 4, Cload = 100 µF, Cload = 3000 µF, Cload = 5000 µF iclamp = 8 A Rload = 1 DPS channel switching into current clamp mode; current is clamped at iclamp.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply If the load capacitor is too high the DPS channel switches into current clamp mode. The current clamp mode limits the maximum DPS current. As can be seen, this behavior results in a significantly increased voltage rise time. Ganging GPDPS Channels In order to achieve a higher output current, you can operate multiple GPDPS channels in parallel, known as the Ganged Mode. This mode is useful e.g. for large CPUs and modules.
6 Device PowerSupply General Purpose Power Supply (GPDPS) The channels of one ganged group have to be in sequence (e.g. DPS11, 12, 13, 14, 21 etc.). Note that it is not possible to gang different types of power supplies together. For details on cable assembly on the DUT board refer to “Routing DPS Lines” on page 163. Setting up Ganged GPDPS Channels Basically, ganged GPDPS channels can be set up in the Pin Configuration window.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply All Power (Force+) and Ground (Force–) pins and all Sense pins must be wired on the DUT board according to the Figure 74 on page 161. To avoid introducing an unwanted potential difference between the DUT pin and the ganged connections, make the connection as close as possible to the supply pin.
6 Device PowerSupply General Purpose Power Supply (GPDPS) Disconnecting the DPS A connected DPS forces the programmed power supply voltage (FW command PSLV). The current is limited to the connect current limit. If the supply reaches the current limit, the voltage at the DUT is decreased. In this case, warnings are displayed in the Report Window.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply Routing DPS Lines Ensure that Power and Ground lines are laid out one directly above the other. Wire width = 3 A/mm2. Sense lines must be positioned close together and parallel to each other to avoid induction of interference. Furthermore, Sense/Force connections must be positioned as close as possible to the DUT.
6 Device PowerSupply General Purpose Power Supply (GPDPS) Current and Voltage Measurements with DPS Device Operation Sequence The figure below shows a typical device operation sequence. device stop functional tests 1 operating current measurement 2 3 functional tests digital operations connect device restart digital operations wait for current settling IDDQ measurement 4 5 disconnect time Udevice Figure 76 Device Operation Sequence 1. Connect: Please note the transient time.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply 4. Device stop: Wait time due to transient time of the voltage controller and the resulting balancing currents in the load capacitor. There is no difference in the execution time for a firmware command or test function, whether the test executes for pass/fail results or for results by value. Due to autoranging, the measurement time depends heavily on the value to be measured.
6 Device PowerSupply General Purpose Power Supply (GPDPS) Range Wait time (GP-DPS) Voltage 0.5 ms 10 A 0.07 ms 300 mA 0.1 ms 10 mA 0.1 ms 100 µA 5 ms Table 30 Wait time required for measurement path to settle 3. In order to select the subsequent measurement path (autoranging), a single measurement is used. 4. After the measurement path has settled, the remaining measurements are performed.
General Purpose Power Supply (GPDPS) 6 Device PowerSupply Sample IDDQ Current Settling Time The table below shows the settling time required for static IDDQ current measurements (sample IDDQ only). The load step appearing when halting the clock, has to be regulated by the DPS. It results in a current flowing through the measurement shunts into the DUT bypass capacitor. The minimum settling time depends on the load and test situation and should be evaluated on a case by case basis.
6 Device PowerSupply High Current Power Supply (HCDPS) High Current Power Supply (HCDPS) This section provides you with information on: • “HCDPS General Description” on page 168 • “HCDPS Specifications” on page 176 • “HCDPS Decoupling Recommendations” on page 176 • “HCDPS Switching Voltages (Vbump)” on page 177 • “Ganging HCDPS Boards” on page 177 • “Disconnecting the HCDPS” on page 177 • “Routing HCDPS Lines” on page 177 • “Current and Voltage Measurement” on page 178 • “Firmware Commands for the HCDPS”
High Current Power Supply (HCDPS) 6 Device PowerSupply Connection to DUT Board The HCDPS is connected to the DUT Board with a special high current, low impedance connecting cable. The cable ends in a pogoblock, consisting of 4 special power pins (Force +) and 4 power ground pins (Force -), capable of carrying 100 ampere in total.
6 Device PowerSupply High Current Power Supply (HCDPS) Block Diagram The following figure shows, in principal, the layout of the HCDPS Figure 78 High Current DPS Block Diagram The main sections of the HCDPS consist of 1. The BUS interface This is basically the same as the BUS interface for the General Purpose DPS.
High Current Power Supply (HCDPS) 6 Device PowerSupply 2. The multiphase stepdown converter This converter steps down two raw +12V supplies to the required output level. It consists of an array of 2, 6 phase step-down converters, each phase shifted 30 degrees to each other. Because of this multiphase technology, ripple and the size of the circuit is minimized and speed is enhanced. Each pair of switches has its own 4-wire series resistor to measure current.
6 Device PowerSupply High Current Power Supply (HCDPS) c. Over-temperature Protection It is possible to add a heat or smoke sensor to the DUT-Board in such a way, that, in the event of an emergency, the safety_line will be pulled down resulting in a shutdown of all HCDPS units simultaneously. d. Over-voltage Protection. Here, there are three levels of protection: I) Programmable protection: This is set with the Firmware command PSOP as described on page 178.
High Current Power Supply (HCDPS) 6 Device PowerSupply e. Over-current Protection There are two modes to be considered here: I) Constant current mode: When the current limit is reached, the HCDPS operates as a constant current source. Note: Constant current mode is not possible in ganged mode. II) Clamp mode: When the current limit is reached, the DPS switches to tristate.
6 Device PowerSupply High Current Power Supply (HCDPS) 5. Diagnostic Circuits As with the General Purpose and High Voltage power supplies, the HCDPS contains additional circuits for diagnostic purposes. The following diagnostic facilities are provided: – Detection of failure of ASTEC-raw power. – Detection of overcurrent and overvoltage. – Detection of the state of safety-lines at the DUTBoard. – For measuring the impedance i.e.
High Current Power Supply (HCDPS) 6 Device PowerSupply diagnostics. This means, that you cannot run any other tests while performing the at-speed test. The HCDPS atspeed loadboard is configurable and can be adapted to each testhead configuration for HCDPS boards at various positions. To permit the HCDPS to be tested at maximum current, each HCDPS pin is short-circuited. This test can only be carried out in current mode.
6 Device PowerSupply High Current Power Supply (HCDPS) HCDPS Specifications Type Value Resolution Accuracy Voltage force 0.3...2.5V (100 Amax) 2.5...4V (50 Amax) 1mV ±5mV Voltage measure 0V...4V 1mV ±5mV Current clamp +1...100A 100mA for I≤10A: ±(200mA+0.5% of value) for I>10A: ±(200mA+2% of value) Current measure ±100A 10mA for 0-100A: ±(100mA+0.
High Current Power Supply (HCDPS) 6 Device PowerSupply HCDPS Switching Voltages (Vbump) This is described in “Switching DPS Voltages (Vbump)” on page 155. Note, however, that the HCDPS board only contains one supply (channel) and not four as is the case with the General Purpose and High Voltage Power Supplies. Ganging HCDPS Boards Normally a maximum of two boards can be ganged together to generate up to 200A.
6 Device PowerSupply High Current Power Supply (HCDPS) Current and Voltage Measurement As with the General Purpose and High Voltage DPS, the High Current DPS can be triggered with a +5V signal (see “Trigger Circuit” on page 175) to cause it to commence with measurements of voltages and/or currents. As the HCDPS only has only one range, it measures all currents in the high current range.
High Current Power Supply (HCDPS) 6 Device PowerSupply disconnect is a hardware functionality which is only available with the High Current DPS. If this command is executed for the General Purpose DPS or High Voltage DPS, it will have no effect. The PSOP? query returns the last programmed value. Syntax: PSOP ,{(pinlist)} PSOP? {(pinlist)} returns PSOP ,{(pinlist)} Parameters: 0 Overvoltage protection (disconnect) disabled. 1 Overvoltage disconnect at U>Uset+0.2V.
6 Device PowerSupply High Current Power Supply (HCDPS) Syntax: HSCM {mode} HSCM? {mode} returns HSCM {mode} Parameters: mode This parameter specifies the DPS clamp mode and can take the values: LIMIT The output current is limited to the programmed current value. OFF The affected DPS channel is switched off if overcurrent occurs. Other power supply channels remain in operation. DELAYED_1 The affected DPS channel is switched off after 2 ms if overcurrent occurs.
High Voltage Power Supply (HVDPS) 6 Device PowerSupply High Voltage Power Supply (HVDPS) This section provides you with information on: • “HVDPS General Description” on this page. • “HVDPS Specifications” on page 182.
6 Device PowerSupply High Voltage Power Supply (HVDPS) also the section “Setting up Performance Ranges” on page 141 for more details, but note that although the General Purpose DPS can deliver currents of up to 8A, the High Voltage DPS can only deliver currents up to a maximum of 1A so that mention of currents above 1A are irrelevant for the High Voltage DPS.
7 7 Analog Modules Testing of mixed-signal devices requires analog resources for applying highly accurate analog signals to devices and capturing analog signals output from devices. Further, the analog resources are required to operate with digital signals synchronously.
7 Analog Modules Waveform Generators Waveform Generators There are three types of AWGs available as follows: • High Resolution AWG (1 MSample/s 18-bit) Code name: WGA • High Speed AWG (128 MSample/s 12-bit) Code name: WGB • Ultra High Speed AWG (2.6 GSample/s 8-bit) Code name: WGC AWG Overview The arbitrary waveform generator (AWG) can source sine waves, pulse waves, ramp waves, pseudo-random noise, and various other waveforms to DUTs.
Waveform Generators 7 Analog Modules Waveform Segments (Mixed-Signal Tool) B A C Sequence Program (Analog Setup Tool) 3 Loops of A Downloading Waveform Memory B A C Downloading Controlling Output Order Sequencer DAC AWG Outputting One Waveform awg_ov Figure 79 Analog Waveform Generation The AWGs start waveform generation by entering the external triggers. Generally, a digital channel is used for each AWG as the external trigger source. A trigger signal must be supplied at the SYNC CLK pin.
7 Analog Modules Waveform Generators The following tables show the key specifications of the AWGs. Specification Value Pin counts per module 8 single-ended (4 parallel test) or 4 differential (2 parallel test) Resolution 18-bit Sampling rate 8 ksps to 1.024 Msps Waveform memory 4M Max. sinewave frequency 250 kHz Output mode Single-ended, Differential Output range 6 Vpp @600 ohm load (0 to 63 dB attenuation with 0.
Waveform Generators 7 Analog Modules Specification Value Pin counts per module 8 single-ended (4 parallel test) or 4 differential (2 parallet test) Resolution 12-bit Sampling rate 8 ksps to 128 Msps Waveform memory 2M Max. sinewave frequency 32 MHz Output mode Single-ended, Differential Output range 2.5 Vpp @50 ohm load (0 to 63 dB attenuation with 0.01 dB resolution) DC offset range ±2.5 V @50 ohm load to GND 0 V to 5 V @50 ohm load to external termination voltage (2.
7 Analog Modules Waveform Generators Specification Value Pin counts per module 8 single-ended (2 parallel test) or 4 differential (2 parallel test) Resolution 8-bit Sampling rate 50 ksps to 2.6 Gsps Waveform memory 8M Max. sinewave frequency 400 MHz (Normal mode) Output mode Differential pair Output range 2 Vpp@50 ohm (Normal mode) (20 mVpp to 2.0 Vpp with 1 mV resolution) 800 MHz (Direct mode) 1 Vpp@50 ohm (Direct mode) (20 mVpp to 1.0 Vpp with 1 mV resolution) DC offset range ±1.
Waveform Generators 7 Analog Modules Theory of Operation for High Resolution and High Speed AWGs This section describes the theory of operation for AWGs. The following is the block diagram of the high resolution AWG and high speed AWG.
7 Analog Modules Waveform Generators Output Multiplexer The output multiplexer can make the following connections: • Output routes • DC routes • Loop back routes Output Routes To output a single-ended signal or a pair of differential signals from the desired pogo pins, the output multiplexer makes the routes between the output amplifier and the desired pogo pins. The following figure shows possible routes for outputting a single-end signal.
Waveform Generators Pogo Pin 7 Analog Modules Output Multiplexer Output Amp Non-inverse Attenu -ator A+ Filter DAC B+ A- Inverse BAGND Non-inverse C+ D+ C- Inverse D- Offset DAC Start SYNC CLK SYNC DATA Master Clock DGND Timing Generator Stop Sequencer/ Waveform memory awg1-2 Figure 82 Output Routes (Differential) A single-ended signal or a pair of differential signals can be output from multiple pogo pins at the same time.
7 Analog Modules Waveform Generators DC Routes The output multiplexer can make the route between a pogo pin and the SYNC CLK pin. This enables DC measurement by using a Pin PMU on a digital channel connected with the SYNC CLK pin. Hence, if you wire a digital channel with the SYNC CLK pin on the DUT board, you can perform DC measurement at the DUT pin connected to the AWG by using a Pin PMU.
Waveform Generators 7 Analog Modules Pogo Pin Output Multiplexer Output Amp Non-inverse Attenu -ator A+ Filter DAC B+ A- Inverse BAGND Non-inverse C+ D+ C- Inverse D- Offset DAC Start SYNC CLK SYNC DATA Master Clock DGND Timing Generator Stop Sequencer/ Waveform memory awg3 Figure 84 Loop Back Routes The loop back route is designed so that the line impedance becomes 50 ohm exactly.
7 Analog Modules Waveform Generators Attenuator The attenuator adjusts the amplitude of the signal generated by the digital-to-analog converter. Filter The filter is a low pass filter for smoothing the waveforms. This filter removes harmonics from the signal. There are several filters with different cut-off frequencies.
Waveform Generators 7 Analog Modules Sequencer and Waveform Memory The sequencer controls the output sequence of the waveform data stored in the waveform memory. The output sequence of the waveform data is specified in the sequence program that is contained in the sequence memory. The following information can be specified in the sequence program. • Waveform memory area to output waveform signal. • Sequence instruction. The following operations can be specified.
7 Analog Modules Waveform Generators Theory of Operation for Ultra High Speed AWG This section describes the theory of operation for the ultra high speed AWG. The following is the block diagram of the ultra high speed AWG.
Waveform Generators 7 Analog Modules one AWG instrument shown as the upper block in the above figure. For one AWG instrument, the front-end module has four signal output pins, one trigger input pin, and one marker output pin. The front-end module makes the following connections. • Output routes • DC routes • Loop back routes Output Routes To output a single-ended signal or a pair of differential signals, the front-end module makes the route between the desired pogo pins and the AWG instrument outputs.
7 Analog Modules Waveform Generators To output a pair of differential signals, A+ and A-, or B+ and B- can be used for channel 1. For channel 2, C+ and C, or D+ and D- can be used. In the following figure, the routes to output a pair of differential signals are shown with bold lines.
Waveform Generators 7 Analog Modules DC Routes The front-end module can make the route between a pogo pin (including the marker pin) and the trigger input pin. The trigger input pin is the SYNC CLK pin for channel 1 or the SYNC DATA pin for channel 2. This enables DC measurement by using a Pin PMU on a digital channel connected with the trigger input pin.
7 Analog Modules Waveform Generators Loop Back Routes The front-end module can make the loop back route between A+ and B+ and between A- and B- for channel 1. For channel 2, it can make the loop back route between C+ and D+ and between C- and D-. When a loop back route is made, the loop back route is disconnected from other routes. Hence, you can make multiple loop back routes, or make a loop back route and another route (output route or DC route) using other pins at the same time.
Waveform Generators 7 Analog Modules AWG Instrument The AWG instrument is installed in the analog support rack. The AWG instrument consists of the following blocks. • Analog output circuit • Digital-to-analog converter • Clock ocsillator • Sequencer and waveform memory The following sections describe the functions of each block. Analog Output Circuit The analog output circuit has the following circuits.
7 Analog Modules Waveform Generators Clock Oscillator The clock oscillator generates the conversion clock and provides it with the DAC. The master clock of the SOC series is phased-locked with the clock oscillator. Sequencer and Waveform Memory The sequencer controls the output sequence of the waveform data stored in the waveform memory. The output sequence of the waveform data is specified in the sequence program that is contained in the sequence memory.
Waveform Digitizers 7 Analog Modules Waveform Digitizers There are two types of waveform digitizers available as follows: • High Resolution Digitizer (2 MSample/s 16-bit) Code name: WDB • High Speed Digitizer (41 MSample/s 12-bit) Code name: WDA Waveform Digitizer Overview The waveform digitizer can digitize the analog signal output from DUT, then store the digitized waveform data in the waveform memory in real-time.
7 Analog Modules Waveform Digitizers When the digitizer starts, no initial discard points are stored. The digitizer stores the digitized waveform data with the specified number of sample points into the specified waveform memory area, according to the sequence program. The following figure shows the real-time waveform digitizing.
Waveform Digitizers 7 Analog Modules To achieve coherent sampling, the measured signals should be periodic and you need to set the sampling period as follows: Master Clock of Digital Clock Domain I/O Channel Board Clock DUT Phase Lock Analog Out Master Clock of Analog Clock Domain High Speed Digitizer I/O Channel Board Synchronization Trigger t t t t Sample T nt + t (n =2) T T wd_ov2 Figure 91 Coherent Sampling Where, the sampling period (T) is slightly different (∆t) from a multiple of
7 Analog Modules Waveform Digitizers The following tables show the key specifications of the waveform digitizers. Specification Value Pin counts per module 8 single-ended or 4 differential Resolution 16-bit (up to 24-bit with hardware averaging) Sampling rate 8 ksps to 2.048 Msps Waveform capture memory 1M Input mode Single-ended or Differential Input range ±6 V, ±3 V, ±1.5 V, ±0.75 V, ±0.
Waveform Digitizers 7 Analog Modules Specification Value Pin counts per module 8 single-ended or 4 differential Resolution 12-bit Sampling rate 1 Msps to 41 Msps Waveform capture memory 512 k Input mode Single-ended or Differential Input range ±2 V, ±1 V, ±0.5 V, ±0.25 V DC offset range ±4 V Common mode range ±2 V @50 ohm, 37.5 ohm, 10 kohm singleended and 100 ohm, 10 kohm differential (without offset) ±2 V @50 ohm, 37.
7 Analog Modules Waveform Digitizers Theory of Operation This section describes the theory of operation for digitizers. The following is the block diagram of the waveform digitizer. Pogo Pin A+ Input Multiplexer B+ C+ D+ + A- - Input Amp Filter ADC BC- DC offset DAGND Conversion Clock Sequencer/ Timing Waveform Generator Start/ Memory SYNC CLK SYNC DATA DGND End digitizeblock4 Figure 92 Digitizer Block Diagram The waveform digitizer consists of the following blocks.
Waveform Digitizers 7 Analog Modules Input Multiplexer The input multiplexer can make the following connections: • Input routes • DC routes • Loop back routes Input Routes For measuring a single-ended signal, the signal is entered to one of the pogo pins. The input multiplexer connects the pogo pin and input amplifier by closing the internal relays between them.
7 Analog Modules Waveform Digitizers V1 V1 X+ Input Amp R Type ADC R High Speed Digitizer 10 kohm, 50 ohm, 37.
Waveform Digitizers 7 Analog Modules DC Routes The input multiplexer can make the route between a pogo pin and the SYNC CLK pin. This enables DC measurement by using a Pin PMU on a digital channel connected with the SYNC CLK pin. Hence, if you wire a digital channel with the SYNC CLK pin on the DUT board, you can perform DC measurement at the DUT pin connected to a digitizer by using a Pin PMU.
7 Analog Modules Waveform Digitizers Loop Back Routes The input multiplexer can make the loop back route between any pogo pins (except for SYNC CLK and SYNC DATA pins). When the loop back route is made, the input amplifier is disconnected from the input multiplexer. In the following figure, the possible loop back routes are represented with bold lines.
Waveform Digitizers 7 Analog Modules lution digitizer for another test item for the Aout pin. When K1 and K3 are closed and K2 is open, the signal from the Aout pin can be measured by the high speed digitizer. When K1, K2, K4, and K5 are closed and K3 is open, the signal from the Aout pin can be measured by the high resolution digitizer.
7 Analog Modules Waveform Digitizers Input Amplifier The input amplifier determines the input voltage range. Any input voltage ranges are normalized to a certain voltage range at the output of the input amplifier. If the signal to be measured includes a DC component and you want to measure only AC components, you can eliminate the DC component by setting the DC offset voltage. The input amplifier eliminates the DC component according to your setting for the DC offset voltage.
Waveform Digitizers 7 Analog Modules Sequencer and Waveform Memory The sequencer controls storage of digitized data into the waveform memory. The conditions for storing digitized data are specified in the sequence program that is contained in the sequence memory. The following conditions can be specified in the sequence program.
7 Analog Modules Sampler Sampler There is one type of sampler available as follows: • Dual High Speed Sampler (1 GHz 12-bit) Code name: SPA Sampler Overview The sampler is a special module in the waveform digitizers. The sampler can capture very high frequency analog signals that cannot be measured by general waveform digitizers described in the previous section. The sampler can record periodic signals only.
Sampler 7 Analog Modules In the sampler, the sampling period (T) is slightly different (∆t) from a multiple of the signal period (t), that is, T=nt+∆t. (∆t is called the equivalent sampling period.) This under-sampling technique is called Coherent Sampling. The sampling is performed for each of the specified phase points on the measured signal, then repeated and averaged for each phase point. To obtain a very short equivalent sampling period (∆t), the sampling period (T) must be freely set.
7 Analog Modules Sampler You can observe or analyze the captured waveform data with the software interface, Mixed-Signal Tool. NOTE The dual high speed sampler can upload previously measured data during the next measurement. It is designed to “capture” and “upload” different data at the same time. By using this feature, you can maximize throughput of data uploading. The following table shows the key specifications of the sampler.
Sampler 7 Analog Modules Theory of Operation This section describes the theory of operation for a sampler. The following is the block diagram of the sampler.
7 Analog Modules Sampler waveform memory are shared between two channels. The SYNC CLK and SYNC DATA pins are also shared between two channels. You can use one channel only or two channels simultaneously. The following sections describe function of each block. Input Multiplexer The input multiplexer makes the following connections.
Sampler 7 Analog Modules DC Routes The input multiplexer can make the route between a pogo pin and the SYNC CLK pin. This enables DC measurement by using a Pin PMU on a digital channel connected with the SYNC CLK pin. Hence, if you wire a digital channel with the SYNC CLK pin on the DUT board, you can perform DC measurement at the DUT pin connected to a sampler by using a Pin PMU. The following figure shows the possible routes between the pogo pins and SYNC CLK pin, which are represented with bold lines.
7 Analog Modules Sampler Loop Back Routes The input multiplexer can make the loop back route between adjacent pogo pins (A+ and B+, or C+ and D+). When a loop back route is made, the loop back route is disconnected from other routes. Hence, you can make multiple loop back routes, or also make a loop back route and another route (output route or DC route) using other pins at the same time. In the following figure, the possible loop back routes are represented with bold lines.
Sampler 7 Analog Modules Sampler Unit The sampler unit periodically samples the high speed input signal and holds it until the analog-to-digital converter converts it into digital data. The sampling period is set to a multiple of the input signal plus a small amount of time. Thus, the frequency of the input signal is converted to one that is low enough to enable the analogto-digital converter to convert the level of the input signal into digital data.
7 Analog Modules Sampler The timing generator contains the delay counter and delay vernier. By using them, the timing generator controls the delay time from when the trigger signal arrives to when waveform measurement starts. When you use two channels simultaneously, the sampling period, start timing, and stop timing of measurement are the same for the two channels because the timing generator and trigger input pins are shared.
Time Interval Analyzer 7 Analog Modules Time Interval Analyzer There is one type of TIA available as follows: • High performance TIA Code name: TIA • General purpose TIA Code name: TIA These TIAs provide the same functions. Some specifications are different between these TIAs. For specifications, see Table 42 and Table 43. TIA Overview The Time Interval Analyzer (TIA) performs time measurements for digital or analog signals, and stores the results.
7 Analog Modules Time Interval Analyzer Single Channel Period (PER) = 1/Frequency (FREQ) Pulse Width (PW-) CH 1 Pulse Width (PW+) Dual Channel Propagation DelayPD-+ PD+- PD++ PD-- CH 1 Start Channel CH 2 Stop Channel tia_ov1 Figure 101 TIA Measurement Functions The TIA can measure intervals with the specified numbers of samples and store them into the local memory, then return the following data calculated from the raw sampled data as the measurement results: • Maximum value • Minimum value • Jit
Time Interval Analyzer 7 Analog Modules • Period/Frequency Measurement This mode is used to measure the period or frequency of a periodic signal. Trigger TrigDelayCntStart(1) 1 2 3 4 5 6 TrigDelayCntStop(5) Signal The TIA measures this interval, then divides the measured interval by 4 (5-1) to get averaged period/frequency.
7 Analog Modules Time Interval Analyzer • Pulse Width Measurement This mode is used to measure the negative or positive pulse width of a signal. PW+(PW ) Trigger TrigDelayCntStart(1) 1 1 TrigDelayCntStop(1) 2 2 3 3 Signal The TIA measures this interval. Figure 103 TrigDelayCnt Parameters for Pulse Width Measurement For PW+ or PW-, after the trigger is detected, the TIA counts rising edges and falling edges, respectively.
Time Interval Analyzer 7 Analog Modules • Propagation Delay Measurement This mode is used to measure the time difference between edges of two input channels: PD++ (PD +, PD+ ,PD ) Trigger TrigDelayCntStart(1) Start Channel Signal 1 2 1 3 2 TrigDelayCntStop Stop Channel Signal The TIA measures this interval.
7 Analog Modules Time Interval Analyzer • Auto Trigger mode This mode uses the edge of the input signal to channel 1 or 2 as the trigger, as follows: – ARM on Start: The TIA starts the interval measurements from the next pulse after the specified edge of the channel 1 input signal is detected as a trigger. For the dual channel measurement, the TIA measures the interval from the specified edge on channel 1 to the specified edge on channel 2.
Time Interval Analyzer 7 Analog Modules detection on channel 1, the edges on channel 2 are ignored. Thus, the measurement data is always a positive value. This is available for PD measurements. • External Trigger mode This mode uses the edge of the external trigger as the arming trigger. The TIA starts the interval measurements from the next pulse after the specified edge of the external trigger is detected as an arm. This mode is available for any measurement.
7 Analog Modules Time Interval Analyzer For a periodic signal, the jitter test has to measure multiple periods that are not averaged. To perform a single period measurement multiple times for EXT(External) trigger mode, the number of measurement times must be set to points and the trigger for each measurement must be specified. In this case, after a measurement is done, the trigger for the next measurement must be set at 30 µs or later.
Time Interval Analyzer 7 Analog Modules The following example shows the relationship of TrigDelayCntStart, TrigDelayCntStop, and points for EXT trigger mode: 30 µs or more 30 µs or more points(3) Trigger 1 2 3 Signal TrigDelayCntStart(1) TrigDelayCntStop(2) 1 2 For 1st trigger 1 2 1 For 2nd trigger 2 For 3rd trigger Figure 107 Measuring Multiple Intervals In the above example, TrigDelayCntStart(1) and TrigDelayCntStop(2) specify one cycle of the waveform to measure the non-averaged period a
7 Analog Modules Time Interval Analyzer Specification Value Max. input frequency 960 MHz (Signal input 50 ohm) (Characteristics) Input voltage range Signal input Trigger (arming) input Threshold voltage (Vth) range Number of threshold per pin Resolution -3 V to +7 V -1.5 V to +2.
Time Interval Analyzer 7 Analog Modules The following tables show the key specifications of the General Purpose TIA. Specification Value Pin counts per front-end module 7 input pins (with signal loopback) 2 trigger pins Number of triggers input 1 input to each TIA instrument Number of channels per TIA instrument 2 channels Max.
7 Analog Modules Time Interval Analyzer Specification Value Resolution 0.8 ps @single-shot Trigger functions Arm on Stop, Arm on Start, Arm Start First Table 43 General Purpose TIA Key Specifications Theory of Operation This section describes the theory of operation for the TIA. The following is simplified block diagram of the TIA.
Time Interval Analyzer 7 Analog Modules The front-end module has seven signal input pins and two trigger input pins. The 7x4 multiplexer inside the frontend module routes one or two input pins among seven input pins to the input channels (CH1 and CH2) of each TIA instrument. The TIA instrument performs the time interval measurement for the signals entered to CH1 and CH2 of the TIA. The trigger input pin is routed to each TIA instrument to send the arming trigger signal.
7 Analog Modules Time Interval Analyzer The front-end module consists of the following three kinds of blocks: • Input block • Center block • Output block The following sections describe the functions of each block. Input Block In the front-end module, there are seven input blocks. One input block corresponds to one input pin. There is one trigger input block for two trigger pins. The grounds of the input blocks are separated from each other.
Time Interval Analyzer 7 Analog Modules • Determines the input impedance. You can select 10 kohm or 50 ohm as the input impedance. For 50 ohm, you can specify the termination voltage. • Makes the DC routes. The specified input pin is connected to the specified trigger pin. Hence, you can perform DC measurement at the input pin by using the Pin PMU if you wire the digital channel to the trigger pin on the DUT board. When the DC route is made, the DC route is disconnected from other routes.
7 Analog Modules Time Interval Analyzer • Routes one or two input pins among seven input pins to the TIA instrument. For single channel measruement (PW, PER, FREQ), only CH1 is routed to a pin. CH2 is only routed to a pin for dual channel measruement (PD). If two TIA instruments are connected with the frontend module, the center block can route one or two input pins to one TIA instrument and another one or two input pins to the other TIA instrument.
Time Interval Analyzer 7 Analog Modules Channel 1 Start path Time Measurement Block Channel 2 Stop path Trigger TIA Figure 111 TIA Instrument Block Diagram The TIA instrument has two signal inputs and one trigger input. Each signal input can be routed to the internal paths for the start and stop signals. This enables events such as pulse width or pulse period to be measured on a single input with one channel only. Two signal inputs must be used for measuring propagation delay.
7 Analog Modules Synchronization Synchronization This section provides the following information for synchronizing between the digital channel operation and the analog module operation (except for TIA): • Synchronization concepts • Technical data of the synchronization trigger • How to adjust the synchronization timing • How to remove the synchronization uncertainty that occurs in the high speed analog modules • Special synchronization function for high speed AWGs and dual high speed samplers Synchroniza
Synchronization 7 Analog Modules Analog Module Trigger-toSignal Delay Accuracy Uncertainty High Resolution AWG 1000 ns ±250 ns ±1 master clock period High Speed AWG 200 ns ±1 ns 0 to ±1 master clock period Ultra High Speed AWG 110 ns ±(450 ps + OTA) ± 1 sampling clock High Resolution Digitizer 0 ns ±500 ns ±1 master clock period High Speed Digitizer 50 ns ±1 master clock period 0 to ±1 master clock period ±1 ns 0 to ±1 master clock period Dual High Speed Sam- 70 ns pler Table 44
7 Analog Modules Synchronization Receive timing Trigger signal @trigger input pin of analog module Trigger-to-signal delay Accuracy range 1 master clock period Uncertainty (±1 master clock period) Analog module’s start timing @Analog module pin Analog module starts from any point in this period.
Synchronization 7 Analog Modules Trigger Line Length and Signal In addition, there are two kinds of signal delay that are Line Length caused by your wiring on a DUT board. One is the delay caused by the electrical length of the trigger line between the digital pin that provides the trigger signal and the trigger input pin of the analog module; the other is the delay caused by the electrical length of the signal line between the analog module’s output/input pin and the DUT input/output pin.
7 Analog Modules Synchronization Trigger signal @digital pin Trigger line length Trigger signal @trigger input pin of analog module Trigger-to-signal delay Measurement start @Analog module pin Signal line length Analog signal @Analog module pin Analog signal @DUT pin Figure 114 Timing Chart and Delay Factor The above timing chart is an example of analog measurement.
Synchronization 7 Analog Modules to consider only trigger-to-signal delay. For the second level, your application needs to consider trigger-to-signal delay, trigger line length, and signal line length. For the third level, your application uses some high speed analog modules, and needs more detailed synchronization that takes account of the synchronization uncertainty.
7 Analog Modules Synchronization Synchronization Trigger The analog module has two pins dedicated for trigger input. One is the SYNC CLK (Synchronization Clock) pin. The other is the SYNC DATA (Synchronization Data) pin. The SYNC DATA pin is for future enhancements. To provide a path for sending a trigger signal, connect the SYNC CLK pin to a digital channel that sends a trigger signal over one wire on the DUT board. The pulse width of the trigger signal must be greater than or equal to 8 ns.
Synchronization 7 Analog Modules Adjusting Synchronization Timing Considering Trigger-to-Signal Delay Only If the trigger line delay and the signal line delay are quite smaller than the trigger-to-signal delay, you can ignore trigger line length and signal line length. Suppose you are using a digitizer to measure an analog signal from a DUT. You have to program the edge location of the trigger signal before the timing when the analog signal is output from the DUT by the trigger-to-signal delay.
7 Analog Modules Synchronization Considering Trigger-to-Signal Delay, Trigger Line, and Signal Line If you cannot ignore any delay factors in your application, you have to consider all of the following three factors: • Trigger-to-signal delay of analog module • Electric length of trigger line between digital pin and trigger input pin of analog module • Electric length of signal line between analog module pin and DUT pin For easy understanding, this section explains how to adjust timing of synchronization
Synchronization 7 Analog Modules Adjusting Timing at Pogo Pin of Analog Module The following is the timing chart for measuring an analog signal from the DUT by using a digitizer. The pogo pin of the analog module is the reference point for considering timing adjustment. For the DUT, you have to stimulate it so that its analog signal can arrive at the pogo pin of the analog module at the desired measurement timing.
7 Analog Modules Synchronization Adjusting Timing at DUT Pin Assuming the DUT pin as the reference point of timing, you have to compensate the signal line length, which is between the DUT pin and pogo pin of the analog module, when you program the edge location of the trigger signal. For the AWG, you have to move the trigger signal edge backward by the trigger line length plus the trigger-tosignal delay plus the signal line length from the reference point.
Synchronization 7 Analog Modules For a digitizer or sampler, you have to move the trigger signal edge backward by the trigger line length plus the trigger-to-signal delay from the reference point, then move it forward by the signal line length. As a result, the digitizer can start the measurement at the moment when the analog signal arrives at the analog module pin.
7 Analog Modules Synchronization Synchronization Uncertainty For high speed mixed-signal applications, the key is to decrease uncertainty with the timing system in the analog modules. The uncertainty arises from the relationship between phases of the trigger signal applied to analog modules and the master clock used for trigger signals and analog modules. Hence, uncertainty is also associated with your trigger line length on the DUT board.
Synchronization 7 Analog Modules The following describes the details of how to remove the synchronization uncertainty when using same master clock for a trigger source and an analog module. You can do either of the following to remove uncertainty that occurs in the trigger-to-signal delay of the analog module. NOTE You can add the specified delay time value to the triggerto-signal delay for each analog module. It is useful to adjust the edge location of the trigger signal to the desired position.
7 Analog Modules Synchronization Beginning of Tester Period TRGL = Trigger line length Tester period Tester period Trigger edge setting Trigger @digital pin Trigger line length Trigger @trigger input pin of analog module Trigger-to-signal delay Analog signal measurement @analog module pogo pin TRGL Figure 120 Trigger Signal Edge Placement when TRGL Is Set to Trigger Line Length m • Program the edge location of the trigger signal before the beginning of the tester period by the trigger line length.
Synchronization 7 Analog Modules TRGL = 0 Beginning of Tester Period Tester period Tester period Trigger edge setting Trigger @digital pin Trigger line length Trigger @trigger input pin of analog module Trigger-to-signal delay Analog signal measurement @analog module pogo pin ase2 Figure 121 Trigger Signal Edge Placement when TRGL Is Set to Zero In addition, to compensate the signal line length, which is between the analog pogo pin and DUT pin, you may want to move the edge location of the trigger s
7 Analog Modules Synchronization The following timing chart is for when the value of TRGL is set to the trigger line length.
Synchronization 7 Analog Modules The following timing chart is for when the TRGL value is set to zero.
7 Analog Modules Synchronization Master Trigger Function When performing tests using multiple channels of high speed analog modules simultaneously, it is important to remove uncertainty between channels as much as possible. When you use different master clock sources for digital channels and analog modules, uncertainty happens not only between the digital channels as the trigger source and analog modules, but also between analog modules.
Synchronization 7 Analog Modules A Card Cage in Testhead Trigger input pin Analog module pin Vernier FF Trigger input pin Analog module pin Vernier ADC Timing FF Trigger input pin Analog module pin Vernier ADC Timing Counter Generator Counter Generator Analog Module Analog Module FF ADC Counter Timing Generator Analog Module "Master-Slave" Internal Connection (Loop) Greater Slot Number Smaller Slot Number Analog Module: High Speed AWG Figure 124 “Master-Slave” Internal Connecti
7 Analog Modules Synchronization A Card Cage in Testhead Analog Module (Master) Analog Module (Slave) Analog Module (Master) Analog Module (Master) Analog Module (Slave) Analog Module (Slave) Analog Module (Slave) Analog Module (Master) Analog Module (Slave) Analog Module (Slave) Analog Module (Master) Analog Module (Master) masterslave2 Figure 125 Examples of Definition of Master/Slave Modules One master module can support up to seven slave modules.
Synchronization 7 Analog Modules control the trigger-to-signal delay for the master and slaves to the same time. Hence, uncertainty between analog modules is eliminated even if you use different master clocks for digital channels and analog modules. Note that uncertainty in the trigger-to-signal delay between a digital channel and analog modules remains regardless of the use of the master trigger function. The following figure is the block diagram for when the master trigger function is used.
7 Analog Modules 264 Synchronization System Reference, January 2001
Appendices Test Setup, January 2001 265
Test Setup, January 2001
A A XICOR EEPROM Summary On the next page you find the XICOR X24C04 EEPROM summary supplied by XICOR. This same summary is also accessible via the XICOR web-address: www.xicor.
Recommended System Management Alternative: X4043 X24C04 4K 512 x 8 Bit Serial EEPROM DESCRIPTION • 2.7V to 5.5V power supply versions • Low power CMOS —Active read current less than 1 mA —Active write current less than 1.
X24C04 PIN DESCRIPTIONS PIN CONFIGURATION Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. SOIC 8 1 N FO OT R RE N C EW O M D M ES EN IG D N ED S A0 Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor.
X24C04 X24C04 to place the device in the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. N FO OT R RE N C EW O M D M ES EN IG D N ED S Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the Figure 1. Data Validity SCL SDA Data Stable Data Change Figure 2.
X24C04 Figure 3. Acknowledge Response From Receiver SCL From Master 1 8 9 N FO OT R RE N C EW O M D M ES EN IG D N ED S Data Output From Transmitter Data Output From Receiver START Acknowledge DEVICE ADDRESSING Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave are the device type identifier (see Figure 4). For the X24C04 this is fixed as 1010[B]. Figure 4.
X24C04 Figure 5. Byte Write Bus Activity: Master Slave Address Word Address S T O P Data S P N FO OT R RE N C EW O M D M ES EN IG D N ED S SDA Bus S T A R T A C K Bus Activity: X24C04 Page Write The X24C04 is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to fifteen more words.
X24C04 Current Address Read Flow 1. ACK Polling Sequence Internally the X24C04 contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the X24C04 issues an acknowledge and transmits the eight bit word.
X24C04 Figure 8. Random Read Bus Activity: Master S T A R T Word Address n Slave Address S T O P Slave Address N FO OT R RE N C EW O M D M ES EN IG D N ED S SDA Line S T A R T S S A C K Bus Activity: X24C04 A C K A C K Sequential Read Sequential Read can be initiated as either a current address read or random access read. The first word is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data.
X24C04 COMMENT Temperature under bias ........................–65 to +135°C Storage temperature .............................–65 to +150°C Voltage on any pin with respect to VSS .................................. –1.0V to +7.0V D.C. output current .............................................. 5 mA Lead temperature (soldering, 10 Seconds) ........300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
X24C04 A.C. CONDITIONS OF TEST EQUIVALENT A.C. LOAD CIRCUIT Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10 ns Input and output timing levels VCC x 0.5 5.0V N FO OT R RE N C EW O M D M ES EN IG D N ED S 1533Ω Output 100pF A.C. CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Read & Write Cycle Limits Symbol Min. Max.
X24C04 Bus Timing tHIGH tF tLOW tR SCL tHD:DAT tSU:DAT tSU:STO N FO OT R RE N C EW O M D M ES EN IG D N ED S tHD:STA tSU:STA SDA IN tAA tDH tBUF SDA OUT Write Cycle Limits Symbol (6) tWC Parameter Min. Write Cycle Time Typ.(5) Max. Unit 5 10 ms Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V). (6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used.
X24C04 Guidelines for Calculating Typical Values of Bus Pull-Up Resistors SYMBOL TABLE WAVEFORM 120 RMIN = IOL Min. =1.8KΩ INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance Resistance (KΩ) N FO OT R RE N C EW O M D M ES EN IG D N ED S 100 VCC Max. tR 80 RMAX = 60 Max.
X24C04 PACKAGING INFORMATION N FO OT R RE N C EW O M D M ES EN IG D N ED S 8-Lead Plastic Small Outline Gull Wing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0.050"Typical 0.050" Typical 0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) 0.
X24C04 Ordering Information X24C04 X X -X VCC Range 2.7 = 2.7V to 5.5V N FO OT R RE N C EW O M D M ES EN IG D N ED S Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package S8 = 8-Lead SOIC Part Mark Convention 8-Lead SOIC X24C04 XX Blank = 8-Lead SOIC F = 2.7 to 5.5V, 0 to +70°C G = 2.7 to 5.5V, -40 to +85°C LIMITED WARRANTY ©Xicor, Inc. 2000 Patents Pending Devices sold by Xicor, Inc.
Index Index AWG 184 Functions 184 pogo pad assignment 90 Specifications 184 Diagnostics 30 # B digital boards 59 128 pins modules 38 Bidirectional pins 121 50 Ohm impedance 118 C Digitizer 203 A cage numbering 64 AC/DC Converters 28 card cage numbering 64 digitizers pogo pad assignment 91 Active load 122 card cages 59, 60 allocation 63 1024 pin DUT board 65 512 pin DUT board 64 Adjusting synchronization timing 249 Alternative master clock generator 50 Cardcages 38 AMC 50 Channel Boards
Index F groups 63 F330 style DUT board 63 H filling algorithm analog dominant configuration 1024 pin test head 77 512 pin test head 75 digital dominant configuration 1024 pin test head 73 512 pin test head 72 overview 78 half groups 63 Filtering Supply and DC Voltage 127 G Ganging GPDPS Channels 159 General Purpose Power Supply (GPDPS) 136 General Purpose TIA 225 Specifications 235 GPDPS 86, 94, 136 Block Diagram 137 Block Diagram (simplified) 141 Board description 136 Capacitive Load & Performance R
Index M R Manipulator 26 Radio frequency decoupling 154 Master clock 49 Available sources 55 Distribution 51 Radio Frequency Interference Supression 154 Master Clock Generator 43 Reference Voltage Generator 43 S Master trigger function 260 Master-slave internal connection 260 Measuring Voltages and currents 139, 164, 178 Sampler 216 Functions 216 Specifications 216 Series resistor 122 Settling Times, GPDPS Voltage 157 N Shielding for mixed-signal tests 126 Noise Reduction 154 Shutting down 34
Index Voltage clamp 122 Voltage measurement 178 W Warning lamps 33 Waveform Digitizer 203 Functions 203 Specifications 203 Workstation 29 272 System Reference, January 2001
