AW-AM510 IEEE 802.11 1X1 a/b/g/n Wireless LAN + Bluetooth 5.1 Combo 12 x 12 LGA Module Datasheet Rev.
Features WLAN Security: WPA3, WPA2, WPA2 and WPA mix mixed mode, WEP Support 802.11 a/b/g/n Dual bands: 2.4 GHz and 5 GHz Bluetooth Single stream 802.11n with 20 MHz and 40 Full Bluetooth 5.1 features MHz channels Long range - 4x coverage Up to MCS7 data rates (150 Mbps) 2 Mbps data rate - 2x faster Support 802.
Revision History Document NO: R2-2510-DST-01 Revision Version DCN NO. Date A 2020/09/17 DCN018312 Description Draft version 3 Initials Approved Renton Tao N.
Table of Contents Revision History .............................................................................................................................. 3 Table of Contents ............................................................................................................................ 4 1. Introduction ................................................................................................................................. 5 1.1 Product Overview ..................................
1. Introduction 1.1 Product Overview AzureWave Technologies, Inc. introduces the IEEE 802.11a/b/g/n WLAN, BT, combo module – AW-AM510. With four advanced radio technologies integrated into a module, AW-AM510 provides the best and most convenient SMT process.
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1.3 Specifications Table 1.3.1 General Features Description Product Description IEEE 802.11 a/b/g/n Wi-Fi with Bluetooth 5.1 Combo Module Major Chipset NXP IW416 WLCSP Host Interface Wi-Fi: SDIO3.0, BT: SDIO3.0, UART Dimension 12 mm X 12 mm x 2 mm(Max) Package LGA Weight TBD 1.3.2 WLAN Features Description WLAN Standard IEEE802.11 a/b/g/n Frequency Rage 2.4 GHz ISM Bands 2.412-2.472 GHz 5.15-5.25 GHz (FCC UNII-low band) for US/Canada and Europe 5.25-5.
2.4G Min Output Power (Board Level Limit)* 11b (11Mbps) @EVM<35% 11g (54Mbps) @EVM≦-27 dB 11n (HT20 MCS7) @EVM≦-28 dB 11n (HT40 MCS7) @EVM≦-28 dB Typ Max Unit TBD dBm TBD dBm TBD dBm TBD dBm 5G Min 11a (54Mbps) @EVM≦-27 dB 11n (HT20 MCS7) @EVM≦-28 dB 11n (HT40 MCS7) @EVM≦-28 dB Typ Max Unit TBD dBm TBD dBm TBD dBm 2.
1.3.3 Bluetooth Features Description Bluetooth Standard Full Bluetooth 5.1 features Frequency Rage 2402MHz~2483MHz Modulation Header GFSK Payload 2M: π/4-DQPSK Payload 3M: 8DPSK Min Output Power Receiver Sensitivity BDR EDR Low Energy BT Sensitivity (BER<0.1%) Min BDR(DH1) EDR(2DH5) EDR(3DH5) Low Energy - Typ TBD TBD TBD Max Unit dBm dBm dBm Typ TBD TBD TBD TBD Max Unit dBm dBm dBm dBm 1.3.4 Operating Conditions Features Description Operating Conditions Voltage 3.
2. Pin Definition 2.1 Pin Map AW-AM510 pin out drawing (top view).
2.2 Pin Table Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Definition Basic Description GND1 Ground WL_BT_ANT Option for RF I/O pin out GND3 Ground NC4 Floating Pin, No connect to anything. NC5 Floating Pin, No connect to anything. BT_HOST_WAKE GPIO Mode : GPIO[12]. _DEV BT Device Wake BT_DEV_WAKE_ GPIO Mode : GPIO[0]. Host BT Host Wake NC8 Floating Pin, No connect to anything. VDD33 3.
38 GPIO13 39 GPIO14 40 41 42 43 44 NC40 UART_RTS UART_TX UART_RX UART_CTS GPIO Mode : GPIO[13]. Host-to-Wi-Fi reset recovery GPIO Mode : GPIO[14]. Host-to-Chip wakeup Floating Pin, No connect to anything. UART_RTSn (active low) UART_SOUT UART_SIN UART_CTSn(active low) VDDIO I/O VDDIO I/O --VDDIO VDDIO VDDIO VDDIO Floating O O I I 3. Electrical Characteristics 3.1 Absolute Maximum Ratings Symbol Parameter Minimum Typical Maximum Unit VDD33 DC supply for the 3.3V input - 3.3 3.
3.3.2 3.3V Operation (VDDIO) Symbol Parameter Minimum Typical Maximum VIH Input high voltage 0.7*VIO - VIO+0.4 VIL Input low voltage -0.4 - 0.3*VIO VOH Output High Voltage VIO-0.4 - - VOL Output Low Voltage - - 0.
3.4 Host Interface 3.4.1 SDIO Interface The AW-AM510 supports a SDIO device interface that conforms to the industry SDIO Full-Speed card specification and allows a host controller using the SDIO bus protocol to access the Wireless SoC device. The AW-AM510 acts as the device on the SDIO bus. The host unit can access registers of the SDIO interface directly and can access shared memory in the device through the use of BARs and a DMA engine. Support SDIO 3.0 Standard. On-chip memory used for CIS.
3.4.2 SDIO Protocol Timing 3.4.2.1 Default Speed, High-Speed Modes (3.3V) SDIO protocol timing Diagram - Default mode. (3.3V) SDIO protocol timing Diagram - High Speed mode. (3.
3.4.2.2 SDR12, SDR25, SDR50 Modes (up to 100MHz) (1.8V) SDIO Protocol Timing Diagram - SDR12, SDR25, SDR50 Modes (up to 100 MHz)(1.8V) Symbol Parameter Condition Min Typ Max Units Fpp CLK Frequency SDR12/25/50 25 - 100 MHz TCLK Clock Time SDR12/25/50 10 - 40 ns TIS Input Setup Time SDR12/25/50 3 - - ns TIH Input Hold Time Rise time, fail time TCR ,TCF <2ns(max) at 100MHz CCARD =10pF Output Delay Time SDR12/25/50 0.8 - - ns SDR12/25/50 - - 0.
3.4.2.3 DDR50 Mode (50MHz) (1.8V) SDIO CMD Timing Diagram - DDR50 Mode (50 MHz) SDIO DAT[3:0] Timing Diagram - DDR50 Mode1 (50 MHz) 1 In DDR50 mode, DAT[3:0] lines are sampled on both edges of the clock (not applicable for CMD line).
Symbol Clock TCLK TCR, TCF Clock Duty CMD Input TIS TIH CMD Output Condition Min Typ Max Units Clock time Rise time, fall time DDR50 DDR50 DDR50 20 45 - 0.2*TCLK 55 ns Ns % Input setup time Input hold time DDR50 DDR50 6 0.8 - - ns ns DDR50 - - 13.7 ns DDR50 1.5 - - ns DDR50 DDR50 3 0.8 - - ns ns DDR50 - - 7 ns DDR50 1.
3.4.3.High-Speed UART Interface The AW-AM510 supports a high-speed Universal Asynchronous Receiver/Transmitter (UART) interface, compliant to the industry standard 16550 specification. High-speed baud rates are supported to provide the physical transport between the device and the host for exchanging Bluetooth data.
3.4.4 PCM Interface 3.4.4.1 PCM Timing Specification – Master Mode Symbol Parameter Condition Min Typ Max Units FBCLK -- -- -- 2/2.048 -- MHz Duty CycleBCLK -- -- 0.4 0.5 0.
3.4.4.2 PCM Timing Specification – Slave Mode Symbol Parameter Condition Min Typ Max Units FBCLK -- -- -- 2/2.048 -- MHz Duty CycleBCLK -- -- 0.4 0.5 0.
3.5 Timing Sequence AW-AM510 power up timing sequence.
3.6 Power Consumption* 3.6.1 WLAN TBD 3.6.
3.7 Sleep Clock(Optional) An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. External 32.
4. Mechanical Information 4.
5. Packing Information One reel can pack 1,500pcs 12x12 LGA modules 1. One production label is pasted on the reel, one desiccant and one humidity indicator card are put on the reel One desiccant One production label One humidity indicator card 2. One reel is put into the anti-static moisture barrier bag, and then one label is pasted on the bag One production label 3.
4. A bubble wrap is put into the inner box and then one label is pasted on the inner box One production label Production label 5. 5 inner boxes could be put into one carton Production 6.
7. One carton label and one box label are pasted on the carton.
AW-AM510 IEEE 802.11 1X1 a/b/g/n Wireless LAN + Bluetooth 5.1 Combo 12mm x 12mm LGA module Layout Guide Rev.
Revision History Version Revision Date A 2021/02/24 B 2021/05/24 Description Initials Approved Initial Version Roger Liu N.C. Chen Add RF trace layout information Roger Liu N.C.
INTRODUCTION This document provides key guidelines and recommendations to be followed when creating AW-AM510 layout. It is strongly recommended that layouts be reviewed by the AzureWave engineering team before being released for fabrication. The following is a summary of the major items that are covered in detail in this application note. Each of these areas of the layout should be carefully reviewed against the provided recommendations before the PCB goes to fabrication.
1. GENERAL RF GUIDELINES Follow these steps for optimal WLAN performance. 1. Control WLAN 50 ohm RF traces by doing the following: • Route traces on the top layer as much as possible and use a continuous reference ground plane underneath them. • Verify trace distance from ground flooding. At a minimum, there should be a gap equal to the width of one trace between the trace and ground flooding. Also keep RF signal lines away from metal shields.
2. Ground Layout Please follow general ground layout guidelines. Here are some general rules for customers’ reference. • The layer 2 of PCB should be a complete ground plane. The rule has to be obeyed strictly in the RF section while RF traces are on the top layer. • Each ground pad of components on top layer should have via drilled to PCB layer 2 and via should be as close to pad as possible. A bulk decoupling capacitor needs two or more.
• The CPW (coplanar waveguide) design and the microstrip line are both recommended; the customers can choose either one depending on the PCB stack of their products. • The RF trace must be isolated with aground beneath it. Other signal traces should be isolated from the RF trace either by ground plane or ground vias to avoid coupling. • To minimize the parasitic capacitance related to the corner of the RF trace, the right angle corner is not recommended.
AW-AM510 RF trace should be follow the rules as below a. Line length of Antenna trace about 88.7mi and 68.5 mil b. Line width of Antenna trace about 10 mil c. Air gap between RF trace and ground about 4.
6. Antenna All the high-speed traces should be moved far away from the antenna. For the best radiation performance, check antenna chip vendor for the layout guideline and clearance.
7. Antenna Matching PCB designer should reserve an antenna matching network for post tuning to ensure the antenna performance in different environments. Matching components should be close to each other. Stubs should also be avoided to reduce parasitic while no shunt component is necessary after tuning. 8. SHIELDING CASE Magnetic shielding, ferrite drum shielding, or magnetic-resin coated shielding is highly recommended to prevent EMI issues.
9. GENERAL LAYOUT GUIDELINES Follow these guidelines to obtain good signal integrity and avoid EMI: 1. Place components and route signals using the following design practices: • Keep analog and digital circuits in separate areas. • Identify all high-bandwidth signals and their return paths. Treat all critical signals as current loops. Check each critical loop area before the board is built. A small loop area is more important than short trace lengths.
10. Stamp Module stencil and Pad opening Suggestion Stencil thickness：0.10~0.12mm Function Pad opening size suggestion: Max. 1:1 PS: This opening suggestion just for customer reference, please discuss with AzureWave’s Engineer before you start SMT. Solder Printer Opening and Customer PCB Footprint suggestion.
11. The other layout guide Information • Make sure every power traces have good return path (ground path). • Connect the input pins of unused internal regulators to ground. • Leave the output pins of unused internal regulators floating. • High speed interface (i.e. UART/SDIO/HSIC) shall have equal electrical length. Keep them away from noise sensitive blocks. • Good power integrity of VDDIO will improve the signal integrity of digital interfaces.
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•Bottom View of PCB Layout Foot Print 14
Federal Communication Commission Interference Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
used. 20cm minimum distance has to be able to be maintained between the antenna and the users for the host this module is integrated into. Under such configuration, the FCC radiation exposure limits set forth for an population/uncontrolled environment can be satisfied. Any changes or modifications not expressly approved by the manufacturer could void the user's authority to operate this equipment.
This device contains licence-exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic Development Canada’s licence-exempt RSS(s). Operation is subject to the following two conditions: (1) This device may not cause interference. (2) This device must accept any interference, including interference that may cause undesired operation of the device.
The maximum antenna gain permitted for devices in the bands 5250-5350 MHz and 5470-5725 MHz shall be such that the equipment still complies with the e.i.r.p. limit. le gain maximal d’antenne permis pour les dispositifs utilisant les bandes 5250-5350 MHz et 5470-5725 MHz doit se conformer à la limite de p.i.r.e. The maximum antenna gain permitted for devices in the band 5725-5850 MHz shall be such that the equipment still complies with the e.i.r.p.
This module is intended for OEM integrator. The OEM integrator is responsible for the compliance to all the rules that apply to the product into which this certified RF module is integrated. Additional testing and certification may be necessary when multiple modules are used. 20cm minimum distance has to be able to be maintained between the antenna and the users for the host this module is integrated into.
Note1: Ant. WLAN 2.4GHz Antenna Gain (dBi) WLAN 5GHz Bluetooth 1 3.20 4.25 3.20 2 2.98 5.16 2.98 3 2.90 4.30 2.
