User's Manual

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2-3.Clock Specifications
2-3-1 External Sleep Clock Timing
External Sleep Clock is necessary for two reasons:
1. Auto frequency Detection.
This is where the internal logic will bin the Ref clock source to figure out what is the reference clock
frequency is. This is done so no strapping is needed for telling 8887 what the ref clock input is.
2. Allow low current modes for BT to enter sleep modes such as sniff modes.
The AW-CM286NF external sleep clock pin is powered from the 1.8V voltage supply.
Symbol
Parameter
Min
Typ
Max
Units
CLK
Clock Frequency Range
32 or 32.768 -50ppm
32 or 32.768
32 or 32.768 +50ppm
KHz
T
HIGH
Clock high time
40
--
--
ns
T
LOW
Clock low time
40
--
--
ns
T
RISE
Clock rise time
--
--
5
ns
T
FALL
Clock fall time
--
--
5
ns
2-4. Reset Configuration
The AW-CM286NF is reset to its default operating state under the following conditions:
 Power-on reset (POR)
 Software/Firmware reset
 External pin reset (RESETn)
2-4-1. Internal Reset
The AW-CM286NF device is reset, and the internal CPU begins the boot sequence when any of the following
internal reset events occur:
 Device receives power and VDDL supplies rise (triggers internal POR circuit)
 External pin (PDn) assertion will generate POR
2-4-2. External Reset
The AW-CM286NF is reset when PDn pin is asserted low and the internal CPU begins the boot sequence when
the PDn pin transitions from low to high.