Data Sheet

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peripheral. Data is written from a master (CPU) over the APB bus to the UART and it is converted to
serial form and transmitted to the destination device. Serial data is also received by the UART and
stored for the master (CPU) to read back.
There is also DMA support on the UART block thus the internal FIFOs can be used. Both UARTs
support hardware flow control signals (RTS, CTS). Features
● 16 bytes Transmit and receive FIFOs
● Hardware flow control support (CTS/RTS)
● Shadow registers to reduce software overhead and also include a software programmable reset
● Transmitter Holding Register Empty (THRE) interrupt mode
● IrDA 1.0 SIR mode supporting low power mode.
● Functionality based on the 16550 industry standard:
● Programmable character properties, such as number of data bits per character (5-8), optional
● parity bit (with odd or even select) and number of stop bits (1, 1.5 or 2)
● Line break generation and detection
● Prioritized interrupt identification
● Programmable serial data baud rate as calculated by the following: baud rate = (serial clock
frequency)/(16 * divisor).
3.8. SPI+ interface
This interface supports a subset of the Serial Peripheral Interface (SPI™). The serial interface can
transmit and receive 8, 16 or 32 bits in master/slave mode and transmit 9 bits in master mode. The
SPI+ interface has enhanced functionality with bidirectional 2x16-bit word FIFOs. SPI is a trademark
of Motorola, Inc.
Features
● Slave and Master mode
● 8 bit, 9 bit, 16 bit or 32 bit operation
● Clock speeds up to 16 MHz for the SPI controller. Programmable output frequencies of SPI
source clock divided by 1, 2, 4, 8
● SPI clock line speed up to 8 MHz
● SPI mode 0, 1, 2, 3 support (clock edge and phase)
● Programmable SPI_DO idle level
● Maskable Interrupt generation
● Bus load reduction by unidirectional writes-only and reads-only modes.
● Built-in RX/TX FIFOs for continuous SPI bursts.