Data Sheet

25
FORM NO.: FR2-015_ A Responsible Department：WBU Expiry Date: Forever
The information contained herein is the exclusive property of AzureWave and shall not be distributed, reproduced, or
disclosed in whole or in part without prior written permission of AzureWave.
SDIO SAT [3:0] Timing Diagram – SDR50 Mode (50MHz)
SDIO Timing Data- DDR50 Mode (50MHz)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Clock
T
CLK
Clock time
DDR50
20
-
-
ns
T
CR
, T
CF
Rise time, fall time
DDR50
-
-
0.2*T
CLK
Ns
Clock Duty
DDR50
45
-
55
%
CMD Input
T
IS
Input setup time
DDR50
6
-
-
ns
T
IH
Input hold time
DDR50
0.8
-
-
ns
CMD Output
T
ODLY
Output delay time during
data transfer mode
DDR50
-
-
13.7
ns
T
OHLD
Output hold time
DDR50
1.5
-
-
ns
DAT [3:0] Input
T
IS2X
Input hold time
DDR50
3
-
-
ns
T
IH2X
Input hold time
DDR50
0.8
-
-
ns
DAT [3:0] Output
T
ODLY2X(max)
Output delay time during
data transfer mode
DDR50
-
-
7
ns
T
ODLY2X(min)
Output hold time
DDR50
1.5
-
-
ns