0623 Roselle Street, San Diego, CA 92121 • (858) 550-9559 • FAX (858) 550-7322 contactus@accesio.com • www.accesio.com MODEL P104-WDG-CSM PC/104-PLUS WATCHDOG TIMER USER MANUAL FILE: MP104-WDG-CSM.
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TABLE OF CONTENTS Chapter 1: Introduction ..................................................................................................................... 5 Watchdog .......................................................................................................................................... 5 Figure 1-1: Block Diagram ........................................................................................................ 6 Watchdog Models ...................................................
Chapter 1: Introduction This multifunction card contains a watchdog timer. Additionally, two additional models with multiple features may be included on your card. Example of these are: a computer power supply monitor, a computer internal temperature monitor, capability to read the temperature, a pair of opto-isolated inputs and outputs and a fan-speed control. Watchdog Your application program must communicate with the watchdog circuit at prescribed intervals.
The Watchdog card can generate an interrupt request one Counter 0 period-width before the reset timeout. For example, if a reset period of 60 seconds is used with a 5 millisecond delay stored in Counter 0 (the result of a maximum value delay), an interrupt would occur at 59.995 seconds. This gives the Interrupt handler software 5 milliseconds to refresh the watchdog before a reset action occurs.
P104-WDG-CSM: Standard Watchdog with Computer Status Monitor This model provides a fully programmable watchdog with open collector outputs that can reset the computer. It also contains various I/O to monitor and control the health of the computer. It contains computer power monitoring, computer temperature monitoring and measurement, isolated inputs and isolated outputs. (See Chapter 5 for 40-pin connector information.) The following I/O connections are provided: a.
P104-WDG-CSMA: Standard Watchdog with Advanced Computer Status Monitor This model provides a fully programmable watchdog with open collector outputs that can reset the computer. It contains all available I/O to monitor and control the health of the computer.
Additional Fused External Power Pin 38 has a 0.3A (300mA) (at room temperature) resettable fuse connected to +5V. At +85C this fuse trips at 0.15A (150mA), at 0 degrees C this fuse trips at 0.6A (600mA). The same is true for the fuse connected to pin 40 (12VDC). Special Options Programmable array logic is available on this card and many possibilities exist for special modifications to suit unique requirements. If your card includes any such modifications, an "S" number (e.g. S08, S09, etc.
Chapter 2: Installation A printed Quick-Start Guide (QSG) is packed with the board for your convenience. If you’ve already performed the steps from the QSG, you may find this chapter to be redundant and may skip forward to begin developing your application. The software provided with this PC/104-Plus board is on CD and must be installed onto your hard disk prior to use. To do this, perform the following steps as appropriate for your operating system.
Hardware Installation Before installing the board, please run Setup.exe. The Setup program can be used to assist in configuring the two switches on the board. Our setup program will lead the user through the process of setting the options on the board (the program does not set the options on the board). The PCI bus clock trace length from the CPU to the cards in the stack is tuned so that the clock edge arrives at the interface when data is valid.
Figure 2-1: Fan Connection Diagram 12 P104-WDG-CSM User Manual
Chapter 3: Address Selection The Watchdog Timer uses one PCI address space, occupying 16 consecutive register locations. PCI architecture is Plug-and-Play. This means that the BIOS or Operating System determines the resources assigned to PCI cards rather than you selecting those resources with switches or jumpers. As a result, you cannot set or change the card's base address. You can only determine what the system has assigned.
Chapter 4: Programming This section of the manual contains information to assist you in developing programs for use with the card. I/O bus address assignments, programming hints, and a description of the utility driver are included.
82c54 Registers (BASE +0 thru +3) See Appendix A of this manual. Status Register (BASE+4) Bit assignments of the Status Register are as follows: BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 Watchdog counter refresh reminder (active low) Temperature good (active low) Reset Isolated Input #2 status Isolated Input #1 status Fan good Power Supply overvoltage (active low) Power Supply undervoltage (active low) IRQ generated (active high) Interrupts will be enabled AFTER this register is READ.
A/DC Channel #3 (BASE+B) Read 8-bit dedicated analog input (light sensor). Dark = FF, Max Light = 00 82c54 Out 2 (BASE+C) Read this address to select the 16MHz clock rate, write to select 2MHz. This determines the width of the watchdog reset output when not connected to the motherboard reset input. TTL & Isolated Output (BASE+D) Write (any value) to turn on isolated (transistor) output #1 and LED1 sink. Read to turn off (default state).
To Program the Watchdog Interval 1. 2. 3. 4. Disable the counters. Program the counter modes Program the desired time delays. Enable the counters. Once the counters have been enabled, the computer will reset if the 32-bit counter (counters 0 and 1) decrements all the way to zero. (Note: An alternative use of the reset signal is to simply notify an external device that a reset is necessary.
4. 5. Load CTR0,1,2 with reset delay Enable Watchdog Then, before the first timeout occurs: 1. Enter main loop 2. Program CTR1 (again) for Mode 2 3. Load CTR1 4. User code goes here 5.
Background Watchdog Mode An alternative method to refresh the counters that provides some flexibility but potentially reduces dependability is to use an interrupt service routine (ISR). The card will generate an interrupt one Counter 0 load value before timeout occurs. If that interrupt is used by a userdefined ISR, it's possible for that ISR to refresh the counters and, thus, avoid need for the main program loop to refresh the counters.
Chapter 5: Connector Pin Assignments One 40-pin right-angle shrouded 2x20 header connector with 0.1” spacing provides access to the I/O signals. The standard mating connector is a Molex “crimp and poke” discrete wire type with a latching feature. Other mating connectors and/or cables may be used.
Chapter 6: Specification Watchdog Timer • Time-out: Software selectable from 2 μsec. to 2060 sec • Pulse Width: Output, 120 nsec. Minimum, 31 msec. Maximum • Clock: 2.08333 MHz, derived from computer clock (33 MHz÷16) • Address: 8-Bit I/O Mapped Status Monitor Register • Voltages IRQ and register indication if +5, +12, or -12 varies by more than +/-6% • Temp. Alarm: IRQ and status register indication when above ~ 122°F (50°C) • Temp. Digitizer: 8 bit ADC, LSB = 0.7 °F (0.
Appendix A: Programmable Interval Timer This Appendix includes basic information about the type 8254 Counter/Timer chip. For those interested in more detailed information, a full description can be found in the manufacturer's data sheets. Please note: The information in this Appendix is for general reference, and may include features or functions not applicable to this card.
Mode 5: Hardware Triggered Strobe In this mode, the counter will start counting after the rising edge of the trigger input and will go low for one clock period when the terminal count is reached. The counter is retriggerable. The output will go low until the full count after the rising edge of the trigger.
Reading and Loading the Counters If you attempt to read the counters on the fly when there is a high frequency input, you will most likely get erroneous data. This is partly caused by "carries" rippling through the counter during the read operation. Also, the low and high bytes are read sequentially rather than simultaneously and, thus, it's possible that "carries" will be propagated from the low byte to the high byte during the read cycle.
OUT: Current state of counter output pin. NC: Null count. this indicates when the last count loaded into the counter register has actually been loaded into the counter itself. The exact time of load depends on the configuration selected. Until the count is loaded into the counter itself, it cannot be read. RW0 and RW1: M0-M2: BCD: Read/Write command. Counter mode. BCD=0 sets binary mode, otherwise counter is in BCD mode.
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