Intel® SRMK2 Internet Server Technical Product Specification February 26, 2001 iPN A39185-001 The Intel ® SRMK2 Internet Server may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in the Intel® SRMK2 Internet Server Specification Update.
Revision History Revision Revision History Date 1.0 Original draft October 18, 2000 1.1 First update January 25, 2001 1.2 Second update February 26, 2001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Preface This Technical Product Specification (TPS) identifies components and software integrated with the Intel® SRMK2 Internet Server. These components include the serverboard, riser card, front panel board, hot-swap backplane, system BIOS, Advanced Server Management (ASM) software, chassis, and power supply. Certifications, reliability, and serviceability of the system are also discussed.
Intel® SRMK2 Internet Server Technical Product Specification iv
Conventions and Terminology Contents 1 INTRODUCTION...............................................................................................................................................11 2 CHASSIS DESCRIPTION ...............................................................................................................................13 2.1 EXTERNAL CHASSIS FEATURES.............................................................................................................. 13 2.1.
Conventions and Terminology 3.17.1 Back Panel I/O Connectors................................................................................................................ 39 3.17.2 Midboard Connectors........................................................................................................................ 41 3.17.3 Front Panel Connector....................................................................................................................... 48 3.18 JUMPER BLOCKS................
Conventions and Terminology 9.3 ISA BUS ERROR ......................................................................................................................................... 85 9.3.2 Processor Bus Error............................................................................................................................... 86 9.3.3 Memory Bus Error.................................................................................................................................. 87 9.3.
Conventions and Terminology Conventions and Terminology This document uses the following terms and abbreviations: Term Ω µA µF A AC ACPI AGP ASCII ASIC BIOS Byte C CD CD-ROM CE cfm CMOS CPU DC DCD DEMKO DIMM DMA DRAM ECC EDO EEPROM EMC EMI EN ESD EU F FC-PGA FCC FD FET FP FPC FRU GB Hz I/O I2C IDE ISA KB kg kV Definition Ohms 0.
Conventions and Terminology LED LVD mA MB MBE MIF mm ms MTBF MTTR NEMKO NIC NMI NVRAM OCP OEM OTP OVP PAC PCI Pf PFC OSB4 PIO PLD POST PPGA PXE RAM RPM RxD SBE SCL SCSI SDA SE SEEPROM SEL SEMKO SIO SMB SMC SMBIOS SMI SMM TTL TxD UART UL USB V VA Vac Light Emitting Diode Low Voltage Differential milliamps megabyte (1024 KB) Multi-bit Error Management Information database millimeters milliseconds Mean Time Between Failure Mean Time To Repair Norges Elektriske Materiellkontroll (Norwegian Board of Testing an
Conventions and Terminology VCCI Vdc Vin VRM Vrms W Wdc WOL WOR ZIF Voluntary Control Council for Interference (by data processing and electronic office equipment) Volts direct current Volts in Voltage Regulator Module Volts root-mean-square Watts Watts direct current Wake on LAN Wake on Ring Zero Insertion Force Intel® SRMK2 Internet Server Technical Product Specification x
1 Introduction This document provides a detailed description of the chassis and system level features of the Intel® SRMK2 Internet Server. This system is a high-density rackmount server consisting of a 1U chassis and the SRMK2 serverboard. The server will come in two models: A SCSI based system (SRMK2S) and a SCSI based system with a –48V DC power supply (SRMK2D). Since both of these systems are based off of the SRMK2S product, this guide has been written to represent the SRMK2S.
Intel® SRMK2 Internet Server Technical Product Specification 12
2 Chassis Description This section describes the features of the Intel® SRMK2 Internet Server chassis. 2.1 External Chassis Features 2.1.1 Chassis Dimensions The chassis is 1.70 inches high by 16.75 inches wide behind the bezel by 24.00 inches deep (measured from the front of the bezel to the deepest portion of the rear bulkhead).
2.1.3 Front View of Chassis The front bezel is a multiple -part plastic molding that contains the buttons, the LED indicator light pipes, and a flip-down door that spans half the width of the bezel and folds down (right striated portion in Figure 2 below). After pulling the flip door down the Power, Sleep, and Reset buttons as well as the NMI pin hole are revealed. This also reveals the floppy and CD-ROM bays. See Figure 3 for button placement.
A Hot Swappable SCSI Drives C Slimline Floppy B Slimline CDROM (Optional) Figure 4 : Front view of chassis without bezel (Does not show Front Panel swung out) 2.1.4 Rear View of Chassis The input/output connectors are accessible at the back panel of the chassis as shown in Figure 5. See Section 3.17.1 Back Panel I/O Connectors for detailed descriptions of the rear panel I/O connectors.
Table 3: 200W power supply output summary DC Power +3.3VDC at 13.0A Max. +5 VDC at 22A Max. +12 VDC at 3.5A Max. -12 VDC at 0.25A 5V Standby 1A Total power from supply 202.9W AC line voltage 90-135,180-265VAC PFC: auto sense AC line frequency 47 / 63 Hz 2.2.1.1 Power Supply Mechanical Outline Both AC and DC power supplies are 3.30”wide by 1.60” high by 9.60”in length.
2.2.1.4 DC Connector Requirements Figure 6 and Figure 7 show the connector pinouts for the serverboard power connectors. These mate with the power supply connectors at connector J27 and J39. 1 13 Ground VRM Input Voltage Ground VRM Input Voltage Ground VRM Input Voltage Ground VRM Input Voltage +3.3V Ground +3.3V Ground +3.3V Ground +3.
2.2.1.5 Power Supply Wiring Requirements The wiring length and the desired wire color-coding are specified in Figure 8. Edge of supply to center of connector on PCB. 3.5" (87.5mm) Only one wire tie at exit of supply this bundle. Wire exit hole in power supply. pin 13 P2 Main Board pin 1 Bundle A Wire lengths should vary to ensure no loops or slack wire. 0.25" Max Main board 2 Conn. P3 Bundle B Mini wire ties at one inch spacing length of bundle. 3.5" ±0.25" (87.
Pin Table 5: Baseboard Power Connector (P3) Signal Name 20 AWG Wire Pin Signal Name 20 AWG Wire 1 HECALERT#* N/A 6 SMB_Data* N/A 2 Ground Black 7 SMB_CLK* N/A 3 Ground Sense Black 8 +3.3V Sense Brown 4 PWR_ON# Green 9 PWRGOOD Grey 5 -12V Blue 10 +5V Sense Red * These pins are not stuffed or used on the SRMK2 power supply Table 6: SCSI Backplane Power Connector (P4) Pin Signal Name 20 AWG Wire 1 +12V Yellow 2 +12V Yellow 3 Ground Black 4 Ground Black 5 +3.
the worst case (lowest efficiency) of the power supply. Under nominal conditions the power supply should perform above the 70% efficiency level which will lower the BTU rating. Table 8: Overall BTU Ratings BTU (Loaded) BTU (Max) 314 BTU 988 BTU Table 9: Loaded System Configuration Manufacturer / Device Configuration Type CPU #1 733MHz (133 FSB) Intel Pentium III CPU #2 733MHz (133 FSB) Intel Pentium III Memory 256MB Micron 133 HDD #1 SCSI 9.1GB Quantum Atlas V HDD #2 SCSI 9.
2.2.5 System Peripheral Bays 2.2.5.1 CD-ROM and Diskette Drive Bay The right side of the system (as viewed from the front) contains the CD-ROM and diskette drive bays. Opening the door in the bezel exposes these peripherals. A slim-line diskette drive is provided with the system and a slim-line CD-ROM is an optional addition. For information on how to add/remove the CD-ROM and floppy, please refer to the instruction sheet that comes with the optional CD-ROM. 2.2.5.2 Internal 3.
2.2.6.2 System Cable Drawings Figure 9 shows drawings of all the internal cables within the system and the locations of their folds. Where applicable, the darker line indicates pin 1.
2.3 System Configuration Table 12 lists the base configuration of the SRMK2S Internet Server. Table 12: Standard configuration Description Qty SRMK2 serverboard 1 Dual-slot 66/64 PCI riser 1 Front panel board 1 200W power supply 1 System fans 9 SCSI Hard drive carriers 2 3.
3 SRMK2 Serverboard Description 3.1 Overview The SRMK2 serverboard features are summarized in Table 14. Table 14: SRMK2 feature summary Form Factor Serverboard dimension: 10.4” x 11.
3.2 Serverboard Layout Figure 10 shows the location of the major components on the serverboard.
Figure 11 is a block diagram of the SRMK2 serverboard.
3.3 Processors The SRMK2 serverboard supports dual Pentium® III processors. The host bus speed (100 MHz or 133 MHz) is automatically selected based on the speed of the processors placed in the PGA370 sockets. The processors must be secured by pushing the Zero-Insertion-Force (ZIF) socket’s lever down. The Intel SRMK2 serverboard can run in either a Uniprocessor (UP) mode or Dual Processor (DP) mode. A terminator must be placed in the second processor PGA370 socket for UP mode operation.
3.4 Chipset The ServerWorks ® ServerSet™ III LE chipset consists of the ServerWorks CNB30LE North Bridge chip and the ServerWorks OSB4 South Bridge chip. The CNB30LE provides an optimized DRAM controller. The I/O subsystem of the ServerWorks chipset is based on the OSB4 South Bridge, which is a highly integrated PCI ISA IDE Xcelerator Bridge. 3.4.
3.4.2 ServerWorks OSB4 South Bridge Chip The OSB4 South Bridge chip is a multifunctional PCI device implementing the PCI-to-ISA bridge, PCI IDE functionality, USB host/hub functionality, and enhanced power management.
3.5 Memory The serverboard has four DIMM sockets. The serial presence detect (SPD) data structure which is programmed into an E2PROM on the DIMM instructs the BIOS on the SDRAM’s size and speed. The minimum memory size is 64MB; the maximum memory size is 4GB. DIMMs can be populated in any order, but due to the 25 degree angle of the DIMM socket mountings it is physically easier to populate DIMMs starting with DIMM0 and moving towards DIMM3.
3.6 SCSI Host bus Interface The SRMK2 motherboard uses an Adaptec® AIC-7899 Ultra 160 SCSI controller for the SCSI Host bus interface. The AIC provides two independent Ultra 160/m SCSI channels combined with a full-featured PCI 2.1/2.2-compliant bus master. The AIC-7899 operates at up to 66MHz and functions as a 64-bit bus master capable of supporting zero wait state 64-bit memory transfers at a maximum data burst rate of 533 Mbytes/sec.
• • • ! Support for isochronous and asynchronous transfer types over the same set of wires Guaranteed bandwidth and low latencies appropriate for telephony, audio, and other applications Error-handling and fault-recovery mechanisms built into the protocol NOTE Computer systems that have an unshielded cable attached to a USB port may not meet FCC Class B requirements, even if no device or a low-speed USB device is attached to the cable.
calendar with alarm features and century rollover. The real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reserved for BIOS use. A coin-cell battery powers the real-time clock and CMOS memory. When the computer is not plugged into a wall socket, the battery has an estimated life of three years. When the computer is plugged in, the 3.3V standby current from the power supply extends the life of the battery. The clock is accurate to ± 13 minutes/year at 25ºC with 3.
• • • • 3.12 4M bytes of video SDRAM organized as 2Mx32-bits, accessible over the 64-bit interface of the controller. DDC1 and DDC2B+ for plug and play monitors. Power management for full VESA DPMS and EPA Energy Star compliance. Integrated hardware diagnostic tests performed automatically upon initialization. Hardware Monitor Two Heceta 3 controllers are provided on the motherboard to monitor temperature, voltage, and fan speed.
+12V D1+/D1- +12V N/A CPU 0 Thermistor CPU 1 Thermistor For more details on accessing the Heceta registers please refer to the ADM1024 data sheet from Analog Devices. 3.13 Wake on Ring and Resume on Ring The SRMK2 baseboard provides three methods for implementing Wake on Ring (WOR). An external modem connected to the serial port can toggle the super I/O controller’s Ring Indicator pin which should be enabled to cause a wakeup event.
3.15 Fan Support The backplane powers nine 40mm system fans. Additionally, it incorporates logic to control and monitor the tachometer speed of fans. Eight of those fans are 40mm x 28mm. The ninth fan is 40mm x 17mm and provides cooling to the PCI add-in card area. 3.16 Baseboard Programming 3.16.
3.16.3 PCIIRQ12 P2S2_INTAC# (PCI64 Slot2 Interrupts A & C) PCIIRQ13 P2S2_INTBD# (PCI64 Slot2 Interrupts B & D) PCIIRQ14 Not Used PCIIRQ15 Not Used SMI and NMI Routing There are numerous SMI/NMI sources. SMI/NMI sources are routed either to OSB4 or SIO GPI input pins. Software must configure the OSB4 and SIO GPI input pins to control whether the corresponding events will generate SMI, NMI or wake up events to the processors. The SMI/NMI sources on the SRMK2 are shown in Table 20.
LAN Controller 2 Slave :85 32 PCI Riser expansion Connector Slave Undefined ** 64 PCI Riser expansion Connector Slave Undefined ** Memory DIMM 0 Slave :50 Memory DIMM 1 Slave :51 Memory DIMM 2 Slave :52 Memory DIMM 3 Slave :53 st Slave :2D nd 2 Heceta System Management chip Slave :2E CNB30LE North Bridge chip Slave :C0 1 Heceta Management chip ** Note: At the writing of this document, the PCI riser expansion boards did not have an I 2C bus ID assigned. 3.
chassis such as fans and internal peripherals. Do not use these connectors for powering devices external to the computer chassis. A fault in the load presented by the external devices could damage the computer, the interconnecting cable, and the external devices themselves. 3.17.1 Back Panel I/O Connectors Figure 13 shows the location of the back panel I/O connectors.
Table 22: PS/2 keyboard/mouse connectors (J7) Pin Signal Name Pin 1 Keyboard or Mouse Data 2 Not connected 3 Ground 4 Fused +5 V 5 Keyboard or Mouse Clock 6 Not connected Table 23: USB stacked connector (J2) Signal Name Pin Signal Name 1 Fused +5 V 5 Fused +5 V 2 3.3 V differential USB signal USB_D- 6 3.3 V differential USB signal USB_D- 3 3.3 V differential USB signal USB_D+ 7 3.
Pin Pin Table 26: Video connector (J4) Signal Name Pin Signal Name 1 V_RED_FB 2 V_GREEN_FB 3 V_BLUE_FB 4 TP_VIO4 5 GRD 6 GRD 7 GRD 8 GRD 9 TP_VIO9 10 GRD 11 (Not Connected) 12 DDC2_SDA 13 V_HSYNC_R# 14 V_VSYNC_R# 15 DDC2_SCL Table 27: External SCSI (Channel A) connector (J1) Signal Name Pin Signal Name Pin Signal Name 1 SDA[12]+ 2 SDA[13]+ 3 SDA[14]+ 4 SDA[15]+ 5 SDA[P1]+ 6 SDA[0]+ 7 SDA[1]+ 8 SDA[2]+ 9 SDA[3]+ 10 SDA[4]+ 11 SDA[5]+ 12 SDA[6]+ 13 SD
− Primary IDE interface • Wake Headers and Power − Power connector − Wake on Ring Header − Wake on LAN Header • Add-in board − PCI bus 3.17.2.1 Peripheral Interfaces Figure 14 shows the locations of the peripheral interface connectors.
Pin Table 29: Internal SCSI (Channel B) Drive connector (J21) Signal Name Pin Signal Name Pin Signal Name 1 SDB[12]+ 2 SDB[13]+ 3 SDB[14]+ 4 SDB[15]+ 5 SDB[P1]+ 6 SDB[0]+ 7 SDB[1]+ 8 SDB[2]+ 9 SDB[3]+ 10 SDB[4]+ 11 SDB[5]+ 12 SDB[6]+ 13 SDB[7]+ 14 SDB[P0]+ 15 GRD 16 DIFFSB 17 SCSIB_5V 18 SCSIB_5V 19 EXT_SCSI_P19_NC 20 GRD 21 ATNB+ 22 GRD 23 BSYB+ 24 ACKB+ 25 RSTB+ 26 MSGB+ 27 SELB+ 28 CDB+ 29 REQB+ 30 IOB+ 31 SDB[8]+ 32 SDB[9]+ 33 SDB[10]+
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Table 31: IDE connector – J9 Primary Signal Name Pin Signal Name Reset IDE Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Ground DDRQ0 [DDRQ1] DIOW# DIOR# DRDY DDAK0# [DDAK1#] IRQ 14 [IRQ 15] IDE_A1 (Address 1) IDE_A0 (Address 0) IDE_CS1# IDE_ACT# 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Ground Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Key (NC) Ground Ground Ground CSEL (Cable Select pull-down) Ground R
To view pinouts and signals for the Power connector(s), see Section 2.2.1.4. Table 32: Wake on Ring connector (J11) Pin Signal Name 1 RINGA# 2 Ground Table 33: Wake on LAN connector (J8) Pin Signal Name 3.17.2.3 1 +5 VSB 2 Ground 3 WOL PCI Bus Riser Card Board Figure 16 shows the location of the PCI 64-bit Riser Bus Connector.
Pin Table 34: PCI 64/66 Riser Card connector (J15) Signal Name Pin Signal Pin Signal Name Name Pin Signal Name A1 +3.3VSB B1 +3.3VSB A52 P2_PAR B52 P2_CBE[1]# A2 +3.3VSB B2 +3.3VSB A53 P2_AD[15} B53 P2_AD[14] A3 +12V B3 -12V A54 +3.3V B54 GND A4 +5V B4 +5V A55 P2_AD[13] B55 P2_AD[12] A5 +3.3V B5 +3.3V A56 P2_AD[11] B56 P2_AD[10] A6 +3.3V B6 +3.
A42 +3.3V B42 GND A93 P2_AD[42] B93 GND A43 P2_FRAME# B43 P2_IRDY# A44 GND B44 +3.3V A94 +3.3V B94 P2_AD[39] A95 P2_AD[40] B95 P2_AD[37] A45 P2_TRDY# B45 P2_DEVSEL# A96 P2_AD[38] B96 +3.3V A46 GND B46 GND A97 GND B97 P2_AD[35] A47 A48 P2_STOP# B47 P2_LOCK# A98 P2_AD[36] B98 P2_AD[33] +3.3V B48 P2_PERR# A99 P2_AD[34] B99 GND A49 NC B49 +3.3V A100 GND B100 NC A50 NC B50 P2_SERR# A101 P2_AD[32] B101 NC A51 GND B51 +3.
3.17.3 Front Panel Connector Figure 17 shows the location of the front panel connector.
Pin Table 36: Front Panel I/O connector (J38) Signal Name Pin Signal Name Pin Signal Name 1 GND 2 +5V Power, Fused 3 D1 4 D0 5 D2 6 GND 7 D3 8 D4 9 D5 10 GND 11 D6 12 D7 13 GND 14 LCD_E# 15 LCD_RESET# 16 LCD_R/W# 17 DSR2 18 LCD_D/I# 19 CS2 20 FP_TYPE_BIT1 21 CS1 22 RI2 23 LED_GREEN_BLINK 24 SW1_PRESSED (scroll_sw1) 25 LED_YELLOW_BLINK 26 SW2_PRESSED (scroll_sw2) 27 LED_HDD 28 RESET_SW# 29 +5V Standby Power, Fused 30 POWERON_SW# 31 +3.
3.18 Jumper Blocks Figure 18 shows the locations of the password override, BIOS Setup configuration and whitebox/Appliance jumpers. CAUTION Do not move a jumper with the power on. Always turn off the power and unplug the power cord from the computer before changing jumper settings. A B C A B C BIOS Setup jumper Whitebox / Appliance jumper Clear Password jumper Figure 18: BIOS Setup configuration and password override jumpers The table below shows the jumper settings for the BIOS Setup jumper (J19).
The password override jumper (J20) will allow you to override a misplaced or forgotten BIOS password. Connecting the pins together with a jumper and starting the system will activate this jumper. Table 38: Password override jumper (J20) Pin Signal Name 1 PSWD_OVERRIDE 2 Ground The Whitebox / Appliance jumper (J16) provides a selection between “Whitebox” mode and “Appliance” mode for the server.
3.19 Thermal Considerations Figure 19 shows the locations of the thermally sensitive components. Table 40 provides maximum component case temperatures for serverboard components that could be sensitive to thermal changes. Case temperatures could be affected by the operating temperature, current load, or operating frequency. Maximum case temperatures are important when considering proper airflow to cool the serverboard.
Table 40: Thermal considerations for components Component Speed Maximum Temperature Pentium® III processor ServerWorks CNB30LE 1.0 GHz 70°C (thermal case) 933 MHz 75°C (thermal case) 866 MHz 80°C (thermal case) 800 MHz 80°C (thermal case) 733 MHz 80°C (thermal case) ® ServerWorks ® OSB4 3.
4 PCI Riser Board 4.1 Introduction A PCI riser board is used in the SRMK2 Internet Server system to facilitate the addition of two PCI add-in boards into the 1u chassis. It provides two PCI-compatible connectors mounted in opposite directions parallel to the serverboard. The pinout of the connectors is exactly the same as a standard PCI compatible connector. 4.2 Riser Board PCI Bus Connectors The riser card provides two 64-bit/66MHz PCI bus connectors.
4) You will then see a list of options. Choose the option entitled “Advanced Configuration Options” and press . 5) Choose “Host Adapter BIOS” from the options on the next screen and press . 6) You will then be in the Host Adapter BIOS options menu. Choose the option entitled “Disabled:scan bus” and press . (Note: You can also select the “Disabled:NOT scan” option if you do not want the bus scanned at startup).
~1.0” ~5.0” ~1.
5 Front Panel Board 5.1 Introduction The front panel board provides nine LED indicators, four system control switches, and four LCD control switches. The front panel board is connected to the SRMK2 serverboard via a highdensity connector.
system is hung. 5.3 Front Panel LED Indicators Table 44 defines the LED indicators on the front panel board. The LED’s are numbered below from 1 through 9 when reading them from in front of the server from left to right. Table 44: Front panel LEDs (DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9) LED Description Power On (Green) This LED indicates if the system is powered on. A blinking green LED indicates the system is in sleep mode.
6 SCSI Backplane 6.1 Introduction Fan 7 Power CDROM Pwr Connector Fan 6 Power Fan 4 Power SCSI Backplane Conn Fan 2 Power Fan 8 Power Backplane Baseboard Conn Fan 5 Power SCA SCSI Conn 0 Fan 3 Power SCA SCSI Conn 1 Backplane Power Connector Fan 9 Power Fan 1 Power The SCSI backplane provides nine fan headers for the system fans, two SCSI SCA drive connectors, and a power connector for the optional CDROM. This board is located between the system fans and the front drive bays.
Table 47: Backplane-to-Baseboard Connector (J10) Pin Signal Name Pin Signal Name 1 GND 11 Max Fans 2 ISC_SCL 12 GND 3 GND 13 Fan Mux 0 4 I2C_SDA 14 Fan Mux 1 5 Drive 0 Fault 15 GND 6 GND 16 Fan 4 Tach 7 Drive 1 Fault 17 Fan 3 Tach 8 Drive 0 Active 18 GND 9 GND 19 Fan 2 Tach 10 Drive 1 Active 20 Fan 1 Tach Intel® SRMK2 Internet Server Technical Product Specification 60
7 BIOS Description 7.1 Overview The SRMK2 serverboard uses an Intel/AMI BIOS, which is stored in Flash memory and can be upgraded using a disk-based program. In addition to the BIOS, the Flash memory contains the Setup program, POST, the PCI auto-configuration utility, and Plug and Play support. This serverboard supports system BIOS shadowing, allowing the BIOS to execute from 64-bit onboard write-protected DRAM. The BIOS displays a message during POST identifying the type of BIOS and a revision code.
7.2.1 Configuration Utility The Configuration Utility (CU) provides the means to configure on-board hardware devices and add-in cards. The CU consists of the standard PC-AT Setup utility (a.k.a. Setup), embedded in Flash ROM, for configuration of on-board resources. 7.2.2 CMOS Configuration RAM Summary The SuperI/O FDC37B782 chip on the baseboard contains battery-backed CMOS memory for system hardware setup parameters. 7.2.3 Flash Memory Update Utility The system BIOS is resident in partitioned Flash ROM.
7.3 System BIOS This section describes features of the system BIOS that are unique to SRMK2. For a complete specification of standard PC-BIOS functions, see Section 14.2 for information about the AMBIOS 98 specification.
7.3.1.1.2 Early Device Auto-Configuration The BIOS performs early initialization of the serial port for console redirection. This initialization must occur before initialization of the video controller so that all POST information may be redirected to a remote user. 7.3.1.1.3 PnP ISA Auto-Configuration For ISA PnP, the BIOS: • • • Fully supports the PnP ISA protocol. Reads the PnP ISA configuration port. Assigns the system I/O, memory, DMA channels, and IRQ’s from the resource pool.
all the operating systems have migrated to MPS version 1.4, MPS version 1.1 is no longer supported.
AP is protected, and does not get overwritten. Failure to comply with these guidelines will result in a system hang during the next SMI. 7.3.1.2.3 Multiple Processor speed support The SRMK2 BIOS supports numerous versions of Pentium® III without the need to reflash the BIOS. Two processor modules of different operating frequencies are not allowed within a single system configuration.
overwrite the existing update with a new release. These functions can be accessed from real mode by executing INT 15 with AX=0xD042. The corresponding 16-bit protected mode interface is not implemented. The BIOS performs all the recommended security checks before validating an update. See Section 14.2 for information about the Pentium® Pro Processor BIOS Writer’s Guide. 7.3.1.6 Processor Clock Ratio Settings and CMOS Clear SRMK2 will support all speeds of the Intel Pentium III processors.
204h MTRRphysBase2 Physical Address Base 2 0000h 205h MTRRphysMask2 Physical Address Mask 2 0000h 206h MTRRphysBase3 Physical Address Base 3 0000h 207h MTRRphysMask3 Physical Address Mask 3 0000h 208h MTRRphysBase4 Physical Address Base 4 0000h 209h MTRRphysMask4 Physical Address Mask 4 0000h 20Ah MTRRphysBase5 Physical Address Base 5 0000h 20Bh MTRRphysMask5 Physical Address Mask 5 0000h 20Ch MTRRphysBase6 Physical Address Base 6 0000h 20Dh MTRRphysMask6 Physical Addre
7.3.2.5 Chipset Performance Optimization The BIOS detects the system configuration (such as board ID, chipset stepping, and processor stepping) and optimizes the chipset for the best performance. The BIOS no longer supports a 1 MB hole at the 15-16 MB memory region. 7.3.
3) If the error is an SBE, the CNB30LE automatically corrects the data before it is returned to memory. The CNB30LE memory controller scrubs the memory location where the error occurred to correct the SBE, and the BIOS will record the SBE via an SMI to the SEL. If the error is an MBE this condition is considered fatal, and after the error is logged an NMI is generated telling the OS to handle this fatal error. 7.3.3.3 ECC Memory Initialization The system BIOS handles ECC memory initialization.
7.3.4 System Services The BIOS provides an interface, using the software interrupt 15h, to report system configuration information to application programs or the OS.
Table 49: System information (INT15h) functions Function (AX) Description DA12h New cache services DA8Ch Get version information DA92h Processor information The following sections describe each function, showing the values in processor registers on call and return. 7.3.4.
7.3.4.
7.3.4.3 Processor Info Call With Table 52: Get Processor Info Description AH = DAh AL = 92h CL = 0 Returns AL = Stepping ID AH = Model BL = Family CX = Processor bus speed in BCD (MHz) DX = Processor core speed in BCD (MHz) CF = 1 CF = 1, AH = 86h ! Description Error Function not supported NOTE This call is enhanced to report the processor core speed and the maximum number of processors in the system. The way processors are numbered is also changed. 7.3.
7.3.5.3 Ultra DMA IDE Support The SRMK2 BIOS provides Ultra DMA IDE support. This feature can be disabled via BIOS setup. 7.3.6 OEM Customization OEMs can customize the BIOS for product differentiation. The extent of customization is limited to what is stated in this section. OEMs can change the BIOS look and feel and manage OEMspecific hardware, if any, by executing their own code during the POST sequence.
This token is of the following format: MSB 15 LSB … 12 # of bits available - 1 11 … 0 Bit offset from start of CMOS of first bit The most significant 4 bits will be equal to the number of CMOS bits available minus 1. This field will be equal to 3 since there are four CMOS bits available. The 12 least significant bits will define the position of the CMOS bit in the RTC (Real Time Clock). This will be a bit address rather than a byte address.
; initialization. If the mask were 0Ch. Both scanpoint_04h and ; scanpoint_08h would be executed during post. 7.3.6.1.1 Scan Point Definitions Table 53 defines the bitmap for each scan point, indicating when the scan point occurs and which resources are available (RAM, Stack, Binary Data Area, Video, Keyboard).
Offset 0 1 - 0fh Table 54: Format of the user binary information structure Bit Definition Bit 0 = 1 if mandatory User Binary, = 0 if not mandatory Bit 1 = 1 if runtime presence required (other than SMM user binary portion, SMM user binary will always be present in runtime irrespective of setting of this bit), = 0, if not required in runtime, and can be discarded at boot time.
address space. Please refer to the System Management BIOS Reference Specification for details.
7.3.9 POST Memory Manager Support The BIOS supports revision 1.0 of the POST Memory Manager (PMM) specification. This specification allows external clients, such as option ROMs, to request memory buffer during initialization and release it later. Without the PMM, the option ROMs may overwrite buffers used by the system BIOS or another client. Check with your plug-in card vendor to make sure their PCI or ISA option ROM is PMM compliant.
from disk and resume. This assumes that no hardware changes were made to the system while it was off. S5: Soft off. The system, when executing a shutdown, will go to a state where the OSB4 is waiting for events to wake it up. Only the RTC section of the OSB4 is running in this state. The system is only truly off when the AC power is unplugged. 7.
For more detailed information regarding the WDT, see the Hardware Management Guide for the SRMK2 on the support.intel.com web site. 7.4.3 Paging Support The SRMK2 supports paging as the result of a request from the ASM software. Any POST error that gets logged in the SEL also causes a page out if paging is enabled. If a page out is required, the BIOS reads the Pager Number String in NVRAM and uses it to dial out (this is set through the ASM software).
8 Flash Memory Update Utility The Flash Memory Update Utility (IFLASH.EXE) loads a fresh copy of the BIOS into Flash ROM. Updating a Flash area takes a file or series of files from a hard or floppy disk, and loads it in the specified area of Flash ROM. ! NOTE The utility IFLASH.EXE must be run without the presence of a Protected Mode control program, such as Windows or EMM386. Do not run in a DOS window under Windows NT, Win98 or Win95. IFLASH.
9 Error Handling, Messages & Beep Codes This section defines how errors are handled by the system BIOS on the SRMK2 pla tform. It describes the role of the BIOS in error handling and the interaction between the BIOS and platform hardware as far as error handling is concerned. In addition, error-logging techniques are described, and beep codes for errors are defined. 9.1 Error Sources and Types One of the major requirements of server management is to correctly and consistently handle system errors.
9.2.1.3 SMI Handler The SMI handler preprocesses all system errors, even those that are normally considered to generate an NMI. The SMI handler is responsible for properly detecting the error type, logging it to the appropriate error log, and passing the error on to the OS if required. 9.3 ISA Bus Error ISA bus errors generate an NMI, triggered by a memory error or IOCHK# assertion on the ISA bus.
Table 58: PCI bus error control bits Bit Description Location Function CNB30LE 04h-05h PCICR 8 SERR# enable 1 = enable, 0 = disable 6 PERR# enable 1 = enable, 0 = disable CNB30LE 06h-07h PCISR 15 Detected Parity Error 1 = error, 0 = OK 14 Signaled System Error 1 = error, 0 = OK 13 Received Master Abort 1 = error, 0 = OK 12 Received Target Abort Status 1 = error, 0 = OK 8 Data Parity Detected 1 = error, 0 = OK 7 Enable SERR# on Received Target Abort 1 = enable, 0 = disable 6 E
9.3.3 Memory Bus Error The CNB30LE generates SERR# on single and multiple-bit errors. The following register bits control and log the errors. The following tables show the action taken by each error handler, and control bits associated with the error.
Beeps Error message Description 8 Display Memory Read/Write Error The system video adapter is either missing or its memory is faulty. This is not a fatal error. 9 ROM Checksum Error The ROM checksum value does not match the value encoded in AMIBIOS. 10 CMOS Shutdown Register Read/Write Error The shutdown register for CMOS RAM has failed. 11 Cache Memory Bad – Do Not Enable Cache The cache memory test failed. Cache memory is disabled.
Error Message Description HDD Controller Failure AMIBIOS cannot communicate with the hard disk drive controller. Check all appropriate connections after the system is powered down. INTR1 Error Interrupt channel 1 failed POST. INTR2 Error Interrupt channel 2 failed POST. Invalid Boot Diskette AMIBIOS can read the diskette in floppy drive A:, but it cannot boot the system with it. Use another boot diskette and follow the screen instructions. Keyboard Is Locked...
10 BIOS Setup Program The BIOS Setup program is used for viewing and changing the system’s BIOS settings. The user accesses Setup by pressing key after the Power-On-Self-Test (POST) memory test begins and before the operating system boot begins. The menu bar and a brief description of each menu item is shown in Table 63.
10.1 Save and Exit: Save the current values and exit Setup. A menu will appear asking the user to confirm. Press to save and exit. Press to remain in Setup. Maintenance Menu The menu bar is shown below. Maintenance Main Advanced Security Server Boot Exit The menu shown in Table 65 is for clearing Setup and boot passwords. Setup only displays this menu in configuration mode. See Section 3.18 for configuration mode setting information.
Secondary IDE Slave No options Reports name of device installed, otherwise displays ”Not Installed” Processor Configuration Processor Type (No options) Displays processor type. Processor Speed (No options) Displays processor speed (MHz). Processor Serial Number: Enables or Disables the Processor Serial Number Enabled / Disabled CPU ID Displays the CPU ID L2 Cache Displays the L2 Cache total English (US) (default). Selects which language the BIOS displays.
Diskette Controller Disabled Enabled (default) Diskette Write Protect Legacy USB Support Disabled (default) Disables or enables the integrated diskette controller. Enabled Disables or enables write protect for the diskette drive. Auto (default) Disables or enables support for legacy USB. Disabled Enabled Onboard SCSI Disabled Enabled (default) 10.4 Disables or enables the onboard SCSI controller. Security Menu The menu bar is shown below.
Quick Boot Disabled Allows the BIOS to skip certain tests while booting. This decreases the time needed to boot the system. Enabled (default) After Power Failure Stays Off Last State (default) Power On On Modem Ring Stay Off (default) APM Mode only: Determines the action of the system when the system power is off and the modem is ringing. Power On On LAN Stay Off Power On (default) On PME Stay Off (default) 1st IDE (default) Configures the peripheral devices.
Serial Port console redirection and paging. COM1 3F8 IRQ4 (default) COM2 2F8 IRQ3 COM3 3E8 IRQ4 Sets the baud rate. Baud Rate 9600 19.2K (default) 38.4K 115.2K If enabled, it will use the flow control selected. Flow Control CTS/RTS = Hardware. No Flow Control XON/XOFF = Software. CTS/RTS (default) CTS/RTS + CD = Hardware + Carrier Detect for modem use. XON/XOFF CTS/RTS+CD LAN Features LAN Console Redirection Disables or enables LAN console redirection.
10.7 Exit Menu The menu bar is shown below. Maintenance Main Advanced Security Boot System Management Exit Table 73 shows the Exit menu. This menu exits the Setup program – saving, discarding, and loading default settings. Feature Table 73: Exit menu Options Description Exit Saving Changes No options Exits system Setup and saves your changes in CMOS. Exit Discarding Changes No options Exits system setup without saving your changes in CMOS.
11 Certification 11.1 Safety Standards / Certifications Table 74: Safety standards / Certifications summary USA/Canada 11.2 UL 1950, 3rd Edition/CSA 22.2, No.
11.3 Electromagnetic Compatibility Notices (SRMK2S) 11.3.1 Japan English translation of the notice above: This is a Class A product based on the standard of the Voluntary Control Council for Interference by Information Technology Equipment (VCCI). If this equipment is used in a domestic environment, radio disturbance may arise. When such trouble occurs, the user may be required to take corrective actions. 11.3.
All cables used to connect to peripherals must be shielded and grounded. Operation with cables, connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception. 11.3.4 Taiwan (BSMI) The BSMI Certification number and the following warning is located on the product safety label which is located visibly on the external chassis. 11.4 Electromagnetic Compatibility Notices (SRMK2D) 11.4.
and on; the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and the receiver. • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. • Consult the dealer or an experienced radio/TV technician for help.
11.6 Mandatory / Standard: Certifications, Registration, Declarations • • • • • • • • UL, cUL Listing German GS Mark Nordic Certification FCC Declaration of Conformity CE Mark Declaration of Conformity VCCI Certification Industry Canada Certification Australia Communications Authority Declaration of Conformity 11.7 Environmental Limits 11.7.1.
12 Reliability and Serviceability 12.1 Reliability Based on a typical configuration, as listed in Table 78, the system’s Mean-Time-BetweenFailure (MTBF) as shipped from the factory was calculated to be approximately 39,278 hours (Approximately 4.5 years).
13 Compatibility Testing At the time of this writing, validation of the SRMK2 Internet Server with third-party operating systems and hardware has not been completed. Please visit http://www.intel.com/isp to find an up-to-date compatibility test report.
14 Specifications and Customer Support 14.1 Online Support Find the latest information on the Intel® SRMK2 Internet Server online at Intel’s site at http://www.intel.com/isp or http://support.intel.com. 14.2 Specifications Table 80 lists the specifications mentioned in this document. Specification ACPI AMI BIOS APM ATA-3 ATAPI ATX Table 80: Specification references Description Revision Level Advanced Configuration and Power Interface Specification Revision 1.0b, February 8, 1999.
ServerWorks® OSB4 Chipset South Bridge Chipset http://www.serverworks.com/home.html Intel 82559 Ethernet Controller Intel Fast Ethernet Multifunction PCI/Cardbus Controller Revision 2.0, May 1999.
SMBIOS DIMM Specification Revision 1.2, October 1998. PC Serial Presence Detect (SPD) Specification Revision 1.2a, December 1997, Intel Corporation System Management BIOS Reference Specification http://developer.intel.com/design/chipsets/memory/ Version 2.3.1, March 16, 1999. American Megatrends Inc., Award Software International Inc., Compaq Computer Corporation, Hewlett-Packard Company, Intel Corporation, IBM Corporation, Phoenix Technologies Ltd., and SystemSoft Corporation http://developer.intel.
Appendix A BIOS Console Commands All typed commands sent to the BIOS Console will be echoed on the display. The BIOS Console formats all output as 8-bit ASCII text. All input and output values are decimal except where noted. Each command is terminated with an ASCII carriage return . Command parameters are separated by ASCII spaces and as a result of this, spaces are not allowed when typing command strings into the BIOS Console.
08 10 99 02 27 07 41 30 00 02 00 00 00 00 00 00 08 10 99 02 26 05 34 11 00 02 00 00 00 00 00 00 >ReadSEL 0 1 Figure 23: ReadSEL Example Reboot -The BIOS console will reboot the system. During reboot, the BIOS will examine BIOSControl to determine if any special action is required such as powering off the system or booting the service partition. CMOS/NVRAM commands GetBootCount The number of times the OS has tried to boot GetLastState This represents the last known state of the system.
2 3 4 Sensor Threshold Non-Critical Sensor Threshold Critical Power Lost GetReasonCode This code represents the reason why the OS went down if known. Only applicable if Last Known State is OS Going Down or OS Down. Possible values are: 0 Unknown or N/A (default) 1 User-requested reboot 2 User-requested shutdown 3 Automatic reboot 4 Automatic shutdown GetSerialConfig PutSerialConfig These codes represent the direct serial or modem configuration.
0 1 Modem (default) Direct connect An example of this command is presented in figure 2 below. 3 1 3 0 1 0 0 0 >GetSerialConfig Figure 24: GetSerialConfig example GetBIOSControl PutBIOSControl This value directs the BIOS to enable/disable various fail-safe BIOS features.
Pager Number String is a string representing the phone number that the BIOS uses to page in case of emergency. Length is not to exceed 64 bytes and spaces are not allowed. An example of this command is shown in figure 3 below. >PutPagerNum 918005991234 Figure 25: PutPagerNum example GetPagerStr PutPagerStr Pager String is a string that the BIOS sends once the pager number has been dialed and a connection has been established. Length is not to exceed 64 bytes and spaces are not allowed.
Password commands EnablePassword This command enables the password for access to the BIOS console. The New Password and the Verification Password must be identical to enable the password. Maximum password length is 20 characters and spaces are not allowed. ChangePassword This command changes the password for access to the BIOS console.
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Press 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 to continue...
Password: Figure 28: Password prompt The password will not be echoed on the display as it is entered. If the correct password is entered, the standard prompt will be displayed and operation proceeds normally. If an incorrect password is entered, an error message is displayed followed by the password prompt.
Intel® SRMK2 Internet Server Technical Product Specification 115
