User`s manual
Devices CPU modules
MELSEC System Q, Hardware 4 – 11
R File regis-
ter
When using the internal RAM: R0–32767 (32768)
with block conversion in steps of 32768 registers,
131072 (for Q04UD(E)HCPU),
393216 (for Q06UD(E)CPU),
524288 (for Q10UD(E)CPU and Q13UD(E)CPU) or
655360 (for Q20UD(E)CPU and Q26UD(E)CPU)
file registers are accessible.
When using a 1 MB SRAM memory card: with block con-
version in steps of 32768 registers, 517120 file registers
are accessible.
When using a 2 MB Flash or 2 MB SRAM memory card:
with block conversion in steps of 32768 registers,
1041408 file registers are accessible.
When using a 4 MB Flash or 4 MB SRAM memory card:
with block conversion in steps of 32768 registers,
2087936 file registers are accessible.
When using a 8 MB SRAM memory card: with block con-
version in steps of 32768 registers, 4184064 file regis-
ters are accessible.
Extension of the data register area
When using a Flash memory card only
reading of the file registers is possible.
It’s not possible, to use an ATA memory
card.
When using the internal RAM:
ZR0–131071 (131072) for Q04UD(E)HCPU,
ZR0–393215 (393216) for Q06UD(E)HCPU,
ZR0–524287 (524288) for Q10UD(E)-/ Q13UD(E)CPU
ZR0–655359 (655359) for Q20UD(E)-/ Q26UD(E)CPU
Block conversion is not necessary.
When using a 1 MB SRAM memory card: ZR0–517119
(517120), Block conversion is not necessary.
When using a 2 MB Flash or 2 MB SRAM memory card:
ZR0–1041408 (1041407), Block conversion is not nec-
essary.
When using a 4 MB Flash or 4 MB SRAM memory card:
ZR0–2087935 (2087936), Block conversion is not nec-
essary.
When using a 8 MB SRAM memory card: ZR0–4184063
(4184064), Block conversion is not necessary.
SB Link spe-
cial relay
SB0–7FF (2048) Bit devices in a network
SW Link spe-
cial regis-
ter
SW0–7FF (2048) Register for Link data
Z Index reg-
ister
Z0–19 (20) Register for indexing of devices
32 Bit-
Index reg-
ister
Z0–18 (10)
(Two index registers are each combined in one word)
N Nesting N0–14 (15 Steps) Displays the nesting of Master control
processes
P Pointer P0–4095 (4096)
The common pointer address is set by parameters.
Target of a jump instruction (CJ, SCJ,
CALL, JMP)
I Interrupt
Pointer
I0 –255 (256)
The constant cyclic interval of system interrupt pointers I28
to 31 can be set up by parameters (0.5 to 1000 ms, 0.5 ms
unit). Default values:
I28: 100 ms; I29: 40 ms; I30: 20 ms; I31: 10 ms
Pointer for branching of interrupt pro-
grams
K Decimal
constant
K -32768–32767 (16 bit instructions)
K -2147483648–2147483647 (32 bit instructions)
For specification of command values
for timer and counter, pointer, interrupt
pointer, number of bit devices and
instruction values
H Hexadeci-
mal con-
stant
H
0–FFFF (16 bit instruction)
H0–FFFFFFFF (32 bit instruction)
For specification of instruction values
FX Function
input
FX0–F (16) Device for the status of input bits for
subroutines.
FY Function
output
FY0–F (16) Device for the status of output bits for
subroutines.
FD Function
register
FD0–4 (5) Status register for the input and output
bits for subroutines
Device name
Range (total number)
ExplanationQ04UDH Q06UDH Q10UDH Q13UDH Q20UDH Q26UDH
Q04UDEH Q06UDEH Q10UDEH Q13UDEH Q20UDEH Q26UDEH
Tab. 4-5: Device list of CPU types Q04UD(E)H to Q26UD(E)H