Service manual

Table Of Contents
16. Start Pulse Generator (SPG) R763512
16.2 Technical Info
Block Diagram
Max. 100Vdc output voltage
Secondary side
Lamp Power Supply
230VAC
mains
C
+
-
Xenon Arc Lamp
2.2kW
Superimposing
transformer
Spark gap
Capacitor loading circuit
(active during lamp startup)
Block diagram Start Pulse Generator
Image 16-2
Block diagram SPG
Technical Description
The transformer is triggered at the primary by a periodical discharge of a few high voltage capacitors (C5, C6, C7) through two spark
gaps (SA1, SA2). This generates an energy pulse of a few megahertz. The voltage at the secondary is several times higher than
the voltage on the primary.
The high voltage capacitors itself are charged by a Switched Mode Power Supply. All active components of the SMPS are on the
subunit of the SPG.
At the beginning of a switching cycle the Mosfet Q1 it turned on. The current through Q1 and the primary of T1 ramps up, putting
energy into T1. The HV diodes on the secondary are at that time off. The current is measured by resistors R5 and R6. When it
reaches about 5 A the control IC I1 switches Q1 off. The energy stored in T1 is now charging C5, C6 and C7 via a current through
D3.
The capacitor C4 and the diode D2 form a clamping circuit for the high voltage peaks on the secondary of T1. The capacitor C4 is
charged through D2 at the beginning of the on period of Q1. To limit the peak current at that time, L1 is added. Because L1 would
generate a high voltage when Q1
is switched off, a snubber network formed around D1, R1 and C3 is also added.
The IC1 is a low power current mode PWM IC (Pulse Width Modulation). It is activated when the lamp voltage reaches about 85V.
This is the minimum dc lamp voltage for igniting the lamp. The moment the lamp voltage drops below this voltage, it means the lamp
is ignited and the IC is disactivated.
Detection of the lamp volta
ge is done by Q2 and Z1. When the voltage across R10 becomes higher than the zener voltage, Q2
begins to conduct and delivers power to IC1.
A turn-on delay of about one second is added by the network C4, R2 and D1 to make sure the dc lamp voltage is stabilized.
The switching frequency is determined by R1 and C5 and is set at about 12.5kHz. D2 and D3 protect the circuit against reversed
polarity.
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R5976820 SLM R12+ PERFORMER 08/03/2005