Installation Instructions

Hardware Installation
RVP8 User’s Manual
September 2005
2–15
For similar reasons (i.e., transition band width), the digital FIR filter itself also becomes difficult
to design when its passband is near a Nyquist multiple. But there is an additional constraint that
the digital filter should have a very large attenuation at DC. This is so that fixed offsets in the
A/D converter do not propagate into the synthesized “I” and “Q” data. Since 36MHz is aliased
into DC, we are left with the contradictory requirements of a zero very close to the edge of the
filter’s passband.
2.2.11 IFD Analog AFC Output Voltage (Optional)
An analog AFC voltage is produced by a 16-bit DAC whose output limits are –10V to +10V.
Gain and Offset potentiometers on the IFD module set the actual operating span within these
limits. Use the switch settings described below to force the low, center, and high voltages to be
output, and then adjust the two potentiometers so that the desired voltage span is achieved. The
Offset adjustment is independent of the Gain adjustment. Hence, a good strategy is to first set
the switches for the midpoint voltage, and adjust the Offset potentiometer so that the center IF
frequency is produced by the STALO mixer. Then, adjust the Gain potentiometer for the desired
tuning range around that center point. The midpoint voltage will not change as you vary the
overall span.
AFC voltage output is always enabled on Rev.B (and earlier) IFD boards. On Rev.C (and later)
boards, the AFC function shares the same connector with the optional reference clock input (See
Section 2.2.12). AFC can be enabled on a Rev.C board as follows:
S Remove U14
S Install U11, U12, U13
S Set JP1 to its AB position, which is also labeled “AFC”.
S Install fixed frequency stable 35.975MHz oscillator at U5.
The instructions are similar for a Rev.D board except that you do not need to remove U14, and
you must check that no jumper has been placed on JP3/BC (See Table 2–7).
Additional information about using AFC can be found in Sections 2.4, 3.2.6, and 5.1.3.
2.2.12 IFD Reference Clock Input (Optional)
When the RVP8 is used in a klystron system, or in any type of synchronous radar, the radar
COHO is supplied to the IFD so that the processor can digitally lock to it. The COHO phase is
measured at the beginning of each transmitted pulse, and is used to lock the subsequent (I,Q)
data for that pulse. The COHO phase is measured relative to the IFD’s own internal stable
sampling clock, which is nominally 35.975MHz. The internal sampling clock itself is not
affected by the application of the COHO. Rather, A/D samples of the COHO are obtained at the
fixed sampling rate, and the (I,Q) data are digitally locked downstream in the RVP8 IF-to-I/Q
processing chain (see Figure 1–3). The procedure is identical to the manner in which phase is
recovered in a magnetron system, except that the COHO signal is used in place of a sample of
the transmit burst.