Installation Instructions

Hardware Installation
RVP8 User’s Manual
September 2005
2–16
There are two special concerns that may come up when the RVP8 is used in the above manner
within a synchronous radar system. Both concerns are the result of the IFD’s sampling clock
being asynchronous with the radar system clock.
S RVP8 Generates the Radar Trigger
The trigger signals supplied by the RVP8 are synchronous with the IFD data sampling
clock. This is accomplished by a clock recovery PLL on the RVP8/Rx that provides
on-board timing which is identical to the sampling clock in the IFD. However, since the
IFD sampling clock is asynchronous with the radar clock(s), the RVP8 trigger outputs are
likewise asynchronous. The result is that each transmitted pulse envelope will be
triggered independently of the COHO phase. The transmitted pulse is still synchronous
–– but the precise alignment of the amplitude modulated envelope will vary.
S In almost all cases, the exact placement of the transmitter’s amplitude envelope does not
affect the overall system stability, nor the ability of the RVP8 to reject ground clutter and
to process multi-mode return signals. For this reason, a synchronous radar system that is
triggered using the RVP8 triggers will still perform optimally using the standard digital
COHO locking techniques. In spite of this, however, some system designers may still
prefer that the amplitude envelope itself be locked to the COHO.
S RVP8 Receives the Existing Radar Trigger
When an external trigger is supplied to the RVP8, the processor synchronizes its internal
range bin selection circuitry to that external trigger. The placement of the range bins
themselves, however, is always synchronous with the IFD’s 35.975MHz acquisition
clock. The result is that 27.8ns of jitter is introduced in the placement of the RVP8’s
range bins relative to the transmitted pulse itself.
S The effect of this synchronization jitter is that targets appear to be fluctuating in range by
approximately 4.2 meters. Although this is small relative to the range bin spacing itself,
and thus does not affect the range accuracy of the data, the effect on overall system
stability is more severe. Using both numerical modeling and actual field measurements,
we have found that sub-clutter visibility of a msec pulse may be limited to approximately
43dB as a result of this 27.8ns range jitter. This falls quite short of the usual expectations
of a synchronous radar system in which clutter rejection of 55–60dB should be
attainable.
The solution to either of the above concerns is to provide some means for the IFD’s internal
sampling clock to be phase locked to the radar system. If the RVP8 provides the radar triggers,
then those triggers would become synchronous with the radar COHO; and if the RVP8 receives
an external trigger, then its range bin clock would be synchronous with that external trigger, and
thus, there will be no synchronization jitter in the range bins.
Beginning with Rev. C, the IFD offers the option of locking its sampling clock to an external
system clock reference. This results in an RVP8 that is fully synchronous with the existing radar
timing. Rather than being derived from a fixed-frequency oscillator, the phase locked IFD
sampling clock is driven by a custom Voltage-Controlled-Crystal-Oscillator (VCXO). This
oscillator can have a center frequency in the 33.5 to 39.5MHz range, which is any rational
multiple P/Q of twice the input reference frequency, where P and Q are integers between 1 and