Installation Instructions
Hardware Installation
RVP8 User’s Manual
September 2005
2–37
The period t
s
of the serial data is (128ń f
aq
), where f
aq
is the acquisition clock frequency given
in the Mc section of the RVP8 setup menu. For the default clock frequency of 71.9502MHz, the
period of the serial data will be 1.779μsec. The logic that is receiving the serial data should first
locate the center of the first data bit at (0.5 t
s
) past the falling edge at the end of the burst
window. Subsequent data bits are then sampled at uniform t
s
intervals.
The actual data sampling rate can be in error by as much as one part in 75 while still maintaining
accurate reception. This is because the data sequence is only 25-bits long, and hence, the last
data bit would still be sampled within 1/3 bit time of its center. Having this flexibility makes
it easier to design the receiving logic. For example, if a 5MHz or 10MHz clock were available,
then sampling at 1.8μsec intervals (1:85 error) would be fine. Likewise, one could sample at
1.75μsec based on a 4MHz or 8MHz clock (1:61 error), but only if the first sample were moved
slightly ahead of center so that the sampling errors were equalized over the 25-bit span.
Interpreting the Serial 16-bit Data Word
The serial 16-bit data word has several different interpretations according to how the RVP8 has
been configured, and whether Bit #22 of the uplink stream is set or clear. The evolution of these
different formats has been in response to new features being added to the IFD (Section 2.2), and
the production of the DAFC Digital AFC Module (Section 2.4).
The original use of the uplink data word was simply to convey a 16-bit AFC level, generally for
use with a magnetron system. Bit #22 is clear in this case, and the word is interpreted as a linear
signed binary value. The use of this format is discouraged for new hardware designs, but it will
remain available to guarantee compatibility with older equipment.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
| | | | | | | | | | | | | | | | |
| 16–Bit AFC Level | AFC–16
|_______________________________________________________________|
Level 0111111111111111 (most positive AFC voltage)
0000000000000000 (center AFC voltage)
1000000000000000 (most negative AFC voltage)
When the IFD is jumpered for phase locking to an external reference clock, then Bit #22 will be
clear and the data word conveys the PLL clock ratio, and the Positive/Negative deviation sign of
the Voltage Controlled Crystal Oscillator (VCXO). This format is commonly used with klystron
systems, especially when the RVP8 is locking to an external trigger.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
| | | | | | | | | | | | | | | | |
| |Pos| Numerator – 1 | Denominator – 1 | PLL–16
|___|___|___________________________|___________________________|
Note that the AFC-16 and PLL-16 formats can never be interleaved for use at the same time,
since there would be no way to distinguish them at the receiving end.
Finally, an expanded format has been defined to handle all future requirements of the serial
uplink. Bit #22 is set in this case, and the data word is interpreted as a 4-bit command and 12-bit
data value. A total of 16x12=192 auxiliary data bits thus become available via sequential
transmission of one or more of these words. The CMD/DATA words can also be used along
with one of the AFC-16 or PLL-16 formats, since Bit #22 marks them differently.