Datasheet

ManualsBrandsBenchmark ManualsTV Converter BoxADC16

Rev. 2.5

April 2003 1/153

ST72334J/N,

ST72314J/N, ST72124J

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,

ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

■ Memories

– 8K or 16K Program memory (ROM or single

voltage FLASH) with read-out protection and

in-situ programming (remote ISP)

– 256 bytes EEPROM Data memory (with read-

out protection option in ROM devices)

– 384 or 512 bytes RAM

■ Clock, Reset and Supply Management

– Enhanced reset system

– Enhanced low voltage supply supervisor with

3 programmable levels

– Clock sources: crystal/ceramic resonator os-

cillators or RC oscillators, external clock,

backup Clock Security System

– 4 Power Saving Modes: Halt, Active-Halt,

Wait and Slow

– Beep and clock-out capabilities

■ Interrupt Management

– 10 interrupt vectors plus TRAP and RESET

– 15 external interrupt lines (4 vectors)

■ 44 or 32 I/O Ports

– 44 or 32 multifunctional bidirectional I/O lines:

– 21 or 19 alternate function lines

– 12 or 8 high sink outputs

■ 4 Timers

– Configurable watchdog timer

– Realtime base

– Two 16-bit timers with: 2 input captures (only

one on timer A), 2 output compares (only one

on timer A), External clock input on timer A,

PWM and Pulse generator modes

■ 2 Communications Interfaces

– SPI synchronous serial interface

– SCI asynchronous serial interface (LIN com-

patible)

■ 1 Analog Peripheral

– 8-bit ADC with 8 input channels (6 only on

ST72334Jx, not available on ST72124J2)

■ Instruction Set

– 8-bit data manipulation

– 63 basic instructions

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

– True bit manipulation

■ Development Tools

– Full hardware/software development package

Device Summary

TQFP44

10 x 10

PSDIP42

PSDIP56

TQFP64

14 x 14

Features ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4

Program memory - bytes 8K 8K 16K 8K 16K 8K 16K 8K 16K

RAM (stack) - bytes 384 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256)

EEPROM - bytes - - -

256 256 256 256

Peripherals

Watchdog, Two 16-bit Timers, SPI, SCI

-ADC

Operating Supply 3.2V to 5.5V

CPU Frequency Up to 8 MHz (with up to 16 MHz oscillator)

Operating Temperature -40°C to +85°C (-40°C to +105/125°C optional)

Packages TQFP44 / SDIP42 TQFP64 / SDIP56 TQFP44 / SDIP42 TQFP64 / SDIP56

Summary of content (153 pages)

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ST72334J/N, ST72314J/N, ST72124J 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES ■ ■ ■ ■ ■ ■ Memories – 8K or 16K Program memory (ROM or single voltage FLASH) with read-out protection and in-situ programming (remote ISP) – 256 bytes EEPROM Data memory (with readout protection option in ROM devices) – 384 or 512 bytes RAM Clock, Reset and Supply Management – Enhanced reset system – Enhanced low voltage supply supervisor with 3 programmable levels – Clock sources: cry
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Table of Contents 1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 12.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ST72334J/N, ST72314J/N, ST72124J To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet.
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ST72334J/N, ST72314J/N, ST72124J 1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION New Features available on the ST72C334 ■ 8 or 16K FLASH/ROM with In-Situ Programming and Read-out protection ■ New ADC with a better accuracy and conversion time ■ New configurable Clock, Reset and Supply system ■ New power saving mode with real time base: Active Halt ■ Beep capability on PF1 ■ New interrupt source: Clock security system (CSS) or Main clock controller (MCC) New Memory Locations in ST72C334 ■ 20h: MISCR reg
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ST72334J/N, ST72314J/N, ST72124J 2 INTRODUCTION The ST72334J/N, ST72314J/N and ST72124J devices are members of the ST7 microcontroller family. They can be grouped as follows: – ST72334J/N devices are designed for mid-range applications with Data EEPROM, ADC, SPI and SCI interface capabilities. – ST72314J/N devices target the same range of applications but without Data EEPROM. – ST72124J devices are for applications that do not need Data EEPROM and the ADC peripheral.
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ST72334J/N, ST72314J/N, ST72124J 3 PIN DESCRIPTION NC NC PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 NC NC RESET ISPSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) Figure 2.
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ST72334J/N, ST72314J/N, ST72124J PIN DESCRIPTION (Cont’d) Figure 3.
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ST72334J/N, ST72314J/N, ST72124J PIN DESCRIPTION (Cont’d) PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET ISPSEL PA7 (HS) PA6 (HS) PA5 (HS) PA4 (HS) Figure 4.
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ST72334J/N, ST72314J/N, ST72124J PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to Section 16 "ELECTRICAL CHARACTERISTICS" on page 107. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD, CT= CMOS 0.3VDD/0.
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ST72334J/N, ST72314J/N, ST72124J Port Alternate function 25 15 15 10 PF0/MCO I/O CT X ei1 X X Port F0 Main clock output (fOSC/2) 26 16 16 11 PF1/BEEP I/O CT X ei1 X X Port F1 Beep signal output 27 17 17 12 PF2 I/O CT X X X Port F2 I/O CT X X X I/O CT HS X X X X Port F6 Timer A Input Capture 1 32 20 20 15 PF7 (HS)/EXTCLK_A I/O CT HS X X X X Port F7 Timer A External Clock Source 24 28 VSS_3 S Digital Ground Voltage ei1 NC 29 18 18 13 PF4/OCMP1_A 30 int P
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ST72334J/N, ST72314J/N, ST72124J 59 45 42 35 OSC1 3) 60 46 43 36 VDD_3 Main Output function (after reset) Alternate function PP ana int wpu Input OD Port float Output Type SDIP42 SDIP56 QFP44 TQFP64 Pin Name Input Level Pin n° External clock input or Resonator oscillator inverter input or resistor input for RC oscillator I S Digital Main Supply Voltage 61 47 44 37 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out 62 48 1 38 PE1/RDI I/O CT X X X X Port E1 SCI Receiv
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ST72334J/N, ST72314J/N, ST72124J 4 REGISTER & MEMORY MAP As shown in the Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 384 or 512 bytes of RAM, up to 256 bytes of data EEPROM and 4 or 8 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors.
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ST72334J/N, ST72314J/N, ST72124J REGISTER & MEMORY MAP (Cont’d) Table 2.
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ST72334J/N, ST72314J/N, ST72124J Address Block 002Ah WATCHDOG 002Bh 002Ch Data-EEPROM Register Label Register Name Reset Status WDGCR Watchdog Control Register CRSR Clock, Reset, Supply Control / Status Register 000x 000x R/W EECSR Data-EEPROM Control/Status Register 00h R/W 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only 3) Read Only 3) R/W 3) R/W 3) 002Dh 0030h 7Fh Remarks R/W
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ST72334J/N, ST72314J/N, ST72124J Address Block Register Label 0058h 006Fh 0070h 0071h 0072h to 007Fh Register Name Reset Status Remarks Reserved Area (24 Bytes) ADC ADCDR ADCCSR Data Register Control/Status Register xxh 00h Read Only R/W Reserved Area (14 Bytes) Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2.
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ST72334J/N, ST72314J/N, ST72124J 5 FLASH PROGRAM MEMORY FLASH devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool) on a byte-bybyte basis. 5.2 MAIN FEATURES ■ ■ ■ ■ Remote In-Situ Programming (ISP) mode Up to 16 bytes programmed in the same cycle MTP memory (Multiple Time Programmable) Read-out memory protection against piracy 5.
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ST72334J/N, ST72314J/N, ST72124J 6 DATA EEPROM 6.1 INTRODUCTION 6.2 MAIN FEATURES The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter.
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ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d) 6.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these different memory access modes. Read Operation (LAT=0) The EEPROM can be read as a normal ROM location when the LAT bit of the EECSR register is cleared. In a read cycle, the byte to be accessed is put on the data bus in less than 1 CPU clock cycle.
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ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d) 6.4 POWER SAVING MODES 6.5 ACCESS ERROR HANDLING Wait mode The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller. The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode. If a read access occurs while LAT=1, then the data bus will not be driven.
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ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d) Bit 1 = LAT Latch Access Transfer This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if PGM bit is cleared. 0: Read mode 1: Write mode 6.6 REGISTER DESCRIPTION CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h) 7 0 0 0 0 0 0 IE LAT PGM Bit 7:3 = Reserved, forced by hardware to 0. Bit 2 = IE Interrupt enable This bit is set and cleared by software.
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ST72334J/N, ST72314J/N, ST72124J 7 DATA EEPROM Register Map and Reset Values Address (Hex.) 002Ch Register Label 7 6 5 4 3 2 1 0 0 0 0 0 0 IE 0 RWM 0 PGM 0 EECSR Reset Value 7.1 READ-OUT PROTECTION OPTION The Data EEPROM can be optionally read-out protected in ST72334 ROM devices (see option 22/153 list on page 146). ST72C334 Flash devices do not have this protection option.
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ST72334J/N, ST72314J/N, ST72124J 8 CENTRAL PROCESSING UNIT 8.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 8.2 MAIN FEATURES ■ ■ ■ ■ ■ ■ ■ ■ 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt 8.
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ST72334J/N, ST72314J/N, ST72124J CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx 7 1 0 1 1 H I N Z C The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry.
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ST72334J/N, ST72314J/N, ST72124J CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh 15 0 8 0 0 0 0 0 0 7 SP7 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11).
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ST72334J/N, ST72314J/N, ST72124J 9 SUPPLY, RESET AND CLOCK MANAGEMENT The ST72334J/N, ST72314J/N and ST72124J microcontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 12. See Section 16 "ELECTRICAL CHARACTERISTICS" on page 107 for more details.
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ST72334J/N, ST72314J/N, ST72124J 9.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.
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ST72334J/N, ST72314J/N, ST72124J 9.2 RESET SEQUENCE MANAGER (RSM) 9.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 15: ■ External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
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ST72334J/N, ST72314J/N, ST72124J RESET SEQUENCE MANAGER (Cont’d) 9.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details.
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ST72334J/N, ST72314J/N, ST72124J 9.3 MULTI-OSCILLATOR (MO) External RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an external resistor and an external capacitor. The frequency of the external RC oscillator (in the range of some MHz.) is fixed by the resistor and the capacitor values. Consequently in this MO mode, the accuracy of the clock is directly linked to the accuracy of the discrete components.
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ST72334J/N, ST72314J/N, ST72124J 9.4 CLOCK SECURITY SYSTEM (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a clock filter control and an Internal safe oscillator. The CSS can be enabled or disabled by option byte. 9.4.1 Clock Filter Control The clock filter is based on a clock frequency limitation function.
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ST72334J/N, ST72314J/N, ST72124J 9.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION Read /Write Reset Value: 000x 000x (xxh) 7 0 0 0 0 LVD RF CSS IE 0 CSS WDG D RF Bit 7:5 = Reserved, always read as 0. Bit 4 = LVDRF LVD reset flag This bit indicates that the last RESET was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by option byte, the LVDRF bit value is undefined.
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ST72334J/N, ST72314J/N, ST72124J 10 INTERRUPTS The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 18. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).
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ST72334J/N, ST72314J/N, ST72124J INTERRUPTS (Cont’d) Figure 18. Interrupt Processing Flowchart FROM RESET I BIT SET? N N Y Y FETCH NEXT INSTRUCTION N IRET? INTERRUPT PENDING? STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR Y EXECUTE INSTRUCTION RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT Table 5.
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ST72334J/N, ST72314J/N, ST72124J 11 POWER SAVING MODES 11.1 INTRODUCTION 11.2 SLOW MODE To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 19): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT. After a RESET the normal operating mode is selected by default (RUN mode).
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ST72334J/N, ST72314J/N, ST72124J POWER SAVING MODES (Cont’d) 11.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged.
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ST72334J/N, ST72314J/N, ST72124J POWER SAVING MODES (Cont’d) 11.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register). MCCSR OIE bit Power Saving Mode entered when HALT instruction is executed 0 HALT mode 1 ACTIVE-HALT mode 11.4.
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ST72334J/N, ST72314J/N, ST72124J POWER SAVING MODES (Cont’d) 11.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 14.2 "MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)" on page 52 for more details on the MCCSR register).
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ST72334J/N, ST72314J/N, ST72124J 12 I/O PORTS 12.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 12.
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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) Figure 26. I/O Port General Block Diagram ALTERNATE OUTPUT REGISTER ACCESS 1 VDD 0 P-BUFFER (see table below) ALTERNATE ENABLE PULL-UP (see table below) DR VDD DDR PULL-UP CONFIGURATION DATA BUS OR PAD If implemented OR SEL N-BUFFER DIODES (see table below) DDR SEL DR SEL ANALOG INPUT CMOS SCHMITT TRIGGER 1 0 EXTERNAL INTERRUPT SOURCE (eix) POLARITY SELECTION ALTERNATE INPUT FROM OTHER BITS Table 6.
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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) Table 7.
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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) 12.4 LOW POWER MODES Mode WAIT HALT 12.5 INTERRUPTS Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode. The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the I-bit in the CC register is reset (RIM instruction).
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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) 12.5.1 Register Description OPTION REGISTER (OR) Port x Option Register PxOR with x = A, B, C, D, E or F. Read /Write Reset Value: 0000 0000 (00h) DATA REGISTER (DR) Port x Data Register PxDR with x = A, B, C, D, E or F. Read /Write Reset Value: 0000 0000 (00h) 7 D7 D6 D5 D4 D3 D2 D1 0 7 D0 O7 Bit 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration.
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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) Table 9. I/O Port Register Map and Reset Values Address (Hex.
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ST72334J/N, ST72314J/N, ST72124J 13 MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several different features such as the external interrupts or the I/O alternate functions. Figure 28. Ext. Interrupt Sensitivity MISCR1 IS10 13.1 I/O PORT INTERRUPT SENSITIVITY PB0 The external interrupt sensitivity is controlled by the ISxx bits of the MISCR1 miscellaneous register. This control allows to have two fully independent external interrupt source sensitivities.
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ST72334J/N, ST72314J/N, ST72124J MISCELLANEOUS REGISTERS (Cont’d) 13.3 REGISTERS DESCRIPTION MISCELLANEOUS REGISTER 1 (MISCR1) Read /Write Reset Value: 0000 0000 (00h) 7 IS11 0 IS10 MCO IS21 IS20 CP1 CP0 SMS Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: ei2 (port B3..0) and ei3 (port B7..4). These 2 bits can be written only when the I bit of the CC register is set to 1 (interrupt disabled).
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ST72334J/N, ST72314J/N, ST72124J MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read /Write Reset Value: 0000 0000 (00h) 7 0 - - BC1 BC0 - - SSM SSI Bit 7:6 = Reserved Must always be cleared Bit 5:4 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability.
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ST72334J/N, ST72314J/N, ST72124J 14 ON-CHIP PERIPHERALS 14.1 WATCHDOG TIMER (WDG) 14.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared. 14.1.
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ST72334J/N, ST72314J/N, ST72124J WATCHDOG TIMER (Cont’d) The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 11 .
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ST72334J/N, ST72314J/N, ST72124J WATCHDOG TIMER (Cont’d) Table 12. Watchdog Timer Register Map and Reset Values Address (Hex.
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ST72334J/N, ST72314J/N, ST72124J 14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) The Main Clock Controller consists of three different functions: ■ a programmable CPU clock prescaler ■ a clock-out signal to supply external devices ■ a real time clock timer with interrupt capability Each function can be used independently and simultaneously. 14.2.1 Programmable CPU clock prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals.
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ST72334J/N, ST72314J/N, ST72124J MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d) MISCELLANEOUS REGISTER 1 (MISCR1) See Section 13 on page 46. MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read /Write Reset Value: 0000 0001 (01h) 7 0 0 0 0 0 TB1 TB0 OIE Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has measured the selected elapsed time (TB1:0).
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ST72334J/N, ST72314J/N, ST72124J 14.3 16-BIT TIMER 14.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (input capture ) or generating up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 31.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS Byte LS Byte is buffered Other instructions Read At t0 +∆t LS Byte Returns the buffered LS Byte value at t0 Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 32. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK FFFD FFFE FFFF 0000 COUNTER REGISTER 0001 0002 0003 TIMER OVERFLOW FLAG (TOF) Figure 33. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000 0001 TIMER OVERFLOW FLAG (TOF) Figure 34.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 14.3.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected by the ICAPi pin (see figure 5). ICiR MS Byte ICiHR LS Byte ICiLR The ICiR register is a read-only register.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 35. Input Capture Block Diagram ICAP1 pin ICAP2 pin (Control Register 1) CR1 EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1 ICIE IEDG1 (Status Register) SR IC2R Register IC1R Register ICF1 ICF2 0 0 0 (Control Register 2) CR2 16-BIT 16-BIT FREE RUNNING CC1 CC0 IEDG2 COUNTER Figure 36.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 14.3.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 38. Output Compare Timing Diagram, fTIMER =fCPU/2 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 OUTPUT COMPARE REGISTER i (OCRi) 2ED3 OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) Figure 39.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 14.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 40. One Pulse Mode Timing Example COUNTER FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD 2ED3 ICAP1 OLVL2 OCMP1 OLVL1 OLVL2 compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 41.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 14.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 14.3.4 Low Power Modes Mode WAIT HALT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 14.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h) 7 0 Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 0 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 0 OCF1 TOF ICF2 OCF2 0 0 0 Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Table 15. 16-Bit Timer Register Map and Reset Values Address (Hex.
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ST72334J/N, ST72314J/N, ST72124J 14.4 SERIAL PERIPHERAL INTERFACE (SPI) 14.4.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. The SPI is normally used for communication between the microcontroller and external peripherals or another microcontroller.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 43.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4 Functional Description Figure 42 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer to the CR, SR and DR registers in Section 14.4.7for the bit definitions. 14.4.4.1 Master Configuration In a master configuration, the serial clock is generated on the SCK pin.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – For correct data transfer, the slave device must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure 45. – The SS pin must be connected to a low level signal during the complete byte transmit sequence.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses. The SS pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with the SPI transfer.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 45.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. – The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. – The MSTR bit is reset, thus forcing the device into slave mode.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: For more security, the slave device may respond to the master with the received data byte. Then the – Single Master System master will receive the previous byte back from the – Multimaster System slave device if all MISO and MOSI pins are connected and the slave has not written its DR register.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.5 Low Power Modes Mode WAIT HALT Description No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. 14.4.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE 0 SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1 or MODF=1 in the SR register Bit 6 = SPE Serial peripheral output enable. This bit is set and cleared by software.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF - - - DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined 0 7 - D7 Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register.
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) Table 17. SPI Register Map and Reset Values Address Register Label 7 6 5 4 3 2 1 0 0021h SPIDR Reset Value MSB x x x x x x x LSB x 0022h SPICR Reset Value SPIE 0 SPE 0 SPR2 0 MSTR 0 CPOL x CPHA x SPR1 x SPR0 x 0023h SPISR Reset Value SPIF 0 WCOL 0 0 MODF 0 0 0 0 0 (Hex.
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ST72334J/N, ST72314J/N, ST72124J 14.5 SERIAL COMMUNICATIONS INTERFACE (SCI) 14.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 14.5.
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 48.
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.5 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1.. It contains 6 dedicated registers: – Two control registers (CR1 & CR2) – A status register (SR) – A baud rate register (BRR) – An extended prescaler receiver register (ERPR) – An extended prescaler transmitter register (ETPR) Refer to the register descriptions in Section 0.1.8 for the definitions of each bit. 14.5.5.
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.5.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the CR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin.
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.5.3 Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, DR register consists in a buffer (RDR) between the internal bus and the received shift register (see Figure 1.).
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 50.
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.5.4 Conventional Baud Rate Generation than zero. The baud rates are calculated as follows: The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as fCPU fCPU follows: Rx = Tx = fCPU fCPU 16*ERPR 16*ETPR Rx = Tx = (32*PR)*RR (32*PR)*TR with: with: ETPR = 1,..,255 (see ETPR register) PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits) ERPR = 1,..
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.6 Low Power Modes Mode WAIT HALT Description No effect on SCI. SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. 14.5.
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 14.5.8 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE 0 TC RDRF IDLE OR NF FE - Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE =1 in the CR2 register.
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) 1: An SCI interrupt is generated whenever TC=1 in the SR register Read/Write Reset Value: Undefined Bit 5 = RIE Receiver interrupt enable. This bit is set and cleared by software. 7 0 0: interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1 R8 T8 M WAKE or RDRF=1 in the SR register Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1.
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data character, depending on whether it is read from or written to. 7 0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR).
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00 h) Allows setting of the Extended Prescaler rate division factor for the receive circuit. 7 0 EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (ETPR) Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate division factor for the transmit circuit.
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ST72334J/N, ST72314J/N, ST72124J 14.6 8-BIT A/D CONVERTER (ADC) 14.6.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 8-bit Data Register.
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ST72334J/N, ST72314J/N, ST72124J 8-BIT A/D CONVERTER (ADC) (Cont’d) 14.6.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than or equal to VDDA (high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication.
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ST72334J/N, ST72314J/N, ST72124J 8-BIT A/D CONVERTER (ADC) (Cont’d) 14.6.6 Register Description DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h) CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 CH2 CH1 0 7 CH0 D7 Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register.
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ST72334J/N, ST72314J/N, ST72124J 8-BIT A/D CONVERTER (ADC) (Cont’d) Table 19. ADC Register Map and Reset Values Address Register Label 7 6 5 4 3 2 1 0 0070h ADCDR Reset Value D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 0071h ADCCSR Reset Value COCO 0 0 ADON 0 0 CH3 0 CH2 0 CH1 0 CH0 0 (Hex.
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ST72334J/N, ST72314J/N, ST72124J 15 INSTRUCTION SET 15.
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ST72334J/N, ST72314J/N, ST72124J ST7 ADDRESSING MODES (Cont’d) 15.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
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ST72334J/N, ST72314J/N, ST72124J ST7 ADDRESSING MODES (Cont’d) 15.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.
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ST72334J/N, ST72314J/N, ST72124J 15.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions.
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ST72334J/N, ST72314J/N, ST72124J INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A=A+M+C A M H N Z C ADD Addition A=A+M A M H N Z C AND Logical And A=A.M A M N Z BCP Bit compare A, Memory tst (A .
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ST72334J/N, ST72314J/N, ST72124J INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg MUL Multiply X,A = X * A A, X, Y X, Y, A NEG Negate (2's compl) neg $10 reg, M NOP No Operation OR OR operation A=A+M A M POP Pop from the Stack pop reg reg M pop CC CC M M reg, CC H I N Z N Z 0 H C 0 I N Z N Z N Z C C PUSH Push onto the Stack push Y RCF Reset carry flag C
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ST72334J/N, ST72314J/N, ST72124J 16 ELECTRICAL CHARACTERISTICS 16.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. 16.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25°C and TA=TAmax (given by the selected temperature range).
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ST72334J/N, ST72314J/N, ST72124J 16.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi16.2.1 Voltage Characteristics Symbol VDD - VSS VDDA - VSSA VIN 1) & 2) |∆VDDx| and |∆VSSx| VDDX- VDDA |VSSA - VSSx| tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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ST72334J/N, ST72314J/N, ST72124J ABSOLUTE MAXIMUM RATINGS (Cont’d) 16.2.
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ST72334J/N, ST72314J/N, ST72124J 16.3 OPERATING CONDITIONS 16.3.1 General Operating Conditions Symbol VDD fOSC TA Parameter Conditions Min Max Unit V Supply voltage see Figure 55 and Figure 56 3.2 5.5 External clock frequency VDD≥3.5V for ROM devices VDD≥4.5V for FLASH devices 0 1) 16 VDD≥3.2V 0 1) 8 1 Suffix Version 0 70 6 Suffix Version -40 85 7 Suffix Version -40 105 3 Suffix Version -40 125 Ambient temperature range MHz °C Figure 55.
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ST72334J/N, ST72314J/N, ST72124J OPERATING CONDITIONS (Cont’d) 16.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for VDD, fOSC, and TA. Symbol Parameter Conditions High Threshold Med. Threshold Low Threshold VIT+ Reset release threshold (VDD rise) VIT- High Threshold Reset generation threshold (VDD fall) Med.
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ST72334J/N, ST72314J/N, ST72124J FUNCTIONAL OPERATING CONDITIONS (Cont’d) Figure 60. High LVD Threshold Versus VDD and fOSC for ROM devices 2) fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 8 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2.5 3 3.5 VIT-≥3.
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ST72334J/N, ST72314J/N, ST72124J 16.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total deSymbol vice consumption, the two current values must be added (except for HALT mode for which the clock is stopped). Parameter ∆IDD(∆Ta) Conditions Supply current variation vs.
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ST72334J/N, ST72314J/N, ST72124J SUPPLY CURRENT CHARACTERISTICS (Cont’d) 16.4.2 WAIT and SLOW WAIT Modes Parameter Typ 1) Max 2) fOSC=2MHz, fCPU=1MHz fOSC=4MHz, fCPU=2MHz fOSC=8MHz, fCPU=4MHz fOSC=16MHz, fCPU=8MHz 0.35 0.7 1.3 2.5 0.6 1.2 2.1 4.0 fOSC=2MHz, fCPU=62.5kHz fOSC=4MHz, fCPU=125kHz fOSC=8MHz, fCPU=250kHz fOSC=16MHz, fCPU=500kHz 0.05 0.1 0.2 0.5 0.1 0.2 0.4 1.
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ST72334J/N, ST72314J/N, ST72124J SUPPLY CURRENT CHARACTERISTICS (Cont’d) 16.4.3 HALT and ACTIVE-HALT Modes Symbol Parameter -40°C≤TA≤+85°C VDD=5.5V IDD Typ 1) Conditions -40°C≤TA≤+125°C -40°C≤TA≤+85°C Supply current in HALT mode 2) VDD=3.6V 16.4.
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ST72334J/N, ST72314J/N, ST72124J 16.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 16.5.1 General Timings Symbol tc(INST) tv(IT) Parameter Conditions Instruction cycle time Interrupt reaction time tv(IT) = ∆tc(INST) + 10 fCPU=8MHz 2) fCPU=8MHz Min Typ 1) Max Unit 2 3 12 tCPU 250 375 1500 ns 10 22 tCPU 1.25 2.75 µs 16.5.2 External Clock Source Symbol Parameter Conditions Min Typ Max VOSC1H OSC1 input pin high level voltage 0.
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ST72334J/N, ST72314J/N, ST72124J CLOCK AND TIMING CHARACTERISTICS (Cont’d) 16.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components.
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ST72334J/N, ST72314J/N, ST72124J CLOCK AND TIMING CHARACTERISTICS (Cont’d) 16.5.3.2 Typical Ceramic Resonators Symbol Parameter tSU(osc) Conditions Ceramic resonator start-up time Typ LP 2MHz 4.2 MP 4MHz 2.1 MS 8MHz 1.1 HS 16MHz 0.7 Unit ms Note: tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a quick VDD ramp-up from 0 to 5V (<50µs). Figure 69.
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ST72334J/N, ST72314J/N, ST72124J CLOCK AND TIMING CHARACTERISTICS (Cont’d) Table 22. Typical Ceramic Resonators Option Byte Config. fOSC (MHz) 1 LP 2 2 MP 4 4 MS 8 8 10 HS 12 162) CL1 Resonator Part Number1) [pF] CSB1000JA CSBF1000JA 3 CL2 [pF] 3 100 100 (47) (47) RFEXT RD kΩ [kΩ] 3.3 CSTS0200MGA06 CSTCC2.00MGA0H6 CSTS0200MGA06 CSTCC2.00MGA0H6 CSTS0400MGA06 CSTCC4.00MGA0H6 CSTS0400MGA06 CSTCC4.00MGA0H6 CSTS0800MGA06 Open CSTCC8.00MGA0H6 0 CSTS0800MGA06 CSTCC8.00MGA0H6 CST10.
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ST72334J/N, ST72314J/N, ST72124J CLOCK CHARACTERISTICS (Cont’d) 16.5.4 RC Oscillators The ST7 internal clock can be supplied with an RC oscillator. This oscillator can be used with internal Symbol Parameter Internal RC oscillator fOSC or external components (selectable by option byte). Conditions frequency 1) Min see Figure 71 Typ 3.60 5.
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ST72334J/N, ST72314J/N, ST72124J CLOCK CHARACTERISTICS (Cont’d) 16.5.5 Clock Security System (CSS) Symbol Parameter fSFOSC Safe Oscillator Frequency 1) fGFOSC Glitch Filtered Frequency 2) Min Typ Max TA=25°C, VDD=5.0V Conditions 250 340 550 TA=25°C, VDD=3.4V 190 260 450 30 Unit kHz MHz Figure 73. Typical Safe Oscillator Frequencies fosc [kHz] -40°C +85°C 400 +25°C +125°C 350 300 250 200 3.2 5.5 VDD [V] Note: 1.
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ST72334J/N, ST72314J/N, ST72124J 16.6 MEMORY CHARACTERISTICS 16.6.1 RAM and Hardware Registers Symbol VRM Parameter Data retention mode Conditions 1) HALT mode (or RESET) Min Typ Max 1.6 Unit V 16.6.2 EEPROM Data Memory Symbol Parameter tprog Programming time for 1~16 bytes 3) tret NRW Conditions Write erase cycles Max 20 -40°C≤TA≤+125°C 25 TA=+25°C 5) Typ -40°C≤TA≤+85°C TA=+55°C 4) Data retention 5) Min Unit ms 20 Years 300 000 Cycles 16.6.
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ST72334J/N, ST72314J/N, ST72124J 16.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 16.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).
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ST72334J/N, ST72314J/N, ST72124J EMC CHARACTERISTICS (Cont’d) 16.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the AN1181 ST7 application note. 16.7.2.
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ST72334J/N, ST72314J/N, ST72124J EMC CHARACTERISTICS (Cont’d) 16.7.2.2 Static and Dynamic Latch-Up ■ LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable I/O pin) and a power supply switch sequence are performed on each sample. This test conforms to the EIA/ JESD 78 IC latch-up standard.
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ST72334J/N, ST72314J/N, ST72124J EMC CHARACTERISTICS (Cont’d) 16.7.3 ESD Pin Protection Strategy To protect an integrated circuit against ElectroStatic Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. The stress generally affects the circuit elements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress.
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ST72334J/N, ST72314J/N, ST72124J EMC CHARACTERISTICS (Cont’d) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode to VDD are not implemented. An additional local protection between the pad and VSS (5a & 5b) is implemented to completely absorb the positive ESD discharge. Multisupply Configuration When several types of ground (VSS, VSSA, ...) and power supply (VDD, VDDA, .
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ST72334J/N, ST72314J/N, ST72124J 16.8 I/O PORT PIN CHARACTERISTICS 16.8.1 General Characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol Parameter Conditions Min Typ 1) 2) VIL Input low level voltage VIH Input high level voltage 2) Vhys Schmitt trigger voltage hysteresis 3) Max 0.3xVDD 0.
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ST72334J/N, ST72314J/N, ST72124J I/O PORT PIN CHARACTERISTICS (Cont’d) 16.8.2 Output Driving Current Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol Parameter Conditions Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 84 and Figure 87) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 85 and Figure 88) VOH 2) Max TA≤85°C TA≥85°C 1.3 1.
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ST72334J/N, ST72314J/N, ST72124J I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 87. Typical VOL vs. VDD (standard I/Os) Vol [V] at Iio=2mA Ta=-40°C Ta=85°C Ta=25°C Ta=125°C 0.5 0.45 0.4 0.35 0.3 0.25 0.2 3.2 3.5 4 4.5 5 Vol [V] at Iio=5mA 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 3.2 5.5 3.5 Ta=-40°C Ta=85°C Ta=25°C Ta=125°C 4 4.5 5 5.5 Vdd [V] Vdd [V] Figure 88. Typical VOL vs.
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ST72334J/N, ST72314J/N, ST72124J 16.9 CONTROL PIN CHARACTERISTICS 16.9.1 Asynchronous RESET Pin Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol Parameter Conditions Min Typ 1) 2) VIL Input low level voltage VIH Input high level voltage 2) Vhys Schmitt trigger voltage hysteresis 3) voltage 4) 0.
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ST72334J/N, ST72314J/N, ST72124J CONTROL PIN CHARACTERISTICS (Cont’d) Figure 91. Typical ION vs. VDD with VIN=VSS Figure 92. Typical VOL at VDD=5V (RESET) Ion [µA] Vol [V] at Vdd=5V 200 Ta=-40°C Ta=85°C Ta=25°C Ta=125°C Ta=-40°C Ta=85°C Ta=25°C Ta=125°C 2 150 1.5 100 1 50 0.5 0 0 3.2 3.5 4 4.5 5 0 5.5 1 2 3 4 5 6 7 8 Iio [mA] Vdd [V] Figure 93. Typical VOL vs. VDD (RESET) Vol [V] at Iio=2mA Ta=-40°C Ta=85°C Vol [V] at Iio=5mA Ta=-40°C Ta=85°C Ta=25°C Ta=125°C 1.
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ST72334J/N, ST72314J/N, ST72124J CONTROL PIN CHARACTERISTICS (Cont’d) 16.9.2 ISPSEL Pin Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol VIL Parameter Input low level voltage 1) VIH Input high level voltage 1) IL Input leakage current Conditions Min Max VSS 0.2 VDD-0.1 12.6 VIN=VSS ±1 Unit V µA Figure 94. Two typical Applications with ISPSEL Pin 2) ISPSEL ST72XXX ISPSEL PROGRAMMING TOOL 10kΩ ST72XXX Notes: 1.
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ST72334J/N, ST72314J/N, ST72124J 16.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). 16.10.1 Watchdog Timer Symbol tw(WDG) Parameter Watchdog time-out duration Conditions fCPU=8MHz Max Unit 12,288 Min Typ 786,432 tCPU 1.54 98.3 ms Max Unit 16.10.
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ST72334J/N, ST72314J/N, ST72124J 16.11 COMMUNICATION INTERFACE CHARACTERISTICS 16.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified. Symbol Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
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ST72334J/N, ST72314J/N, ST72124J COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 96. SPI Slave Timing Diagram with CPHA=11) SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) MISO OUTPUT see note 2 tv(SO) th(SO) MSB OUT HZ tsu(SI) BIT6 OUT LSB OUT see note 2 th(SI) MSB IN MOSI INPUT tdis(SO) tr(SCK) tf(SCK) Figure 97.
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ST72334J/N, ST72314J/N, ST72124J COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d) 16.11.2 SCI - Serial Communications Interface Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI and TDO). Conditions Symbol Parameter fCPU fTx fRx Accuracy vs. Standard ~0.16% Communication frequency 8MHz ~0.
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ST72334J/N, ST72314J/N, ST72124J 16.12 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
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ST72334J/N, ST72314J/N, ST72124J 8-BIT ADC CHARACTERISTICS (Cont’d) ADC Accuracy Symbol VDD=5V, 2) fCPU=1MHz Parameter Typ. |ET| EO Max Total unadjusted error 1) Offset error 1) 1) VDD=5.0V, 3) fCPU=8MHz Typ. Max VDD=3.3V, 3) fCPU=8MHz Typ Unit Max 2.0 2.0 2.0 1.5 1.5 1.5 EG Gain Error 1.5 1.5 1.5 |ED| Differential linearity error 1) 1.5 1.5 1.5 |EL| Integral linearity error 1) 1.5 1.5 1.5 LSB Figure 99.
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ST72334J/N, ST72314J/N, ST72124J 17 PACKAGE CHARACTERISTICS 17.1 PACKAGE MECHANICAL DATA Figure 100. 64-Pin Thin Quad Flat Package D A D1 A2 mm Dim. Min Typ A A1 b e E1 E L Min Typ Max 1.60 0.063 0.15 0.002 0.006 A1 0.05 A2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 D 16.00 0.630 D1 14.00 0.551 E 16.00 0.630 E1 14.00 0.551 e 0.80 0.031 θ 0° L 0.45 3.5° 7° 0° 3.5° 7° 0.60 0.75 0.018 0.024 0.030 1.
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ST72334J/N, ST72314J/N, ST72124J PACKAGE MECHANICAL DATA (Cont’d) Figure 102. 44-Pin Thin Quad Flat Package b e c L1 Min inches Max Min Typ Max 1.60 0.063 0.15 0.002 0.006 A1 0.05 A2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 C 0.09 0.20 0.004 0.000 0.008 D 12.00 0.472 D1 10.00 0.394 E 12.00 0.472 E1 10.00 0.394 e 0.80 0.031 θ 0° L 0.45 3.5° 7° 0° h 3.5° 7° 0.60 0.75 0.018 0.024 0.030 1.00 L1 L Typ A A1 E1 E mm Dim.
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ST72334J/N, ST72314J/N, ST72124J Symbol Ratings Value RthJA Package thermal resistance (junction to ambient) TQFP64 SDIP56 TQFP44 SDIP42 60 45 52 55 PD TJmax °C/W Power dissipation 1) 500 mW Maximum junction temperature 2) 150 °C and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.
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ST72334J/N, ST72314J/N, ST72124J 17.2 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines in Figure 105 and Figure 106. Recommended glue for SMD plastic packages dedicated to molding compound with silicone: ■ Heraeus: PD945, PD955 ■ Loctite: 3615, 3298 Figure 105. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) 250 200 150 Temp.
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ST72334J/N, ST72314J/N, ST72124J 18 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (ROM). E2PROM data memory and FLASH devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured.
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ST72334J/N, ST72314J/N, ST72124J DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) 18.2 TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents and the list of the selected options (if any). The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .S19 format generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended.
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ST72334J/N, ST72314J/N, ST72124J MICROCONTROLLER OPTION LIST Customer: Address: ................................................................................... ................................................................................... Contact: ................................................................................... Phone No: ................................................................................... Reference/ROM code*:. . . . . . . . . . . . . . . . . . . . . . . . . . .
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ST72334J/N, ST72314J/N, ST72124J 18.3 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtain from the STMicroelectronics Internet site: ➟ http//mcu.st.com. Tools from these manufacturers include C compliers, emulators and gang programmers.
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ST72334J/N, ST72314J/N, ST72124J DEVELOPMENT TOOLS (Cont’d) 18.3.1 Suggested List Of Socket Types Table 28. Suggested List of TQFP64 Socket Types Package / Probe TQFP64 EMU PROBE Adaptor / Socket Reference Socket type ENPLAS OTQ-64-0.8-02 Open Top YAMAICHI IC51-0644-1240.KS-14584 Clamshell YAMAICHI IC149-064-008-S5 SMC Suggested List of TQFP44 Socket Types Package / Probe TQFP44 TQFP44 EMU PROBE 148/153 Adaptor / Socket Reference Socket type ENPLAS OTQ-44-0.
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ST72334J/N, ST72314J/N, ST72124J 18.
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ST72334J/N, ST72314J/N, ST72124J IDENTIFICATION AN 982 AN1014 AN1015 AN1040 AN1070 AN1324 AN1477 AN1502 AN1529 DESCRIPTION USING ST7 WITH CERAMIC RESONATOR HOW TO MINIMIZE THE ST7 POWER CONSUMPTION SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES ST7 CHECKSUM SELF-CHECKING CAPABILITY CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS EMULATED DATA EEPROM WITH XFLASH MEMORY EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
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ST72334J/N, ST72314J/N, ST72124J 19 IMPORTANT NOTES 19.1 SCI Baud rate registers Caution: The SCI baud rate register (SCIBRR) MUST NOT be written to (changed or refreshed) while the transmitter or the receiver is enabled.
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ST72334J/N, ST72314J/N, ST72124J 20 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Revision Main changes Date Replaced Note by Caution in “Conventional Baud Rate Generation” on page 91 2.
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ST72334J/N, ST72314J/N, ST72124J Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.