Datasheet

ST72334J/N, ST72314J/N, ST72124J
14/153
REGISTER & MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Address Block
Register
Label
Register Name
Reset
Status
Remarks
0000h
0001h
0002h
Port A
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
1)
00h
00h
R/W
R/W
R/W
2)
0003h Reserved Area (1 Byte)
0004h
0005h
0006h
Port C
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h
1)
00h
00h
R/W
R/W
R/W
0007h Reserved Area (1 Byte)
0008h
0009h
000Ah
Port B
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
1)
00h
00h
R/W
R/W
R/W
2)
000Bh Reserved Area (1 Byte)
000Ch
000Dh
000Eh
Port E
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h
1)
00h
00h
R/W
R/W
R/W
2)
000Fh Reserved Area (1 Byte)
0010h
0011h
0012h
Port D
PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h
1)
00h
00h
R/W
R/W
R/W
2)
0013h Reserved Area (1 Byte)
0014h
0015h
0016h
Port F
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h
1)
00h
00h
R/W
R/W
R/W
0017h
to
001Fh
Reserved Area (9 Bytes)
0020h MISCR1 Miscellaneous Register 1 00h R/W
0021h
0022h
0023h
SPI
SPIDR
SPICR
SPISR
SPI Data I/O Register
SPI Control Register
SPI Status Register
xxh
0xh
00h
R/W
R/W
Read Only
0024h
to
0028h
Reserved Area (5 Bytes)
0029h MCC MCCSR Main Clock Control / Status Register 01h R/W