Datasheet

ST72334J/N, ST72314J/N, ST72124J
57/153
16-BIT TIMER (Cont’d)
Figure 32. Counter Timing Diagram, internal clock divided by 2
Figure 33. Counter Timing Diagram, internal clock divided by 4
Figure 34. Counter Timing Diagram, internal clock divided by 8
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
CPU CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC FFFD 0000 0001
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC FFFD
0000