Datasheet

ST72334J/N, ST72314J/N, ST72124J
59/153
16-BIT TIMER (Cont’d)
Figure 35. Input Capture Block Diagram
Figure 36. Input Capture Timing Diagram
ICIE
CC0
CC1
16-BIT FREE RUNNING
COUNTER
IEDG1
(Control Register 1) CR1
(Control Register 2) CR2
ICF2ICF1 000
(Status Register) SR
IEDG2
ICAP1
ICAP2
EDGE DETECT
CIRCUIT2
16-BIT
IC1R Register
IC2R Register
EDGE DETECT
CIRCUIT1
pin
pin
FF01 FF02 FF03
FF03
TIMER CLOCK
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: Active edge is rising edge.