Datasheet

ST72334J/N, ST72314J/N, ST72124J
77/153
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 45. Data Clock Timing Diagram
CPOL = 1)
CPOL = 0)
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =1
CPOL = 1
CPOL = 0
MSBit Bit 6 Bit 5
Bit 4 Bit3 Bit 2 Bit 1 LSBit
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MISO
(from master)
MOSI
SS
(to slave)
CAPTURE STROBE
CPHA =0
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
(from slave)
VR02131B
MSBit Bit 6 Bit 5
Bit 4 Bit3 Bit 2 Bit 1 LSBit
MSBit Bit 6 Bit 5
Bit 4 Bit3 Bit 2 Bit 1 LSBit
SCLK (with
SCLK (with