Specifications

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
127/141
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
13.11.2 I
2
C - Inter IC Control Interface
Subject to general operating conditions for V
DD
,
f
OSC
, and T
A
unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SDAI and SCLI). The ST7 I
2
C interface meets the
requirements of the Standard I
2
C communication
protocol described in the following table.
Figure 94. Typical Application with I
2
C Bus and Timing Diagram
4)
Notes:
1. Data based on standard I
2
C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
Symbol Parameter
Standard mode I
2
C Fast mode I
2
C
Unit
Min
1)
Max
1)
Min
1)
Max
1)
t
w(SCLL)
SCL clock low time 4.7 1.3
µs
t
w(SCLH)
SCL clock high time 4.0 0.6
t
su(SDA)
SDA setup time 250 100
ns
t
h(SDA)
SDA data hold time 0
3)
0
2)
900
3)
t
r(SDA)
t
r(SCL)
SDA and SCL rise time 1000 20+0.1C
b
300
t
f(SDA)
t
f(SCL)
SDA and SCL fall time 300 20+0.1C
b
300
t
h(STA)
START condition hold time 4.0 0.6
µs
t
su(STA)
Repeated START condition setup time 4.7 0.6
t
su(STO)
STOP condition setup time 4.0 0.6 ns
t
w(STO:STA)
STOP to START condition time (bus free) 4.7 1.3 ms
C
b
Capacitive load for each bus line 400 400 pF
REPEATED START
START
STOP
START
t
f(SDA)
t
r(SDA)
t
su(SDA)
t
h(SDA)
t
f(SCK)
t
r(SCK)
t
w(SCKL)
t
w(SCKH)
t
h(STA)
t
su(STO)
t
su(STA)
t
w(STO:STA)
SDA
SCK
4.7kΩ
SDAI
ST72XXX
SCLI
V
DD
100Ω
100Ω
V
DD
4.7kΩ
I
2
CBUS